Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched, the layer to be etched comprising a first region and a second region; forming a plurality of first core layers separated along a first direction parallel to a substrate surface on the first region; forming a plurality of second core layers separated along a second direction parallel to the substrate surface on the second region, wherein the second dimension of adjacent second core layers is greater than the first dimension of adjacent first core layers; forming a spacer material layer on the sidewall surfaces and top surfaces of the first and second core layers; etching the spacer material layer using a first etching process to form a first spacer on the sidewall of the first core layer, the first spacer having a first dimension in the first direction; etching the spacer material layer using a second etching process to form a second spacer on the sidewall of the second core layer, the second spacer having a second dimension in the first direction and being greater than the first dimension; and etching the layer to be etched using the first and second spacers. The semiconductor structure formed by this method has a good morphology.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the continuous development of semiconductor process technology, fin field-effect transistors (Fin FETs) are widely used in the field of semiconductor manufacturing due to their superior performance, namely, the ability to improve circuit control, reduce leakage current, and shorten the gate length of transistors.

[0003] As a key structure in FinFETs, the fin structure significantly impacts the performance of FinFETs. As technology nodes continue to decrease, it is necessary to form fin structures of different sizes and pitches on the same chip to meet device requirements.

[0004] However, the existing process for forming fin structures with different sizes and pitches needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the process of forming fin structures with different size pitches.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, wherein the layer to be etched includes a first region and a second region; forming a plurality of discrete first core layers on the first region, wherein the plurality of first core layers are arranged along a first direction, wherein the first direction is parallel to the surface of the substrate; forming a plurality of discrete second core layers on the second region, wherein the plurality of second core layers are arranged along the first direction, wherein the second size of adjacent second core layers is greater than the first size of adjacent first core layers, wherein the first size includes the size of the first core layers along the first direction and the spacing between adjacent first core layers, and the second size includes the spacing of the second core layers along the first direction. size and the spacing between adjacent second core layers; forming a sidewall material layer on the sidewall surface and top surface of the first core layer, and on the sidewall surface and top surface of the second core layer; using a first etching process to etch the sidewall material layer on the sidewall surface and top surface of the first core layer, forming a first sidewall on the sidewall of the first core layer, and the first sidewall has a first size in the first direction; using a second etching process to etch the sidewall material layer on the sidewall surface and top surface of the second core layer, forming a second sidewall on the sidewall of the second core layer, and the second sidewall has a second size in the first direction, and the second size is larger than the first size; etching the layer to be etched with the first sidewall and the second sidewall.

[0007] Optionally, the first etching process includes an anisotropic dry etching process.

[0008] Optionally, the second etching process includes a multi-cycle etching process, and the etching process includes: passivating the side wall material layer on the top surface of the second core layer to form a passivation layer on the top surface of the side wall material layer; after the passivation layer is formed, modifying the side wall material layer at the bottom of the passivation layer and the top surface of the second core layer to form a modified layer on the top surface of the side wall material layer; and removing the modified layer.

[0009] Optionally, the sidewall material layer on the sidewall surface and top surface of the second core layer includes a first part and a second part located on the first part, the first part is located on the sidewall of the second core layer, the bottom plane of the second part is flush with the top plane of the second core layer, the second part includes a first region and a second region located on both sides of the first region, the first region is located on the surface of the second core layer, the second region is connected to the first part, and the size of the second region in the first direction gradually increases along the second direction, and the second direction is perpendicular to the surface of the layer to be etched; the passivation layer is located on the top surface of the second part.

[0010] Optionally, the thickness of the passivation layer on the top surface of the second region is greater than the thickness of the passivation layer on the top surface of the first region.

[0011] Optionally, the process of modifying the sidewall material layer at the bottom of the passivation layer includes hydrogenation treatment; the process parameters of the hydrogenation treatment include: the gas is a mixed gas of hydrogen, ammonia and methane; the bias power is 100 watts to 300 watts.

[0012] Optionally, the thickness of the modified layer on the top surface of the second region is smaller than the thickness of the modified layer on the top surface of the first region.

[0013] Optionally, the process of removing the modified layer includes a dry etching process; the process parameters of the dry etching process include: the gas includes a mixed gas of hydrogen, methane, ammonia, nitrogen trifluoride and carbon tetrafluoride; the pressure is 300 mTorr to 600 mTorr; and the ion source power is 500 W to 1500 W.

[0014] Optionally, the material of the sidewall material layer includes silicon oxide.

[0015] Optionally, the process of passivating the top surface of the side wall material layer includes a nitridation process; the parameters of the nitridation process include: the gas includes a mixture of argon, nitrogen and helium; the ion source power is 800 watts to 1500 watts; the bias power is 100 watts to 800 watts; and the pressure is 3 mTorr to 40 mTorr.

[0016] Optionally, the material of the spacer material layer includes silicon nitride.

[0017] Optionally, the process of passivating the top surface of the side wall material layer includes an oxidation treatment process; the parameters of the oxidation treatment process include: the gas includes a mixture of argon, oxygen and helium; the ion source power is 800 watts to 1000 watts; the bias power is 100 watts to 500 watts; and the pressure is 3 mTorr to 15 mTorr.

[0018] Optionally, the time for passivation treatment of the side wall material layer on the top surface of the second core layer is the first time, and the time for modification treatment of the side wall material layer at the bottom of the passivation layer and the top surface of the second core layer is the second time, and the ratio range of the first time and the second time is: 2:1 to 5:1.

[0019] Optionally, the second sidewall includes an effective area arranged along a direction perpendicular to the surface of the layer to be etched and an ineffective area located on the effective area, and the top surface of the ineffective area is an inclined surface having an angle with the direction parallel to the surface of the layer to be etched.

[0020] Optionally, the layer to be etched includes: a substrate; a first hard mask layer located on the substrate; a core material layer located on the first hard mask layer; and a second hard mask layer located on the core material layer.

[0021] Optionally, after forming the first side wall and the second side wall, the process further includes: etching the second hard mask layer and the core material layer using the first side wall and the second side wall as masks to form a third core layer on the first hard mask layer in the first region, and forming a fourth core layer on the first hard mask layer in the second region; forming a third side wall on the side wall of the third core layer, and forming a fourth side wall on the side wall of the fourth core layer; etching the first hard mask layer and the substrate using the third side wall and the fourth side wall as masks to form a base, a plurality of first fins located on the first region of the substrate, and a plurality of second fins located on the second region of the substrate, and the spacing between adjacent second fins is greater than the spacing between adjacent first fins.

[0022] Optionally, the method further includes: shrinking the first fin, so that the size of the first fin in the first direction is smaller than the size of the second fin in the first direction.

[0023] Optionally, the material of the first core layer and the material of the second core layer are different from the material of the second hard mask layer; the material of the first side wall and the material of the second side wall are different from the material of the second hard mask layer; the material of the first side wall and the material of the second side wall are different from the material of the first core layer and the material of the second core layer.

[0024] Optionally, the material of the first core layer and the material of the second core layer include silicon; and the material of the second hard mask layer includes silicon oxide or silicon nitride.

[0025] Optionally, the material of the third core layer and the material of the fourth core layer are the same as the material of the first core layer and the material of the second core layer; the material of the first hard mask layer is the same as the material of the second hard mask layer; the material of the third side wall and the material of the fourth side wall are the same as the material of the first side wall and the material of the second side wall.

[0026] Optionally, a first height is provided from the top plane of the first sidewall to the surface of the layer to be etched, and a second height is provided from the top plane of the second sidewall to the surface of the layer to be etched, and the second height is greater than the first height.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] The technical solution of the present invention forms a first sidewall spacer by etching the sidewall material layer on the sidewall and top surfaces of the first core layer using a first etching process. The first sidewall spacer has a first dimension in a first direction. The second sidewall spacer has a second dimension in the first direction, and the second dimension is larger than the first dimension. The sidewall material layer on the sidewall and top surfaces of the first core layer and the sidewall material layer on the sidewall and top surfaces of the second core layer are formed simultaneously. The sidewall material layer on the sidewall and top surfaces of the first core layer and the sidewall material layer on the sidewall and top surfaces of the second core layer are etched using different etching processes, respectively, to obtain first and second sidewall spacers of different dimensions. This eliminates the need for a separate etching process to reduce the size of the first sidewall spacer. The first sidewall spacer can be formed using a single etching process, resulting in minimal damage to the first sidewall spacer, better morphology, and higher dimensional accuracy. This is beneficial for improving the morphology and performance of subsequently formed semiconductor structures.

[0029] Furthermore, the etching process includes passivating the spacer material layer on the top surface of the second core layer, forming a passivation layer on the top surface of the spacer material layer, wherein the thickness of the passivation layer on the top surface of the second region is greater than the thickness of the passivation layer on the top surface of the first region. Therefore, when the spacer material layer at the bottom of the passivation layer is modified, the thickness of the passivation layer on the top surface of the first region is relatively thin, so that plasma in the modification process can more easily pass through the passivation layer on the top surface of the first region to modify the spacer material layer at the bottom of the passivation layer. The thickness of the passivation layer on the top surface of the second region is relatively thick, so that plasma in the modification process can less easily pass through the passivation layer on the top surface of the second region to modify the spacer material layer at the bottom of the passivation layer, thereby resulting in the thickness of the modified layer formed on the top surface of the second region being less than the thickness of the modified layer on the top surface of the first region. Therefore, when removing the modified layer, the thickness loss of the first region of the spacer material layer is greater, while the thickness loss of the second region of the spacer material layer is less, resulting in a smaller loss in the height of the formed second spacer. Furthermore, the etching process etches the surface of the spacer material layer parallel to the substrate surface to a much greater extent than the surface of the spacer material layer on the sidewall surface of the second core layer, resulting in a smaller loss in the dimensional size of the formed second spacer in the first direction. In summary, this ensures that the second dimension of the formed second spacer is greater than the first dimension of the first spacer, meeting design requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0031] Figures 4 to 13 is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0032] Figure 14 It is a cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the existing process for forming fin structures with different sizes and pitches needs to be improved.

[0034] Figures 1 to 3 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0035] Please refer to Figure 1, providing a layer to be etched 100, wherein the layer to be etched 100 includes a first region I and a second region II; forming a plurality of discrete first core layers 101 on the first region I, wherein the plurality of first core layers 101 are arranged along a first direction parallel to the surface of the substrate 100; forming a plurality of discrete second core layers 201 on the second region II, wherein the plurality of second core layers 201 are arranged along the first direction, and a distance between adjacent second core layers 201 is greater than a distance between adjacent first core layers 101.

[0036] Please refer to Figure 2 An initial first spacer 103 is formed on the sidewall surface of the first core layer 101 , and a second spacer 203 is formed on the sidewall surface of the second core layer 201 .

[0037] Please refer to Figure 3 The initial first sidewall 103 is shrunk to form a first sidewall 104 , wherein the size of the first sidewall 104 in the first direction is smaller than the size of the second sidewall 203 in the first direction.

[0038] During the formation of the semiconductor structure, the patterns of the first sidewall 104 and the second sidewall 203 are continuously transferred downward to form a core layer again in the layer to be etched, and then a new pattern is formed using a double pattern alignment technique, and then the new pattern is used as a mask to form a first fin located in the first region and a second fin in the second region. The first region I and the second region II are used to form different device structures, and the device structure on the second region II requires a larger fin spacing. If the first sidewall 104 and the second sidewall 203 are the same size, the partial spacing between the formed first fin and the second fin is also the same. In order to make the spacing range between the second fins on the second region larger than the spacing range between the first fins, the initial first sidewall 103 formed at the same time as the second sidewall 203 needs to be reduced to form a first sidewall 104 with a smaller size. An isotropic dry etching process is usually used to reduce the initial first sidewall 103.

[0039] However, the shrinking process easily causes the initial first sidewall 103 to be damaged, tilted, or even collapsed. When the pattern is subsequently transferred downward, the morphology and dimensional accuracy of the formed first fin are difficult to control, thereby affecting the performance of the semiconductor structure.

[0040] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure. A first sidewall is formed by etching a sidewall material layer on the sidewall and top surfaces of a first core layer using a first etching process. The first sidewall has a first dimension in a first direction. A second sidewall is formed by etching a sidewall material layer on the sidewall and top surfaces of a second core layer using a second etching process. The second sidewall has a second dimension in the first direction, and the second dimension is greater than the first dimension. Different etching processes are used to etch the sidewall material layer on the sidewall and top surfaces of the first core layer and the sidewall material layer on the sidewall and top surfaces of the second core layer, respectively, to obtain first and second sidewalls of different dimensions. This eliminates the need for further etching processes to reduce the size of the first sidewall. The first sidewall can be formed using a single etching process, resulting in minimal damage to the first sidewall, a better morphology, and high dimensional accuracy. This is beneficial for improving the morphology and performance of subsequently formed semiconductor structures.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 13 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0043] Please refer to Figure 4 , providing a layer to be etched, wherein the layer to be etched includes a first region I and a second region II.

[0044] The layer to be etched includes: a substrate 200 ; a first hard mask layer 210 located on the substrate 200 ; a core material layer 211 located on the first hard mask layer 210 ; and a second hard mask layer 212 located on the core material layer 211 .

[0045] The substrate 200 is made of a semiconductor material. In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multinary semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] The first hard mask layer 210 is used to improve the accuracy of the pattern transfer when the pattern formed by the subsequent core material layer 211 is transferred to the substrate 200; the second hard mask layer 212 is used to improve the accuracy of the pattern transfer when the pattern formed on the second hard mask layer 212 is transferred to the substrate 200.

[0047] The material of the first hard mask layer 210 is different from that of the core material layer 211, and the material of the second hard mask layer 212 is different from that of the core material layer 211. Therefore, the first hard mask layer 210 and the core material layer 211 have different etching selectivities, and the second hard mask layer 212 and the core material layer 211 have different etching selectivities, thereby improving the accuracy of pattern transfer.

[0048] The material of the first hard mask layer 210 includes silicon oxide, silicon, nitride, and nitride carbide, and the nitride or nitride carbide includes silicon nitride or silicon nitride carbide; the material of the second hard mask layer 212 includes silicon oxide, silicon, nitride, and nitride carbide, and the nitride or nitride carbide includes silicon nitride or silicon nitride carbide; the material of the core material layer 211 includes silicon oxide, silicon, nitride, and nitride carbide, and the nitride or nitride carbide includes silicon nitride or silicon nitride carbide.

[0049] In this embodiment, the material of the first hard mask layer 210 is the same as that of the second hard mask layer 212 .

[0050] In this embodiment, the material of the first hard mask layer 210 and the second hard mask layer 212 includes silicon nitride; and the material of the core material layer 211 includes silicon.

[0051] In another embodiment, the material of the first hard mask layer and the material of the second hard mask layer include silicon oxide.

[0052] Please continue to refer to Figure 4 , a plurality of discrete first core layers 301 are formed on the first region I, and the plurality of first core layers 301 are arranged along a first direction X, and the first direction X is parallel to the surface of the substrate 200; a plurality of discrete second core layers 302 are formed on the second region II, and the plurality of second core layers 302 are arranged along the first direction X, and a second dimension d2 of adjacent second core layers 302 is greater than a first dimension d1 of adjacent first core layers 301.

[0053] The first dimension d1 includes the dimension of the first core layer 301 along the first direction X and the spacing between adjacent first core layers 301 ; the second dimension d2 includes the dimension of the second core layer 302 along the first direction X and the spacing between adjacent second core layers 302 .

[0054] The second dimension d2 of the adjacent second core layer 302 is greater than the first dimension d1 of the adjacent first core layer 301, so that the spacing of the second sidewalls subsequently formed in the second area II is greater than the spacing of the first sidewalls formed in the first area I. After the pattern continues to be transferred, the spacing of the second fins formed in the second area II is greater than the spacing of the first fins formed in the first area I, so as to meet the design requirements of the device.

[0055] The first core layer 301 and the second core layer 302 are formed simultaneously.

[0056] The material of the first core layer 301 and the material of the second core layer 302 are different from the material of the second hard mask layer 212 , so that the second hard mask layer 212 is less damaged when the material of the first core layer 301 and the second core layer 302 are formed.

[0057] In this embodiment, the material of the first core layer 301 and the material of the second core layer 302 include silicon.

[0058] Please refer to Figure 5 A spacer material layer 303 is formed on the sidewall surface and the top surface of the first core layer 301 and the sidewall surface and the top surface of the second core layer 302 .

[0059] The sidewall material layer 303 on the sidewall surface and top surface of the second core layer 302 includes a first part A and a second part B located on the first part A, the first part A is located on the sidewall of the second core layer 302, the bottom plane of the second part B is flush with the top plane of the second core layer 302, the second part B includes a first area B1 and a second area B2 located on both sides of the first area B1, the first area B1 is located on the surface of the second core layer 302, the second area B2 is connected to the first part A, and the size of the second area B2 in the first direction X gradually increases along the second direction Y, and the second direction Y is perpendicular to the surface of the layer to be etched.

[0060] In this embodiment, the process of forming the side wall material layer 303 includes an atomic layer deposition process. The step coverage rate of the atomic layer deposition process is good, and the thickness distribution of the formed side wall material layer 303 is uniform, so that the formed side wall material layer 303 has the above-mentioned different first part A and the second part B located on the first part A.

[0061] The material of the spacer material layer 303 is different from that of the second hard mask layer 212; the material of the spacer material layer 303 is different from that of the first core layer 301 and the second core layer 302. Therefore, when the spacer material layer 303 is subsequently etched to form the first and second spacers, the etching process causes minimal damage to the second hard mask layer 212, the material of the first core layer 301, and the second core layer 302.

[0062] In this embodiment, the material of the spacer material layer 303 includes silicon oxide.

[0063] In another embodiment, the material of the spacer material layer includes silicon nitride.

[0064] Please refer to Figure 6, a first etching process is used to etch the side wall surface and the top surface of the side wall material layer 303 of the first core layer 301, and a first side wall 304 is formed on the side wall of the first core layer 301. The first side wall 304 has a first size P1 in the first direction X, and the top plane of the first side wall 304 has a first height to the surface of the layer to be etched.

[0065] The first etching process includes an anisotropic dry etching process.

[0066] In this embodiment, the material of the spacer material layer 303 includes silicon nitride, and the process parameters of the anisotropic dry etching process include: the gas includes carbon, hydrogen and fluorine gas.

[0067] In other embodiments, the material of the spacer material layer includes silicon oxide, and the process parameters of the anisotropic dry etching process include: the gas includes carbon fluorine gas.

[0068] The anisotropic dry etching process has a low selectivity ratio between etching the spacer material layer 303 on the top surface of the first core layer 301 and etching the spacer material layer 303 on the sidewall surface of the first core layer 301. That is, when the anisotropic dry etching process etches the spacer material layer 303 on the top surface of the first core layer 301, the spacer material layer 303 on the sidewall surface of the first core layer 301 is also etched, so that the first dimension P1 of the formed first spacer 304 has a large dimensional loss compared with the thickness of the spacer material layer 303. At the same time, the first height of the first spacer 304 also has a dimensional loss compared with the height of the first core layer 301, so that the first dimension P1 of the formed first spacer 304 is smaller than the second dimension of the subsequently formed second spacer. Therefore, there is no need to use another etching process to reduce the first spacer 304. The first spacer 304 can be formed by only one etching process, so that the first spacer 304 is less damaged, has a better morphology, and has a higher dimensional accuracy.

[0069] After forming the first spacer 304 , the first core layer 301 is removed; alternatively, after forming the second spacer, the first core layer 301 and the second core layer 302 are removed simultaneously.

[0070] In this embodiment, when the sidewall material layer 303 on the top surface and the sidewall surface of the first core layer 301 is etched using the first etching process, a covering layer (not shown) is also formed on the second region II, and the covering layer is used to protect the sidewall material layer 303 on the second region II.

[0071] After forming the first spacer 304 , the cover layer is removed.

[0072] Next, a second etching process is used to etch the sidewall surface and the top surface of the second core layer 302 of the spacer material layer 303, and a second spacer 307 is formed on the sidewall of the second core layer 302. The second spacer 307 has a second size P2 in the first direction X, and the second size P2 is larger than the first size P1. The formation process of the second spacer 307 is shown in FIG. Figures 7 to 10 .

[0073] The second etching process includes a multi-cycle etching process, which includes: passivating the sidewall material layer on the top surface of the second core layer to form a passivation layer on the top surface of the sidewall material layer; after the passivation layer is formed, modifying the sidewall material layer at the bottom of the passivation layer and the top surface of the second core layer to form a modified layer on the top surface of the sidewall material layer; and removing the modified layer. For a description of the etching process, please refer to Figures 7 to 9 .

[0074] Please refer to Figure 7 , the spacer material layer 303 on the top surface of the second core layer 302 is passivated to form a passivation layer 305 on the top surface of the spacer material layer 303 , and the passivation layer 305 is located on the top surface of the second portion B.

[0075] In this embodiment, the material of the side wall material layer 303 includes silicon nitride, and the process of passivating the top surface of the side wall material layer 303 includes an oxidation treatment process; the parameters of the oxidation treatment process include: the gas includes a mixture of argon, oxygen and helium; the ion source power is 800 watts to 1000 watts; the bias power is 100 watts to 500 watts; and the pressure is 3 mTorr to 15 mTorr.

[0076] In other embodiments, the material of the side wall material layer includes silicon oxide, and the process of passivating the top surface of the side wall material layer includes a nitridation process; the parameters of the nitridation process include: the gas includes a mixture of argon, nitrogen and helium; the ion source power is 800 watts to 1500 watts; the bias power is 100 watts to 800 watts; and the pressure is 3 mTorr to 40 mTorr.

[0077] In this embodiment, the thickness of the passivation layer 305 on the top surface of the second region B2 is greater than the thickness of the passivation layer 305 on the top surface of the first region B1.

[0078] Because the passivation treatment is an anisotropic plasma treatment process with high directional selectivity, the reaction rate on the surface of the spacer material layer 303 parallel to the surface of the substrate 200 is much greater than the reaction rate on the surface of the spacer material layer 303 on the sidewall surface of the second core layer 302. The size of the second region B2 in the first direction X gradually increases along the second direction Y, that is, the surface of the second region B2 is uneven. The ions in the passivation treatment are diffusely reflected on the surface of the second region B2 and sputter each other, resulting in a deeper reaction between the passivation treatment and the second region B2, resulting in the thickness of the passivation layer 305 on the top surface of the second region B2 being greater than the thickness of the passivation layer 305 on the top surface of the first region B1.

[0079] Please refer to Figure 8 The sidewall material layer 303 at the bottom of the passivation layer 305 and the top surface of the second core layer 302 is modified to form a modified layer 306 on the top surface of the sidewall material layer 303 .

[0080] In this embodiment, the process for modifying the spacer material layer 303 at the bottom of the passivation layer 305 includes a hydrogenation treatment. The hydrogenation treatment can make the modified layer 306 formed after the modification of the spacer material layer 303 have a large etching selectivity with the spacer material layer 303, thereby facilitating the subsequent removal of the modified layer 306.

[0081] In this embodiment, the thickness of the modified layer 306 on the top surface of the second area B2 is less than the thickness of the modified layer 306 on the top surface of the first area B1. The process parameters of the hydrogenation treatment include: the gas is a mixture of hydrogen, ammonia and methane; the bias power is 100W to 300W.

[0082] The modification process is an anisotropic plasma treatment process, which has high directional selectivity, so that the reaction rate on the surface of the sidewall material layer 303 parallel to the surface of the substrate 200 is much greater than the reaction rate on the surface of the sidewall material layer 303 on the sidewall surface of the second core layer 302.

[0083] Because the thickness of the passivation layer 305 on the top surface of the second area B2 is greater than that of the passivation layer 305 on the top surface of the first area B1, when the plasma of the hydrogenation process passes through the passivation layer 305 to modify the spacer material layer 303, the passivation layer 305 on the top surface of the second area B2 is thicker, making it more difficult for the plasma of the hydrogenation process to penetrate the passivation layer 305 on the top surface of the second area B2. The passivation layer 305 on the top surface of the first area B1 is thinner, making it easier for the plasma of the hydrogenation process to penetrate the passivation layer 305 on the top surface of the first area B1 to modify the spacer material layer 303. As a result, the thickness of the modified layer 306 formed on the top surface of the second area B2 is less than that of the modified layer 306 on the top surface of the first area B1.

[0084] Please refer to Figure 9 , removing the modified layer 306.

[0085] In this embodiment, the process of removing the modified layer 306 includes a dry etching process; the process parameters of the dry etching process include: the gas includes a mixed gas of hydrogen, methane, ammonia, nitrogen trifluoride and carbon tetrafluoride; the pressure is 300 mTorr to 600 mTorr; and the ion source power is 500 W to 1500 W.

[0086] The dry etching process can remove a portion of the passivation layer 305 while removing the modified layer 306. The dry etching process has a relatively large etching selectivity for the modified layer 306 and the spacer material layer 303, thereby minimizing damage to the remaining spacer material layer 303 when removing the modified layer 306.

[0087] Because the thickness of the passivation layer 305 on the top surface of the second region B2 is greater than the thickness of the passivation layer 305 on the top surface of the first region B1, the thickness of the modified layer 306 formed on the top surface of the second region B2 is less than the thickness of the modified layer 306 on the top surface of the first region B1. Therefore, when removing the modified layer 306, since the thickness of the modified layer 306 on the top surface of the second region B2 is smaller and the thickness of the passivation layer 305 on the top surface of the second region B2 is larger, the thickness loss of the second region B2 is relatively small when the passivation layer 305 and the modified layer 306 on the surface of the first region B1 are removed by the dry etching process.

[0088] Therefore, when removing the modified layer 306, the first region B1 of the spacer material layer 303 loses a greater thickness, while the second region B2 of the spacer material layer 303 loses less thickness, resulting in a smaller height loss for the formed second spacer 307. Furthermore, the etching process etches the surface of the spacer material layer 303 parallel to the surface of the substrate 200 to a much greater extent than the etching of the surface of the spacer material layer 303 on the sidewall surface of the second core layer 302, resulting in a smaller dimensional loss for the formed second spacer 307 in the first direction X. In summary, the second dimension P2 of the formed second spacer 307 can be ensured to be greater than the first dimension P1 of the first spacer 304, thus meeting design requirements.

[0089] Please refer to Figure 10 A second sidewall 307 is formed on the sidewall of the second core layer 302. The second sidewall 307 has a second size P2 in the first direction X, and the second size P2 is greater than the first size P1. The top plane of the second sidewall 307 has a second height to the surface of the layer to be etched, and the second height is greater than the first height.

[0090] The second size P2 of the second side wall 307 is greater than the first size P1 of the first side wall 304, so that the patterns of the second side wall 307 and the first side wall 304 are subsequently transferred to the core material layer 211 to form a third core layer and a fourth core layer, and then a third side wall is formed in the third core layer. When the fourth side wall is formed in the fourth core layer, the spacing between the third side wall and the fourth side wall is different, so that the spacing between the first fin and the second fin formed subsequently is different.

[0091] After multiple cycles of the etching process, a second sidewall spacer 307 is formed on the sidewall of the second core layer 302. Because the etching process etches the sidewall material layer 303 in a direction parallel to the surface of the substrate 200 to a much greater extent than the etching of the sidewall material layer 303 on the sidewall surface of the second core layer 302, after multiple cycles, the second dimension P2 of the second sidewall spacer 307 in the first direction X has a smaller dimensional loss than the thickness of the sidewall material layer 303, thereby making the second dimension P2 larger than the first dimension P1. At the same time, the etching process causes a smaller thickness loss in the second area B2, thereby making the second height of the formed second sidewall spacer 307 larger than the first height, making the morphology and pattern transfer capability of the second sidewall spacer more stable.

[0092] In summary, the spacer material layer 303 on the sidewall surface and top surface of the first core layer 301 and the spacer material layer 303 on the sidewall surface and top surface of the second core layer 302 are formed simultaneously. Different etching processes are used to etch the spacer material layer 303 on the sidewall surface and top surface of the first core layer 301 and the spacer material layer 303 on the sidewall surface and top surface of the second core layer 302, respectively, to obtain first spacers 304 and second spacers 307 of different sizes. Therefore, there is no need to use another etching process to reduce the size of the first spacer 304. The first spacer 304 can be formed through only one etching process, so that the first spacer 304 is less damaged, has a better morphology, and has a higher dimensional accuracy. This is conducive to improving the morphology of the subsequently formed semiconductor structure and is conducive to improving the performance of the semiconductor structure.

[0093] In this embodiment, when the second etching process is used to etch the sidewall material layer 303 on the top surface and the sidewall surface of the second core layer 302, a covering layer (not marked) is also formed on the first region I, and the covering layer is used to protect the first sidewall 304 on the first region I.

[0094] After forming the first spacer 304 and the second spacer 307 , the cover layer is removed.

[0095] After forming the second sidewall spacer 307 , the second core layer 302 is removed, or the first core layer 301 and the second core layer 302 are removed simultaneously.

[0096] Next, the layer to be etched is etched using the first sidewall 304 and the second sidewall 307. Figures 11 to 13 .

[0097] Please refer to Figure 11 , using the first sidewall 304 and the second sidewall 307 as masks, the second hard mask layer 212 and the core material layer 211 are etched to form a third core layer 308 on the first hard mask layer 210 in the first region I, and a fourth core layer 309 is formed on the first hard mask layer 210 in the second region II.

[0098] The process of etching the second hard mask layer 212 and the core material layer 211 includes a dry etching process, which can form a third core layer 308 and a fourth core layer 309 with good and straight sidewall morphology, which is beneficial to improving the accuracy of graphic transmission.

[0099] Please refer to Figure 12 A third spacer 310 is formed on the sidewall of the third core layer 308 , and a fourth spacer 311 is formed on the sidewall of the fourth core layer 309 .

[0100] The material of the third spacer 310 and the material of the fourth spacer 311 are the same as the material of the first spacer 304 and the material of the second spacer 307 .

[0101] The method for forming the third sidewall 310 and the fourth sidewall 311 includes: forming a sidewall material layer (not shown) on the sidewall surface and top surface of the third core layer 308, on the sidewall surface and top surface of the fourth core layer 309, and on the surface of the first hard mask layer 210; etching back the sidewall material layer until the top surface of the third core layer 308, the top surface of the fourth core layer 309 and the surface of the first hard mask layer 210 are exposed, forming a third sidewall 310 on the sidewall of the third core layer 308, and forming a fourth sidewall 311 on the sidewall of the fourth core layer 309; and removing the third core layer 308 and the fourth core layer 309.

[0102] The process of removing the third core layer 308 and the fourth core layer 309 includes a wet etching process.

[0103] Please refer to Figure 13 , using the third sidewall 310 and the fourth sidewall 311 as masks to etch the first hard mask layer 210 and the substrate 200, so that the substrate 200 forms a base 300, a plurality of first fins 312 located on the first region I of the substrate 300, and a plurality of second fins 313 located on the second region II of the substrate 300, and the spacing between adjacent second fins 313 is greater than the spacing between adjacent first fins 312.

[0104] The spacing between adjacent second fins 313 is greater than the spacing between adjacent first fins 312 , so that when a device structure is subsequently formed on the second region II, the process window of the device structure is larger, and a thicker device structure can be formed to meet performance requirements.

[0105] In this embodiment, a size of the first fin 312 in the first direction X is the same as a size of the second fin 313 in the first direction X.

[0106] In another embodiment, the method further includes: performing a shrinking process on the first fin, wherein the shrinking process causes a size of the first fin in the first direction to be smaller than a size of the second fin in the first direction.

[0107] Figure 14 It is a cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0108] Please refer to Figure 14 , Figure 14 For Figure 9Based on the structural schematic diagram, a second side wall 407 is formed on the side wall of the second core layer 302, and the second side wall 407 has a second size P2 in the first direction X, and the second size P2 is greater than the first size P1. The top plane of the second side wall 407 has a second height to the surface of the layer to be etched, and the second height is greater than the first height.

[0109] The second sidewall 407 is formed through multiple cycles of etching process, and the etching process includes: passivating the sidewall material layer on the top surface of the second core layer to form a passivation layer on the top surface of the sidewall material layer; after the passivation layer is formed, modifying the sidewall material layer at the bottom of the passivation layer and the top surface of the second core layer to form a modified layer on the top surface of the sidewall material layer; and removing the modified layer.

[0110] Please refer to the etching process Figures 7 to 9 , I will not go into details here.

[0111] In this embodiment, the second sidewall spacer 407 includes an active area h1 arranged perpendicular to the surface of the substrate 200 and an inactive area h2 located on the active area h1. The top surface of the inactive area h2 is an inclined surface that is parallel to the surface of the layer to be etched.

[0112] In this embodiment, the sidewall material layer on the top surface of the second core layer is passivated, and the time for forming the passivation layer on the top surface of the sidewall material layer is a first time t1. The sidewall material layer at the bottom of the passivation layer and the top surface of the second core layer is modified, and the time for forming the modified layer on the top surface of the sidewall material layer is a second time t2. The time ratio of the first time t1 and the second time t2 is 2:1 to 5:1, so that the top surface of the formed invalid area h2 is an inclined surface with an angle parallel to the surface direction of the substrate 200.

[0113] The time ratio of t1 to t2 is 2:1 to 5:1, resulting in a top surface of the inactive region h2 that is angled relative to the surface of the layer to be etched. Consequently, after multiple cycles of etching, the height loss of the sidewall material layer 303 perpendicular to the surface of the substrate 200 is minimal. Simultaneously, the height of the inactive region h2 is also reduced, resulting in a higher height of the active region h1. The higher the height of the active region h1, the more accurate the subsequent pattern transfer will be, depending on the morphology and size of the active region h1. Specifically, the higher the height of the active region h1, the greater the dimensional accuracy of the pattern transfer.

[0114] Next, the second hard mask layer and the core material layer are etched using the first and second sidewall spacers as masks, forming a third core layer on the first hard mask layer in the first region and a fourth core layer on the first hard mask layer in the second region; a third sidewall spacer is formed on the sidewall of the third core layer and a fourth sidewall spacer is formed on the sidewall of the fourth core layer; the first hard mask layer and the substrate are etched using the third and fourth sidewall spacers as masks, so that the substrate forms a base, a plurality of first fins located on the first region of the substrate, and a plurality of second fins located on the second region II of the substrate. For the specific process of forming the fourth core layer, the third sidewall spacer, the fourth sidewall spacer, the first fin and the second fin, please refer to Figures 11 to 13 , I will not go into details here.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein the layer to be etched includes a first area and a second area; forming a plurality of discrete first core layers on the first region, wherein the plurality of first core layers are arranged along a first direction parallel to the substrate surface; forming a plurality of discrete second core layers on the second region, wherein the plurality of second core layers are arranged along a first direction, wherein a second dimension of adjacent second core layers is greater than a first dimension of adjacent first core layers, wherein the first dimension includes a dimension of the first core layer along the first direction and a spacing between adjacent first core layers, and the second dimension includes a dimension of the second core layer along the first direction and a spacing between adjacent second core layers; Forming a spacer material layer on the sidewall surface and top surface of the first core layer, and the sidewall surface and top surface of the second core layer, the spacer material layer on the sidewall surface and top surface of the second core layer includes a first portion and a second portion located on the first portion, the first portion is located on the sidewall of the second core layer, the bottom plane of the second portion is flush with the top plane of the second core layer, the second portion includes a first region and second regions located on both sides of the first region, the first region is located on the surface of the second core layer, the second region is connected to the first portion, and the size of the second region in the first direction gradually increases along the second direction, and the second direction is perpendicular to the surface of the layer to be etched; Etching the spacer material layer on the sidewall surface and the top surface of the first core layer using a first etching process to form a first spacer on the sidewall of the first core layer, wherein the first spacer has a first size in a first direction; Etching the sidewall material layer on the sidewall surface and the top surface of the second core layer using a second etching process to form a second sidewall spacer on the sidewall of the second core layer, wherein the second sidewall spacer has a second size in the first direction, and the second size is larger than the first size; The layer to be etched is etched using the first sidewall spacer and the second sidewall spacer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process includes an anisotropic dry etching process.

3. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process includes a multi-cycle etching process, and the etching process includes: passivating the sidewall material layer on the top surface of the second core layer to form a passivation layer on the top surface of the sidewall material layer, and the passivation layer is located on the top surface of the second part; after the passivation layer is formed, modifying the sidewall material layer at the bottom of the passivation layer and the top surface of the second core layer to form a modified layer on the top surface of the sidewall material layer; and removing the modified layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The thickness of the passivation layer on the top surface of the second region is greater than the thickness of the passivation layer on the top surface of the first region.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of modifying the sidewall material layer at the bottom of the passivation layer includes hydrogenation treatment; the process parameters of the hydrogenation treatment include: the gas is a mixed gas of hydrogen, ammonia and methane; the bias power is 100 watts to 300 watts.

6. The method for forming a semiconductor structure according to claim 5, wherein: The thickness of the modified layer on the top surface of the second region is smaller than the thickness of the modified layer on the top surface of the first region.

7. The method for forming a semiconductor structure according to claim 3, wherein: The process of removing the modified layer includes a dry etching process; the process parameters of the dry etching process include: the gas includes a mixed gas of hydrogen, methane, ammonia, nitrogen trifluoride and carbon tetrafluoride; the pressure is 300 mTorr~600 mTorr; and the ion source power is 500 W~1500 W.

8. The method for forming a semiconductor structure according to claim 3, wherein: The material of the spacer material layer includes silicon oxide.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process for passivating the top surface of the sidewall material layer includes a nitridation process; the parameters of the nitridation process include: the gas includes a mixture of argon, nitrogen and helium; the ion source power is 800 watts to 1500 watts; the bias power is 100 watts to 800 watts; and the pressure is 3 mTorr to 40 mTorr.

10. The method for forming a semiconductor structure according to claim 3, wherein: The material of the spacer material layer includes silicon nitride.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process for passivating the top surface of the sidewall material layer includes an oxidation process; the parameters of the oxidation process include: the gas includes a mixture of argon, oxygen and helium; the ion source power is 800 watts to 1000 watts; the bias power is 100 watts to 500 watts; and the pressure is 3 mTorr to 15 mTorr.

12. The method for forming a semiconductor structure according to claim 3, wherein: The time for passivation treatment of the side wall material layer on the top surface of the second core layer is the first time, and the time for modification treatment of the side wall material layer at the bottom of the passivation layer and the top surface of the second core layer is the second time. The ratio range of the first time and the second time is: 2:1 to 5:

1.

13. The method for forming a semiconductor structure according to claim 12, wherein: The second sidewall includes an effective area arranged along a direction perpendicular to the surface of the layer to be etched and an ineffective area located on the effective area. The top surface of the ineffective area is an inclined surface with an angle formed with the direction parallel to the surface of the layer to be etched.

14. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate; a first hard mask layer located on the substrate; a core material layer located on the first hard mask layer; and a second hard mask layer located on the core material layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: After forming the first side wall and the second side wall, the method further includes: etching the second hard mask layer and the core material layer using the first side wall and the second side wall as masks to form a third core layer on the first hard mask layer in the first area, and forming a fourth core layer on the first hard mask layer in the second area; forming a third side wall on the side wall of the third core layer, and forming a fourth side wall on the side wall of the fourth core layer; etching the first hard mask layer and the substrate using the third side wall and the fourth side wall as masks to form a base, a plurality of first fins located on the first area of ​​the base, and a plurality of second fins located on the second area of ​​the base, and the spacing between adjacent second fins is greater than the spacing between adjacent first fins.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: The first fin is reduced in size, so that a size of the first fin in the first direction is smaller than a size of the second fin in the first direction.

17. The method for forming a semiconductor structure according to claim 15, wherein: The material of the first core layer and the material of the second core layer are different from the material of the second hard mask layer; the material of the first side wall and the material of the second side wall are different from the material of the second hard mask layer; the material of the first side wall and the material of the second side wall are different from the material of the first core layer and the material of the second core layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The material of the first core layer and the material of the second core layer include silicon; the material of the second hard mask layer includes silicon oxide or silicon nitride.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the third core layer and the material of the fourth core layer are the same as the material of the first core layer and the material of the second core layer; the material of the first hard mask layer is the same as the material of the second hard mask layer; the material of the third side wall and the material of the fourth side wall are the same as the material of the first side wall and the material of the second side wall.

20. The method for forming a semiconductor structure according to claim 1, wherein: A first height is provided from the top plane of the first sidewall to the surface of the layer to be etched, and a second height is provided from the top plane of the second sidewall to the surface of the layer to be etched. The second height is greater than the first height.

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