Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device has a substrate; a lower conductive region disposed in the substrate; a first gate structure disposed on the substrate; a first drain region disposed in the substrate and adjacent to a sidewall of the first gate structure; and a first extended conductive region disposed in the substrate, below the first drain region, contacting a lower surface of the first drain region, and away from the lower conductive region. An upper surface of the first drain region and an upper surface of the substrate are substantially coplanar. The lower conductive region and the first extended conductive region comprise a same electrical type. The first drain region and the first extended conductive region comprise different electrical types.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 17 / 465,309, filed September 2, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. In particular, it relates to a semiconductor device having a leakage current guiding path and a method for fabricating the semiconductor device having the leakage current guiding path. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the increasing demands for computing power. However, this shrinking process introduces new and increasingly complex problems. Therefore, the challenges of improving quality, yield, performance, and reliability, while reducing complexity, continue.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate; a lower conductive region disposed in the substrate; a first gate structure disposed on the substrate; a first drain region disposed in the substrate and adjacent to a sidewall of the first gate structure; and a first extended conductive region disposed in the substrate, below the first drain region, contacting a lower surface of the first drain region, and away from the lower conductive region. An upper surface of the first drain region is coplanar with an upper surface of the substrate. The lower conductive region and the first extended conductive region have the same electrical type. The first drain region and the first extended conductive region have different electrical types.

[0006] In some embodiments, the semiconductor device further includes a first source region adjacent to another sidewall of the first gate structure. An upper surface of the first source region is substantially coplanar with the upper surface of the substrate.

[0007] In some embodiments, the semiconductor device further includes a baseline conductive region disposed in the substrate. An upper surface of the baseline conductive region is substantially coplanar with the upper surface of the substrate. The baseline conductive region and the lower conductive region have the same electrical type.

[0008] In some embodiments, the semiconductor device further includes an edge conductive region disposed in the substrate, above the lower conductive region, below the baseline conductive region, and away from the baseline conductive region. The lower conductive region and the edge conductive region have the same electrical type.

[0009] In some embodiments, the semiconductor device further includes a plurality of gate spacers disposed on the sidewalls of the first gate structure and on the substrate. The plurality of gate spacers include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

[0010] In some embodiments, the semiconductor device further includes a plurality of first lightly doped regions disposed in the substrate, respectively and correspondingly adjacent to the first drain region and the first source region, and respectively and correspondingly below the plurality of gate spacers.

[0011] In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate conductive layer, wherein the first gate dielectric layer is disposed on the substrate and the first gate conductive layer is disposed on the first gate dielectric layer.

[0012] In some embodiments, a lower surface of the first extended conductive region is in a vertical plane, which is lower than a vertical plane of an upper surface of the edge conductive region.

[0013] In some embodiments, the lower surface of the baseline conductive region is substantially coplanar with the lower surface of the first drain region.

[0014] In some embodiments, a lower surface of the baseline conductive region is in a vertical plane that is lower than a vertical plane of the lower surface of the first drain region.

[0015] In some embodiments, in a top view, a length of the first extended conductive region is greater than or equal to a length of the first drain region.

[0016] In some embodiments, the length of the edge conductive region is greater than or equal to the length of the baseline conductive region.

[0017] In some embodiments, the substrate and the lower conductive region comprise the same electrical type.

[0018] In some embodiments, the first drain region is configured to be electrically coupled to an external voltage source, which is between approximately +0.0 volts and approximately +6.0 volts.

[0019] In some embodiments, the baseline conductive region is configured to be electrically coupled to an external voltage source, which is between approximately +0.0 volts and approximately -2.0 volts.

[0020] In some embodiments, the semiconductor device further includes a second gate structure, a second drain region, and a second extended conductive region. The second gate structure is disposed on the substrate, between the first gate structure and the baseline conductive region. The second drain region is disposed in the substrate, near one sidewall of the second gate structure, and between the first source region and the baseline conductive region. The second extended conductive region is disposed in the substrate, below the second drain region, contacting a lower surface of the second drain region, and away from the lower conductive region. An upper surface of the second drain region is substantially coplanar with an upper surface of the substrate. The lower conductive region and the second extended conductive region have the same electrical type; wherein the second drain region and the second extended conductive region have different electrical types.

[0021] In some embodiments, the semiconductor device further includes an isolation layer disposed in the substrate and located between the second drain region and the first source region. The isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

[0022] In some embodiments, a lower surface of the insulating layer is located at a vertical plane that is higher than the vertical plane of the lower surface of the first extended conductive region.

[0023] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a lower conductive region in the substrate; forming a first extended conductive region in the substrate and above the lower conductive region; forming a first gate structure on the substrate; and forming a first drain region in the substrate, adjacent to one sidewall of the first gate structure, and on the first extended conductive region. An upper surface of the first drain region is substantially coplanar with an upper surface of the substrate. The lower conductive region and the first extended conductive region have the same electrical type. The first drain region and the first extended conductive region have different electrical types.

[0024] In some embodiments, the method of fabricating the semiconductor element further includes forming an edge conductive region in the substrate, on the lower conductive region, and away from the first extended conductive region.

[0025] Due to the design of the semiconductor device disclosed herein, the lower conductive region, the first extended conductive region, the second extended conductive region, and the edge conductive region can serve as multiple routing paths for multiple leakage currents generated by high voltage during programming operations. Therefore, the performance and reliability of the semiconductor device can be improved.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the embodiments and claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0029] Figure 2 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 3 This is a sectional view, illustrating along... Figure 2 The section along line A-A'.

[0031] Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 5 and Figure 6 This is a cross-sectional schematic diagram illustrating the preparation along an embodiment of the present disclosure. Figure 4 The section A-A' shows a partial process flow of a semiconductor device.

[0033] Figure 7 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0034] Figure 8 This is a sectional view, illustrating along... Figure 7 The section along line A-A'.

[0035] Figure 9 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0036] Figures 10 to 15 This is a cross-sectional schematic diagram illustrating the preparation along an embodiment of the present disclosure. Figure 9 The section A-A' shows a partial process flow of a semiconductor device.

[0037] Figure 16This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0038] Figure 17 This is a sectional view, illustrating along... Figure 16 The section along line A-A'.

[0039] The reference numerals in the attached figures are explained as follows:

[0040] 1A: Semiconductor components

[0041] 10: Preparation method

[0042] 101: Lower Conductive Region

[0043] 101TS: Top surface

[0044] 103: First extended conductive region

[0045] 103BS: Lower surface

[0046] 103TS: Top surface

[0047] 105: Second extended conductive region

[0048] 105BS: Lower surface

[0049] 105TS: Top surface

[0050] 107: Edge conductive region

[0051] 107BS: Lower surface

[0052] 107TS: Top surface

[0053] 109: Baseline Conductive Region

[0054] 109BS: Lower surface

[0055] 109TS: Top surface

[0056] 210: First gate structure

[0057] 211: First gate dielectric layer

[0058] 213: First gate conductive layer

[0059] 215: First Drain Region

[0060] 215TS: Top surface

[0061] 217: First Source Region

[0062] 217TS: Top surface

[0063] 219: First lightly doped region

[0064] 220: Second gate structure

[0065] 221: Second gate dielectric layer

[0066] 223: Second gate conductive layer

[0067] 225: Second drain region

[0068] 225TS: Top surface

[0069] 227: Second source pole region

[0070] 227TS: Top surface

[0071] 229: Second lightly doped region

[0072] 301: Base

[0073] 301TS: Top surface

[0074] 303: Isolation layer

[0075] 303BS: Lower surface

[0076] 305: Isolation layer

[0077] 305BS: Lower surface

[0078] 307: Gate spacer

[0079] 501: First isolation material

[0080] 503: First conductive material

[0081] 505: Lightly doped layer

[0082] 507: Spacer Material

[0083] 509: First masking layer

[0084] L1: Length

[0085] L2: Length

[0086] L3: Length

[0087] L4: Length

[0088] L5: Length

[0089] L6: Length

[0090] S11: Steps

[0091] S13: Steps

[0092] S15: Steps

[0093] S17: Steps

[0094] S19: Steps

[0095] S21: Steps

[0096] Z: Direction Detailed Implementation

[0097] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0098] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass not only the orientations shown in the figures but also different orientations of the elements during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0099] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0100] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0101] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term “substantially” may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0102] In this disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0103] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0104] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 This is a sectional view, illustrating along... Figure 2The section along line A-A'.

[0105] Please refer to Figures 1 to 3 In step S11, a substrate 301 may be provided, and a conductive region 101 may be formed in the substrate 301.

[0106] Please refer to Figure 2 and Figure 3 The substrate 301 may include a silicon-containing material. Examples of suitable silicon-containing materials for the substrate 301 may include, but are not limited to, silicon, germanium, carbon-doped silicon, germanium silicon carbide, carbon-doped silicon, silicon carbide, and multilayers thereof. While silicon is the primary semiconductor material used in wafer fabrication, in some embodiments other semiconductor materials may be applied as multiple additional layers, such as germanium, gallium arsenide, gallium nitride, germanium silicon, cadmium telluride, zinc selenide, germanium tin, etc., but are not limited to these.

[0107] In some embodiments, substrate 301 may be doped by a p-type impurity implantation process to have a first electrical type. This p-type impurity implantation process can add multiple impurities to an intrinsic semiconductor, creating multiple valence electron deficiencies. In a silicon-containing substrate, for example, a p-type dopant means that the impurity includes, but is not limited to, boron, aluminum, gallium, or indium.

[0108] It should be understood that the term "electrical type" refers to a doped region that is p-type or n-type.

[0109] Please refer to Figure 2 and Figure 3 The lower conductive region 101 may be formed in the substrate 301. In some embodiments, the lower conductive region 101 may be formed by an impurity implantation process, for example, a p-type impurity implantation process using a p-type dopant, such as boron, aluminum, gallium, or indium. In some embodiments, the lower conductive region 101 may have a first electrical type, which is the same as the electrical type of the substrate 301.

[0110] In some embodiments, the lower conductive region 101 and the substrate 301 may be doped with the same dopant. In some embodiments, the lower conductive region 101 and the substrate 301 may be doped with different dopants. In some embodiments, the doping concentration of the lower conductive region 101 may be less than the doping concentration of the substrate 301. In some embodiments, the doping concentration of the lower conductive region 101 may be greater than the doping concentration of the substrate 301.

[0111] Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 and Figure 6 This is a cross-sectional schematic diagram illustrating the preparation along an embodiment of the present disclosure. Figure 4 The partial process of semiconductor element 1A with cross-section A-A'.

[0112] Please refer to Figure 1 and Figures 4 to 6 In step S13, an edge conductive region 107 may be formed on the lower conductive region 101, and multiple isolation layers 303 and 305 may be formed in the substrate 301.

[0113] Please refer to Figure 4 and Figure 5 A mask layer (not shown for clarity) may be formed on substrate 301. The mask layer may have a pattern of edge conductive regions 107. In some embodiments, the mask layer may be a photoresist layer. In some embodiments, the mask layer may be a hard mask layer comprising silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable materials. An impurity implantation process using the mask layer as a pattern guide may be performed to form the edge conductive regions 107. For example, the impurity implantation process may be a p-type impurity implantation process using p-type dopants, such as boron, aluminum, gallium, or indium. After the edge conductive regions 107 are formed, the mask layer can be removed.

[0114] In a cross-sectional view, an edge conductive region 107 may be formed in the substrate 301 and on the upper surface 101TS of the lower conductive region 101. The lower surface 107BS of the edge conductive region 107 may directly contact the upper surface 101TS of the lower conductive region 101. In some embodiments, the sidewalls of the edge conductive region 107 may be tapered. In a top view, in some embodiments, the area of ​​the edge conductive region 107 may be smaller than the area of ​​the lower conductive region 101. For example, the area of ​​the edge conductive region 107 may be between approximately 5% and approximately 20% smaller than the area of ​​the lower conductive region 101. In some embodiments, the area of ​​the edge conductive region 107 may be approximately the same as the area of ​​the lower conductive region 101.

[0115] It should be understood that, in the description of this disclosure, a surface of an element (or feature) at the highest vertical plane along the Z-axis is referred to as an upper surface of the element (or feature). A surface of an element (or feature) at the lowest vertical plane along the Z-axis is referred to as a lower surface of the element (or feature).

[0116] In some embodiments, the edge conductive region 107 may have a first electrical type, which is the same as the electrical type of the lower conductive region 101. In some embodiments, the edge conductive region 107 and the lower conductive region 101 may be doped with the same dopant. In some embodiments, the edge conductive region 107 and the lower conductive region 101 may be doped with different dopants.

[0117] In some embodiments, the doping concentration of the edge conductive region 107 may be less than the doping concentration of the substrate 301. In some embodiments, the doping concentration of the edge conductive region 107 may be greater than the doping concentration of the substrate 301.

[0118] In some embodiments, the doping concentration of the edge conductive region 107 may be approximately the same as the doping concentration of the lower conductive region 101. In some embodiments, the doping concentration of the edge conductive region 107 may be greater than the doping concentration of the lower conductive region 101. In some embodiments, the doping concentration of the edge conductive region 107 may be less than the doping concentration of the lower conductive region 101.

[0119] Please refer to Figure 6 A series of deposition processes can be performed to deposit a pad oxide layer (not shown for clarity) and a pad nitride layer (not shown for clarity) on a substrate 301. A photolithography process can be performed to pattern a plurality of isolation layers 303, 305. After the photolithography process, an etching process, such as an anisotropic etching process, can be performed to form a plurality of trenches passing through the pad oxide layer, the pad nitride layer, and the substrate 301. An isolation material can be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, can then be performed to remove excess filler material until the substrate 301 is exposed to obtain the plurality of isolation layers 303, 305. For example, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the plurality of isolation layers 303, 305 can define a plurality of active regions in the substrate 301.

[0120] It should be understood that, in the description of this disclosure, silicon oxynitride represents a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide represents a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0121] Please refer to Figure 6 The upper surfaces of the plurality of isolation layers 303, 305 may be substantially coplanar with the upper surface 301TS of the substrate 301. In some embodiments, the plurality of isolation layers 303, 305 may be formed directly above the lower conductive region 101. In some embodiments, the plurality of isolation layers 303, 305 may be horizontally away from the edge conductive region 107.

[0122] In some embodiments, the lower surfaces 303BS, 305BS of the plurality of insulating layers 303, 305 and the upper surface 107TS of the edge conductive region 107 may be substantially on the same vertical plane. In some embodiments, the lower surfaces 303BS, 305BS of the plurality of insulating layers 303, 305 may be on a vertical plane that is lower than the vertical plane of the upper surface 107TS of the edge conductive region 107. In some embodiments, the lower surfaces 303BS, 305BS of the plurality of insulating layers 303, 305 may be on a vertical plane that is higher than the vertical plane of the upper surface 107TS of the edge conductive region 107.

[0123] Figure 7 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 8 This is a sectional view, illustrating along... Figure 7 The section along line A-A'.

[0124] Please refer to Figure 1 , Figure 7 and Figure 8 In step S15, a baseline conductive region 109 may be formed in the substrate 301.

[0125] Please refer to Figure 7 and Figure 8 A mask layer (not shown for clarity) may be formed on substrate 301. The mask layer may have a pattern of baseline conductive region 109. In some embodiments, the mask layer may be a photoresist layer. In some embodiments, the mask layer may be a hard mask layer comprising silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable materials. An impurity implantation process using the mask layer as a pattern guide may be performed to form the baseline conductive region 109. For example, the impurity implantation process may be a p-type impurity implantation process using p-type dopants, such as boron, aluminum, gallium, or indium. After the baseline conductive region 109 is formed, the mask layer can be removed.

[0126] In a cross-sectional view, a baseline conductive region 109 may be formed in a substrate 301. The upper surface 109TS of the baseline conductive region 109 may be substantially coplanar with the upper surface 301TS of the substrate 301. In some embodiments, the lower surface 109BS of the baseline conductive region 109 may be on a vertical plane that is higher than the vertical planes of the lower surfaces 303BS, 305BS of the plurality of insulating layers 303, 305. In some embodiments, the edge conductive region 107 may be topographically aligned with the baseline conductive region 109. In other words, in a top view, the edge conductive region 107 may overlap with the baseline conductive region 109.

[0127] It should be understood that in the description of this disclosure, an xyz coordinate system is assumed, where x and y represent the dimensions in the plane parallel to the main surface of the structure, and z represents a dimension perpendicular to the plane. When two features have approximately the same x and y coordinates, those features are aligned on the terrain structure.

[0128] In some embodiments, in a top view, the area of ​​the baseline conductive region 109 may be approximately the same as the area of ​​the edge conductive region 107. In some embodiments, the area of ​​the baseline conductive region 109 may be slightly smaller than the area of ​​the edge conductive region 107. For example, the area of ​​the baseline conductive region 109 may be approximately 5% to 20% smaller than the area of ​​the edge conductive region 107. In some embodiments, the length L1 of the edge conductive region 107 may be greater than the length L2 of the baseline conductive region 109. In some embodiments, the length L1 of the edge conductive region 107 and the length L2 of the baseline conductive region 109 may be approximately the same.

[0129] In some embodiments, the baseline conductive region 109 may have a first electrical type, which is the same as the electrical type of the lower conductive region 101, the electrical type of the edge conductive region 107, or the electrical type of the substrate 301. In some embodiments, the baseline conductive region 109 and the lower conductive region 101 may be doped with the same dopant. In some embodiments, the baseline conductive region 109 and the lower conductive region 101 may be doped with different dopants. In some embodiments, the baseline conductive region 109 and the edge conductive region 107 may be doped with the same dopant. In some embodiments, the baseline conductive region 109 and the edge conductive region 107 may be doped with different dopants.

[0130] In some embodiments, the doping concentration of the baseline conductive region 109 may be greater than the doping concentration of the substrate 301. In some embodiments, the doping concentration of the baseline conductive region 109 may be greater than the doping concentration of the lower conductive region 101. In some embodiments, the doping concentration of the baseline conductive region 109 may be greater than the doping concentration of the edge conductive region 107.

[0131] In some embodiments, the baseline conductive region 109 may be configured to be electrically coupled to an external voltage source. The external voltage source may be grounded or may be set to approximately 0.0 volts to approximately -2.0 volts.

[0132] Figure 9 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 10 to 15 This is a cross-sectional schematic diagram illustrating the preparation along an embodiment of the present disclosure. Figure 9 The partial process of semiconductor element 1A with cross-section A-A'.

[0133] Please refer to Figure 1 , Figure 9 and Figure 10In step S17, a first extended conductive region 103 and a second extended conductive region 105 may be formed in the substrate 301.

[0134] Please refer to Figure 9 and Figure 10 A mask layer (not shown for clarity) may be formed on substrate 301. The mask layer may have a pattern of a first extended conductive region 103 and a second extended conductive region 105. In some embodiments, the mask layer may be a photoresist layer. In some embodiments, the mask layer may be a hard mask layer comprising silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable materials. A defect implantation process using the mask layer as a pattern guide may be performed to form the first extended conductive region 103 and the second extended conductive region 105. For example, the defect implantation process may be a p-type defect implantation process using p-type dopants, such as boron, aluminum, gallium, or indium. After the first extended conductive region 103 and the second extended conductive region 105 are formed, the mask layer can be removed.

[0135] In some embodiments, the first extended conductive region 103 and the second extended conductive region 105 may have an electrical type that is the same as the electrical type of the lower conductive region 101, the electrical type of the edge conductive region 107, or the electrical type of the substrate 301.

[0136] In some embodiments, the first extended conductive region 103, the second extended conductive region 105, and the lower conductive region 101 may be doped with the same dopant. In some embodiments, the first extended conductive region 103, the second extended conductive region 105, and the lower conductive region 101 may be doped with different dopants. In some embodiments, the first extended conductive region 103, the second extended conductive region 105, and the edge conductive region 107 may be doped with the same dopant. In some embodiments, the first extended conductive region 103, the second extended conductive region 105, and the edge conductive region 107 may be doped with different dopants.

[0137] In some embodiments, the doping concentration of the first extended conductive region 103 and the second extended conductive region 105 may be greater than the doping concentration of the substrate 301. In some embodiments, the doping concentration of the first extended conductive region 103 and the second extended conductive region 105 may be approximately the same as the doping concentration of the lower conductive region 101. In some embodiments, the doping concentration of the first extended conductive region 103 and the second extended conductive region 105 may be approximately the same as the doping concentration of the edge conductive region 107.

[0138] In a cross-sectional view, a first extended conductive region 103 and a second extended conductive region 105 may be formed in the substrate 301. The first extended conductive region 103 may be formed adjacent to the insulating layer 305 and located between the plurality of insulating layers 303, 305. The second extended conductive region 105 may be formed adjacent to the insulating layer 303 and located between the insulating layer 303 and the baseline conductive region 109.

[0139] In some embodiments, the upper surfaces 103TS and 105TS of the first extended conductive region 103 and the second extended conductive region 105 may be located on a vertical plane, which is lower than the lower surface 109BS of the baseline conductive region 109. In some embodiments, the upper surfaces 103TS and 105TS of the first extended conductive region 103 and the second extended conductive region 105 may be located on a vertical plane, which is higher than the lower surface 109BS of the baseline conductive region 109. In some embodiments, the lower surface 109BS of the baseline conductive region 109 and the upper surfaces 103TS and 105TS of the first extended conductive region 103 and the second extended conductive region 105 may be located on substantially the same plane.

[0140] In some embodiments, the upper surfaces 103TS and 105TS of the first extended conductive region 103 and the second extended conductive region 105 may be located on a vertical plane, which is higher than the upper surface 107TS of the edge conductive region 107. In some embodiments, the lower surfaces 103BS and 105BS of the first extended conductive region 103 and the second extended conductive region 105 may be located on a vertical plane, which is lower than the upper surface 107TS of the edge conductive region 107.

[0141] In some embodiments, the lower surfaces 103BS and 105BS of the first extended conductive region 103 and the second extended conductive region 105 may be located on a vertical plane, which is higher than the upper surface 101TS of the lower conductive region 101. That is, there are gaps between the first extended conductive region 103 and the lower conductive region 101, and between the second extended conductive region 105 and the lower conductive region 101, respectively.

[0142] In some embodiments, in a top view, the area of ​​the first extended conductive region 103 is approximately the same as the area of ​​the second extended conductive region 105. In some embodiments, the area of ​​the first extended conductive region 103 may be smaller than the area of ​​the edge conductive region 107. The length L3 of the first extended conductive region 103 may be approximately the same as the length L4 of the second extended conductive region 105. In some embodiments, the length of the edge conductive region 107 may be approximately the same as the length L3 of the first extended conductive region 103. In some embodiments, the length L2 of the baseline conductive region 109 may be approximately the same as the length L3 of the first extended conductive region 103. In some embodiments, the length L3 of the first extended conductive region 103 may be smaller than the length L1 of the edge conductive region 107 or the length L2 of the baseline conductive region 109.

[0143] Please refer to Figure 1 and Figures 11 to 15 In step S19, a first gate structure 210 and a second gate structure 220 may be formed on the substrate 301, and a plurality of gate spacers 307 may be formed on each sidewall of the first gate structure 210 and the second gate structure 220.

[0144] Please refer to Figure 11 A first insulating material 501 may be formed on the substrate 301 in a blanket manner. For example, the fabrication techniques for the first insulating material 501 include chemical vapor deposition, atomic layer deposition, similar techniques, or other applicable deposition processes. For example, the first insulating material 501 may be silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant. For example, a dielectric material with a high dielectric constant may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0145] Please refer to Figure 11 A first conductive material 503 may be formed on the first insulating material 501. For example, the fabrication technology of the first conductive material 503 may include chemical vapor deposition, physical vapor deposition, sputtering, similar techniques, or other applicable deposition processes. For example, the first conductive material 503 may be polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0146] Please refer to Figure 11 A first masking layer 509 may be formed on the first conductive material 503. The first masking layer 509 may have a pattern of a first gate structure 210 and a second gate structure 220. In some embodiments, the first masking layer 509 may be a photoresist layer. In some embodiments, the first masking layer 509 may be a hard masking layer comprising silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable materials.

[0147] Please refer to Figure 12An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the first insulating material 501 and the first conductive material 503. After the etching process, the remaining first insulating material 501 can be transformed into a first gate dielectric layer 211 and a second gate dielectric layer 221. The remaining first conductive material 503 can be transformed into a first gate conductive layer 213 and a second gate conductive layer 223.

[0148] The first gate dielectric layer 211 may be formed on the substrate 301, between the plurality of isolation layers 303, 305, and may not be aligned with the topographic structure of the first extended conductive region 103. In other words, in a cross-sectional view, the first gate dielectric layer 211 may not be directly above the first extended conductive region 103. The first gate conductive layer 213 may be formed on the first gate dielectric layer 211. The first gate dielectric layer 211 and the first gate conductive layer 213 are configured together to form the first gate structure 210.

[0149] A second gate dielectric layer 221 may be formed on the substrate 301 and between the isolation layer 303 and the baseline conductive region 109. The second gate dielectric layer 221 may not be aligned with the topographic structure of the second extended conductive region 105. In other words, in a cross-sectional view, the second gate dielectric layer 221 may not be directly above the second extended conductive region 105. A second gate conductive layer 223 may be formed on the second gate dielectric layer 221. The second gate dielectric layer 221 and the second gate conductive layer 223 are configured together to form a second gate structure 220.

[0150] The first gate structure 210 and the second gate structure 220 can be integrated together to form multiple programmable units, such as electronic fuses or antifuses, in order to control the access of the programming current to the programmable units.

[0151] Please refer to Figure 13 A smear implantation process can be performed using the first gate structure 210 and the second gate structure 220 as multiple pattern guides to form multiple lightly doped layers 505. For example, the smear implantation process can be an n-type smear implantation process using an n-type dopant (or impurity). The n-type dopant can be added to an intrinsic semiconductor to contribute multiple free electrons to the intrinsic semiconductor. Examples of n-type dopants in a silicon-containing substrate include, but are not limited to, antimony, arsenic, and phosphorus. The multiple lightly doped layers 505 can have a second electrical type, which is different from the first electrical type. For example, the multiple lightly doped layers 505 can be n-type.

[0152] In some embodiments, during the impurity implantation process, a region on the baseline conductive region 109 may be covered by a masking layer (not shown for clarity).

[0153] Please refer to Figure 14 A spacer material 507 can be conformally formed to cover the substrate 301, the first gate structure 210, and the second gate structure 220. In some embodiments, for example, the spacer material 507 may be a material having etch selectivity relative to the substrate 301, or having etch selectivity relative to the substrate 301 and the first gate conductive layer 213. In some embodiments, for example, the spacer material 507 may be low-temperature silicon. In some embodiments, the spacer material 507 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, the like, or a combination thereof.

[0154] Please refer to Figure 15 A spacer etching process can be performed to remove the portions of the spacer material 507 formed on the upper surface 301TS of the substrate 301, the first gate structure 210, and the second gate structure 220. The spacer etching process can be an isotropic etching process. During the spacer etching process, the etch ratio of the spacer material 507 to the substrate 301 or the first gate conductive layer 213 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between 10:1 and approximately 2:1. After the spacer etching process, the remaining spacer material 507 can be considered as a plurality of spacers 307.

[0155] Figure 16 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 17 This is a sectional view, illustrating along... Figure 16 The section along line A-A'.

[0156] Please refer to Figure 1 , Figure 16 and Figure 17 In step S21, the first source / drain regions 215, 217 and the second source / drain regions 225, 227 may be formed in the substrate 301.

[0157] Please refer to Figure 16 and Figure 17A defect implantation process can be performed using a first gate structure 210, a second gate structure 220, and a plurality of gate spacers 307 as multiple pattern guides to form first source / drain regions 215, 217 and second source / drain regions 225, 227. For example, the defect implantation process can be an n-type defect implantation process using n-type dopants, such as antimony, arsenic, and phosphorus. After the formation of the first source / drain regions 215, 217 and the second source / drain regions 225, 227, a plurality of lightly doped layers 505 can be transformed into a plurality of first lightly doped regions 219 and a plurality of second lightly doped regions 229, which are directly below the plurality of gate spacers 307 and adjacent to the first source / drain regions 215, 217 and the second source / drain regions 225, 227, respectively.

[0158] The first source / drain regions 215, 217 and the second source / drain regions 225, 227 may have a second electrical type, which is the same as the plurality of first lightly doped regions 219 and the plurality of second lightly doped regions 229. The doping concentration of the first source / drain regions 215, 217 and the second source / drain regions 225, 227 may be greater than the doping concentration of the plurality of first lightly doped regions 219 and the plurality of second lightly doped regions 229. In some embodiments, the doping concentration of the first source / drain regions 215, 217 and the second source / drain regions 225, 227 may be between approximately 1E17 atoms / cm². 3 It is between approximately 1E18 atoms / cm3.

[0159] The first source / drain regions 215, 217 and the second source / drain regions 225, 227, the plurality of first lightly doped regions 219 and the plurality of lightly doped regions 229 may be doped with the same dopant. In some embodiments, the first source / drain regions 215, 217 and the second source / drain regions 225, 227, the plurality of first lightly doped regions 219 and the plurality of second lightly doped regions 229 may be doped with different dopant.

[0160] In some embodiments, a degradation process may be performed to activate the first source / drain regions 215, 217 and the second source / drain regions 225, 227. The annealing process temperature may be between approximately 800°C and approximately 1250°C. The annealing process may have a process duration between approximately 1 millisecond and approximately 500 milliseconds. For example, the annealing process may be a rapid thermal anneal, laser spike anneal, or flash lamp anneal.

[0161] First source / drain regions 215 and 217 may be formed in the substrate 301 and are distributed and correspond to the sidewalls adjacent to the first gate structure 210. In some embodiments, the first source / drain region 215 may be formed in the substrate 301, adjacent to the isolation layer 305, adjacent to the spacer 307 on the first gate structure 210, and on the first extended conductive region 103. The upper surface 215TS of the first drain region 215 may be substantially coplanar with the upper surface 301TS of the substrate 301. The lower surface of the first drain region 215 may directly contact the upper surface 103TS of the first extended conductive region 103. That is, the lower surface of the first drain region 215 and the upper surface 103TS of the first extended conductive region 103 may be substantially coplanar. The first source region 217 may be formed in the substrate 301, adjacent to the isolation layer 303 and adjacent to the spacer 307 on the first gate structure 210. The upper surface 217TS of the first source pole region 217 can be approximately coplanar with the upper surface 301TS of the substrate 301.

[0162] In some embodiments, the lower surfaces of the first source / drain regions 215, 217 may be substantially coplanar with the lower surface 109BS of the baseline conductive region 109. In some embodiments, the lower surfaces of the first source / drain regions 215, 217 may be located on a vertical plane that is higher than the vertical plane of the lower surface 109BS of the baseline conductive region 109. In some embodiments, the lower surfaces of the first source / drain regions 215, 217 may be located on a vertical plane that is lower than the vertical plane of the lower surface 109BS of the baseline conductive region 109. In some embodiments, the lower surfaces of the first source / drain regions 215, 217 may be located on a vertical plane that is higher than the vertical plane of the upper surface 107TS of the edge conductive region 107.

[0163] Second source / drain regions 225 and 227 may be formed in the substrate 301 and respectively adjacent to the sidewalls of the second gate structure 220. In some embodiments, the second drain region 225 may be formed in the substrate 301, adjacent to the isolation layer 303, adjacent to the spacer 307 on the second gate structure 220, and on the second extended conductive region 105. The upper surface 225TS of the second drain region 225 may be substantially coplanar with the upper surface 301TS of the substrate 301. The lower surface of the second drain region 225 may directly contact the upper surface 105TS of the second extended conductive region 105. That is, the lower surface of the second drain region 225 and the upper surface 105TS of the second extended conductive region 105 may be substantially coplanar. The second source region 227 may be formed in the substrate 301, adjacent to the spacer 307 on the second gate structure 220, and between the baseline conductive region 109 and the second drain region 225. The upper surface 227TS of the second source region 227 can be approximately coplanar with the upper surface 301TS of the substrate 301.

[0164] In some embodiments, the lower surfaces of the second source / drain regions 225, 227 and the lower surface 109BS of the baseline conductive region 109 may be substantially coplanar. In some embodiments, the lower surfaces of the second source / drain regions 225, 227 may be located on a vertical plane that is higher than the vertical plane of the lower surface 109BS of the baseline conductive region 109. In some embodiments, the lower surfaces of the second source / drain regions 225, 227 may be located on a vertical plane that is lower than the vertical plane of the lower surface 109BS of the baseline conductive region 109. In some embodiments, the lower surfaces of the second source / drain regions 225, 227 may be located on a vertical plane that is higher than the vertical plane of the upper surface 107TS of the edge conductive region 107.

[0165] In some embodiments, in a top view, the area of ​​the first drain region 215 may be smaller than the area of ​​the first extended conductive region 103. In some embodiments, the length L5 of the first drain region 215 may be smaller than the length L3 of the first extended conductive region 103. In some embodiments, the area of ​​the second drain region 225 may be smaller than the area of ​​the second extended conductive region 105. In some embodiments, the length L6 of the second drain region 225 may be smaller than the length L4 of the second extended conductive region 105.

[0166] The first drain region 215 and the second drain region 225 may be configured to be electrically coupled to a common external voltage source, which provides a voltage between approximately 0.0 volts and approximately +6.0 volts. This common external voltage source can provide voltage to program the programmable cell integrated with the first gate structure 210 and the second gate structure 220. The first source region 217 and the second source region 227 may be configured to be electrically coupled to a common ground.

[0167] Semiconductor element 1A may include multiple programmable cells (not shown for clarity) integrated with a first gate structure 210 and a second gate structure 220. Programming voltages may be provided via a common external voltage source and a common ground, respectively, through first source / drain regions 215, 217 and second source / drain regions 225, 227. The first gate structure 210 and the second gate structure 220 may each be electrically connected to different voltage sources to individually control access to multiple programming currents between the first source / drain regions 215, 217 or between the second source / drain regions 225, 227.

[0168] When only a programmable cell integrated with the first gate structure 210 is programmed, a high voltage (e.g., +6.0 volts) can be simultaneously applied to the first drain region 215. This high voltage can generate a leakage current from the first drain region 215. Due to the presence of the first extended conductive region 103, the leakage current from the first drain region 215 can be directed to the first extended conductive region 103, and can also be directed to the lower conductive region 101. That is, the first extended conductive region 103 can serve as a current path for guiding the leakage current to prevent multiple adjacent components (e.g., the second gate structure 220, which is not a programmed object) from being damaged by the leakage current. Accordingly, the second extended conductive region 105 can serve as a current path for guiding the leakage current to prevent multiple adjacent components from being damaged by the leakage current.

[0169] Furthermore, leakage current may originate from the voltage applied to the baseline conductive region 109. The edge conductive region 107 can serve as a current path to guide the leakage current from the baseline conductive region 109, thereby preventing multiple nearby components from being damaged by the leakage current.

[0170] Conversely, without the presence of the first extended conductive region 103, the second extended conductive region 105, and the lower conductive region 101, the leakage current generated by the high voltage may deviate from the first drain region 215 or the second drain region 225, damaging, for example, multiple components adjacent to the gate structure. This may reduce the critical voltage of the damaged gate structure. Therefore, it may severely affect the performance of the damaged gate structure during current-programmed operation or further operation.

[0171] One embodiment of this disclosure provides a semiconductor device including a substrate; a lower conductive region disposed in the substrate; a first gate structure disposed on the substrate; a first drain region disposed in the substrate and adjacent to a sidewall of the first gate structure; and a first extended conductive region disposed in the substrate, below the first drain region, contacting a lower surface of the first drain region, and away from the lower conductive region. An upper surface of the first drain region is coplanar with an upper surface of the substrate. The lower conductive region and the first extended conductive region have the same electrical type. The first drain region and the first extended conductive region have different electrical types.

[0172] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a lower conductive region in the substrate; forming a first extended conductive region in the substrate and above the lower conductive region; forming a first gate structure on the substrate; and forming a first drain region in the substrate, adjacent to one sidewall of the first gate structure, and on the first extended conductive region. An upper surface of the first drain region is substantially coplanar with an upper surface of the substrate. The lower conductive region and the first extended conductive region have the same electrical type. The first drain region and the first extended conductive region have different electrical types.

[0173] Due to the design of the semiconductor device disclosed herein, the lower conductive region 101, the first extended conductive region 103, the second extended conductive region 105, and the edge conductive region 107 can serve as multiple routing paths for multiple leakage currents generated by high voltage during programming operations. Therefore, the performance and reliability of the semiconductor device 1A can be improved.

[0174] It should be understood that the functions or steps mentioned in this disclosure may occur in a different order than in the diagrams. For example, two diagrams displayed consecutively may actually be executed approximately simultaneously, or sometimes in reverse order, depending on the functions or steps contained therein.

[0175] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0176] It should be understood that the term "about" modifies an ingredient, a quantity of a component, or a reactant of this disclosure, indicating a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of the components or the implementation of the methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0177] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0178] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One base; A conductive region is disposed in the substrate; A first gate structure is disposed on the substrate; A first drain region is disposed in the substrate and adjacent to a sidewall of the first gate structure; as well as A first extended conductive region is disposed in and surrounded by the substrate, below the first drain region, contacting a lower surface of the first drain region, and away from the lower conductive region; The upper surface of the first drain region is coplanar with the upper surface of the substrate; The substrate, the lower conductive region, and the first extended conductive region include the same electrical type; The first drain region and the first extended conductive region include different electrical types.

2. The semiconductor device of claim 1 further includes a first source region adjacent to another sidewall of the first gate structure; wherein an upper surface of the first source region is substantially coplanar with the upper surface of the substrate.

3. The semiconductor device of claim 2, further comprising a baseline conductive region disposed in the substrate; wherein an upper surface of the baseline conductive region is substantially coplanar with the upper surface of the substrate; wherein the baseline conductive region and the lower conductive region comprise the same electrical type.

4. The semiconductor device of claim 3 further includes an edge conductive region disposed in the substrate, on the lower conductive region, below the baseline conductive region, and away from the baseline conductive region; wherein the lower conductive region and the edge conductive region have the same electrical type.

5. The semiconductor device of claim 4 further includes a plurality of gate spacers disposed on the sidewall of the first gate structure and on the substrate; wherein the plurality of gate spacers include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

6. The semiconductor device of claim 5 further includes a plurality of first lightly doped regions disposed in the substrate, respectively and correspondingly adjacent to the first drain region and the first source region, and respectively and correspondingly below the plurality of gate spacers.

7. The semiconductor device of claim 6, wherein the first gate structure includes a first gate dielectric layer and a first gate conductive layer, the first gate dielectric layer being disposed on the substrate, and the first gate conductive layer being disposed on the first gate dielectric layer.

8. The semiconductor element of claim 7, wherein a lower surface of the first extended conductive region is in a vertical plane, which is lower than a vertical plane of an upper surface of the edge conductive region.

9. The semiconductor device of claim 8, wherein a lower surface of the baseline conductive region is substantially coplanar with the lower surface of the first drain region.

10. The semiconductor element of claim 8, wherein a lower surface of the baseline conductive region is in a vertical plane, which is lower than a vertical plane of the lower surface of the first drain region.

11. The semiconductor device of claim 8, wherein, in a top view, a length of the first extended conductive region is greater than or equal to a length of the first drain region.

12. The semiconductor device of claim 11, wherein a length of the edge conductive region is greater than or equal to a length of the baseline conductive region.

13. The semiconductor device of claim 12, wherein the first drain region is configured to be electrically coupled to an external voltage source between +0.0 volts and +6.0 volts.

14. The semiconductor device of claim 12, wherein the baseline conductive region is configured to be electrically coupled to an external voltage source between +0.0 volts and -2.0 volts.

15. The semiconductor device of claim 12, further comprising a second gate structure, a second drain region, and a second extended conductive region; wherein the second gate structure is disposed on the substrate and between the first gate structure and the baseline conductive region; wherein the second drain region is disposed in the substrate, near one sidewall of the second gate structure, and between the first source region and the baseline conductive region; wherein the second extended conductive region is disposed in the substrate and surrounded by the substrate, below the second drain region, in contact with a lower surface of the second drain region, and away from the lower conductive region; wherein an upper surface of the second drain region is substantially coplanar with an upper surface of the substrate; wherein the substrate, the lower conductive region, and the second extended conductive region have the same electrical type; wherein the second drain region and the second extended conductive region have different electrical types.

16. The semiconductor device of claim 15, further comprising an isolation layer disposed in the substrate and located between the second drain region and the first source region; wherein the isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

17. The semiconductor device of claim 16, wherein a lower surface of the isolation layer is located at a vertical plane, which is higher than the vertical plane of the lower surface of the first extended conductive region.

18. A method for fabricating a semiconductor element, comprising: Provide a base; A conductive region is formed in the substrate; A first extended conductive region is formed, which is surrounded by the substrate and above the lower conductive region; A first gate structure is formed on the substrate; and A first drain region is formed in the substrate, near one of the sidewalls of the first gate structure, and on the first extended conductive region; The upper surface of the first drain region is approximately coplanar with the upper surface of the substrate; The substrate, the lower conductive region, and the first extended conductive region include the same electrical type; The first drain region and the first extended conductive region include different electrical types.

19. The method for fabricating a semiconductor element as claimed in claim 18, further comprising forming an edge conductive region in the substrate, on the lower conductive region, and away from the first extended conductive region.

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