Method for eliminating damage to nanosheet channel of ring gate

Abstract

The application provides a method for eliminating damage of a ring gate nanometer sheet channel, which comprises the following steps: forming two or more channel layers and one or more sacrificial layers on a substrate in sequence to form a channel stack; forming a dummy gate across the channel stack on the substrate, and forming a first side wall on the surface of the dummy gate; etching the sacrificial layer to form a concave structure on the side surface of the channel stack, and forming a second side wall in the concave structure; preparing a source electrode and a drain electrode on the two sides of the channel stack respectively; when the channel layer in the channel stack is in contact with the dummy gate, etching the dummy gate and the adjacent channel layer until the sacrificial layer is exposed; etching the sacrificial layer again to form a ring gate preparation space; and preparing a ring-shaped metal gate in the ring gate preparation space to form a ring gate device. The method for eliminating damage of a ring gate nanometer sheet channel can effectively eliminate the damage of the nanometer sheet channel in the ring gate device and improve the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a method for eliminating channel damage in ring gate nanosheets. Background Technology

[0002] In the fabrication of gate-around-the-loop (GOLLO) structures, the first nanosheet often suffers lattice or physical-scale damage during processes such as pseudo-gate etching and implantation, leading to a decrease in the effective current of the GOLLO device. Furthermore, in GOLLO processes, when Lg > 150 nm, the first nanosheet is prone to warping at the gate edge. In addition, the channel layer and sacrificial layer have different oxidation properties, and some elements in the sacrificial layer readily diffuse at high temperatures. This results in severe diffusion at the fin edges during the subsequent high-temperature oxidation process of shallow trench isolation high-density plasma deposition. Due to the different oxidation processes, irregular channel / sacrificial layers form concave corners between the fins, complicating subsequent processes. Simultaneously, the oxidation process during shallow trench isolation high-density plasma deposition causes strain accumulation at the bottom of the channel layer fins, and these strain effects can induce lattice defects in the first nanosheet, ultimately degrading the electrical performance of the GOLLO device. Summary of the Invention

[0003] The method for eliminating nanosheet channel damage in ring gate devices provided by this invention can effectively eliminate nanosheet channel damage in ring gate devices and improve device performance.

[0004] This invention provides a method for eliminating channel damage in ring-gate nanosheets, the method comprising:

[0005] Two or more channel layers and one or more sacrificial layers are sequentially and alternately formed on the substrate to form a channel stack;

[0006] A dummy gate is formed on the substrate across the channel stack, and a first sidewall is formed on the surface of the dummy gate;

[0007] The sacrificial layer is etched to form a concave structure on the side surface of the channel stack, and a second sidewall is formed within the concave structure.

[0008] Source and drain electrodes are fabricated on both sides of the channel stack, respectively;

[0009] When the channel layer in the channel stack comes into contact with the dummy gate, the dummy gate and the adjacent channel layer are etched until the sacrificial layer is exposed; then the sacrificial layer is etched to form the ring gate fabrication space.

[0010] An annular metal gate is fabricated within the annular gate fabrication space to form an annular gate device.

[0011] Optionally, etching the dummy gate and adjacent channel layers until the sacrificial layer is exposed includes:

[0012] The dummy gate and the adjacent channel layer are etched sequentially;

[0013] The first dielectric film layer is formed using the same material as the second sidewall;

[0014] The region of the first dielectric film layer corresponding to the sacrificial layer is etched, and during the etching process, the first dielectric film layer corresponding to the area above the second sidewall is retained.

[0015] Optionally, etching the sacrificial layer to form the gate ring fabrication space includes:

[0016] The sacrificial layer is chemically etched or atomically etched to remove it, forming a ring gate fabrication space.

[0017] Optionally, forming a channel stack by sequentially and alternately forming two or more channel layers and one or more sacrificial layers on a substrate includes:

[0018] Silicon-germanium film and silicon film are alternately formed on an insulator-on-silicon substrate by epitaxy, wherein the silicon-germanium film is a sacrificial layer and the silicon film is a channel layer;

[0019] The channel stack is etched using a dry etching process to form a fin-shaped channel stack extending along a first direction.

[0020] Optionally, forming a dummy gate across the channel stack on the substrate includes:

[0021] A second dielectric film layer is formed on the substrate surface and the channel stack;

[0022] Based on the pattern shape of the channel stack, the second dielectric film layer is etched to form a dummy gate that has a step along the first direction with the channel stack and crosses the channel stack along the second direction.

[0023] Optionally, forming a first sidewall on the surface of the dummy fence includes:

[0024] A third dielectric film layer is formed on the surface of the dummy gate, the channel stack, and the substrate, wherein the third dielectric film layer has an etching selectivity ratio with the second dielectric film layer;

[0025] The third dielectric film layer is etched to form a first sidewall that is aligned with the side surface of the channel stack along a first direction, surrounds the side surface of the dummy gate, and covers the upper surface of the dummy gate.

[0026] Optionally, etching the sacrificial layer to form a recessed structure on the side surface of the channel stack includes:

[0027] The exposed sidewalls of the sacrificial layer are etched inward to form a concave structure; wherein the etching depth is equal to the thickness of the first sidewall.

[0028] Optionally, forming a second sidewall within the recessed structure includes:

[0029] A first dielectric film layer is formed, wherein the thickness of the first dielectric film layer is not less than the depth of the concave structure;

[0030] The first dielectric film layer is etched to form a second sidewall aligned with the channel layer in a first direction.

[0031] Optionally, before etching the dummy gate and the adjacent channel layer, the method further includes:

[0032] The device is planarized to remove the third dielectric film layer on top of the dummy gate, exposing the upper surface of the dummy gate.

[0033] Optionally, forming an annular metal gate within the annular gate fabrication space to create an annular gate device includes:

[0034] An annular metal gate is formed within the fabrication space using atomic layer deposition or vapor phase deposition.

[0035] In the technical solution provided by the invention, addressing the issue that the first nanosheet is prone to defects during the fabrication of a ring gate device, during the etching of the dummy gate, if the lower part of the dummy gate is adjacent to the first channel nanosheet, then the channel nanosheet is etched, preferably using a high-selectivity atomic layer etching method. Thus, after the defective nanosheet is etched away, only good nanosheets remain, thereby ensuring the overall performance of the device. Attached Figure Description

[0036] Figure 1 This is a flowchart illustrating a method for eliminating channel damage in a ring-shaped nanosheet according to an embodiment of the present invention;

[0037] Figure 2 A flowchart illustrating the method for filling depressions formed by etching the channel layer in another embodiment of the present invention to eliminate channel damage of the annular nanosheet;

[0038] Figure 3 This is a flowchart illustrating the method for etching channel stacks to eliminate channel damage in a ring-gate nanosheet according to another embodiment of the present invention;

[0039] Figure 4 This is a flowchart illustrating the method for forming a dummy gate in another embodiment of the present invention for eliminating channel damage in annular nanosheets;

[0040] Figure 5This is a flowchart illustrating the method for forming a first sidewall to eliminate channel damage in a ring-shaped nanosheet according to another embodiment of the present invention;

[0041] Figure 6 This is a flowchart illustrating the method for forming a second sidewall to eliminate damage to the annular nanosheet channel according to another embodiment of the present invention;

[0042] Figure 7 This is a structural diagram of the method for eliminating channel damage in ring-gate nanosheets according to another embodiment of the present invention after forming the sacrificial layer and the channel layer;

[0043] Figure 8 This is a structural diagram of a method for eliminating channel damage in annular nanosheets according to another embodiment of the present invention, showing the formation of a channel stack.

[0044] Figure 9 This is a structural diagram of a method for eliminating channel damage in annular nanosheets according to another embodiment of the present invention, showing the formation of a dummy gate and a first sidewall;

[0045] Figure 10 This is a structural diagram illustrating a method for eliminating channel damage in ring-shaped nanosheets according to another embodiment of the present invention, forming a concave structure.

[0046] Figure 11 This is a structural diagram of a method for forming a second sidewall to eliminate damage to the annular nanosheet channel according to another embodiment of the present invention;

[0047] Figure 12 A structural diagram of the source / drain formed by a method for eliminating channel damage in ring-gate nanosheets according to another embodiment of the present invention;

[0048] Figure 13 This is a structural diagram of the method for eliminating channel damage in ring-shaped nanosheets according to another embodiment of the present invention after etching the dummy gate;

[0049] Figure 14 This is a structural diagram of the channel layer after etching, representing another embodiment of the method for eliminating channel damage in ring-gate nanosheets according to the present invention.

[0050] Figure 15 This is a structural diagram illustrating the method for filling the depressions formed by etching the channel layer in another embodiment of the present invention to eliminate damage to the annular nanosheet channel;

[0051] Figure 16 This is a structural diagram of the method for eliminating channel damage in ring-gate nanosheets according to another embodiment of the present invention after etching the sacrificial layer;

[0052] Figure 17 This is a structural diagram of a metal gate formed by a method for eliminating channel damage in annular nanosheets according to another embodiment of the present invention;

[0053] Figure 18 This is a structural diagram of a method for forming a metal plug to eliminate channel damage in a ring-gate nanosheet, according to another embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] This invention provides a method for eliminating channel damage in ring-gate nanosheets, such as... Figure 1 As shown, the method includes:

[0056] Step 100: Two or more channel layers and one or more sacrificial layers are sequentially and alternately formed on the substrate to form a channel stack;

[0057] In some embodiments, a substrate refers to a structure that supports the formation of a semiconductor device. In this embodiment, the substrate may be, for example, a silicon-on-insulator substrate, or other substrates. A channel layer refers to a material film layer used as a channel after device formation, and a sacrificial layer refers to a material film layer that is removed during device fabrication. In this step, either the channel layer or the sacrificial layer can be formed first. The sacrificial layer can be made of silicon-germanium, germanium, silicon carbide, or gallium arsenide (GaAs), etc.; the channel layer can be made of a different material than the sacrificial layer, such as silicon-germanium, germanium, silicon carbide, or GaAs, etc. That is, the material types selected for the channel layer and the sacrificial layer must be different, so that the channel layer can be retained when the sacrificial layer is removed.

[0058] Step 200: Form a dummy gate across the channel stack on the substrate, and form a first sidewall on the surface of the dummy gate;

[0059] In some embodiments, a dummy gate refers to a material film layer formed in the region corresponding to the gate. This material film layer serves as a placeholder, reserving space for the gate. In subsequent fabrication processes, the dummy gate is removed before the gate is fabricated, and the resulting space is used to form the gate. A dummy gate spanning the channel stack refers to a dummy gate whose extension direction is perpendicular to the extension direction of the channel stack. Furthermore, the dummy gate covers two opposite sides of the channel stack along its own extension direction, and also covers the top surface of the channel stack. Forming a first sidewall on the surface of the dummy gate means forming a first sidewall around the dummy gate, covering both the side and top surfaces of the dummy gate.

[0060] Step 300: Etch the sacrificial layer to form a concave structure on the side surface of the trench stack, and form a second sidewall within the concave structure;

[0061] In some embodiments, during the etching of the sacrificial layer, the exposed sidewalls of the sacrificial layer are etched inwards. After the sacrificial layer is etched, a portion of it is removed, creating an inward recess on the side surface of the channel stack corresponding to the sacrificial layer. Forming the second sidewall involves filling the recessed structure to restore the side surface of the channel stack to a smooth state. The filling material can be one or a mixture of two or more of SiC, Si3N4, and SiON. Since the sacrificial layer is positioned for subsequent fabrication of the gate ring, the second sidewall serves two purposes: firstly, to limit the size of the gate ring, and secondly, to insulate the gate ring from the source and drain.

[0062] Step 400: Source and drain electrodes are fabricated on both sides of the channel stack, respectively;

[0063] In some embodiments, since the sidewalls of the channel layer in the channel stack are exposed, the channel layer will contact the source and drain during the fabrication of the source and drain.

[0064] Step 500: When the channel layer in the channel stack comes into contact with the dummy gate, the dummy gate and the adjacent channel layer are etched until the sacrificial layer is exposed; then the sacrificial layer is etched to form the ring gate fabrication space.

[0065] In some embodiments, when the channel layer in a channel stack contacts the dummy gate, the top channel layer nanosheets may suffer damage due to etching, implantation, and high-temperature oxidation. To ensure device performance, after etching the dummy gate, the exposed channel layer is etched away until the top sacrificial layer is exposed. After etching away the dummy gate and the top channel layer, the sacrificial layer is exposed. Etching the sacrificial layer removes it, creating a cavity in the space it occupies. In the fabrication of channel stacks, another scenario occurs where the sacrificial layer contacts the dummy gate. In this case, because the sacrificial layer protects the top first channel layer, additional etching of the top channel layer is not required; only the dummy gate needs to be etched before directly etching the sacrificial layer.

[0066] Step 600: A ring-shaped metal gate is fabricated within the ring gate fabrication space to form a ring gate device.

[0067] In some embodiments, after the sacrificial layer and dummy gate are removed, the space occupied by the sacrificial layer and dummy gate forms a cavity, providing space for the fabrication of the ring gate. Since the dummy gate and sacrificial layer form a structure enclosing the channel layer, the cavity is also formed around the channel layer. After forming the dielectric metal gate in the cavity, the dielectric metal will form a ring gate around the channel layer. In some embodiments, the dielectric layer can be a high-k dielectric.

[0068] In the technical solution provided in the embodiments of the invention, based on the problem that the first nanosheet is prone to defects during the fabrication of the ring gate device, if the lower part of the dummy gate is adjacent to the first channel nanosheet, then the channel nanosheet is etched during the etching of the dummy gate. Thus, after the defective nanosheet is etched away, the remaining nanosheets are all good nanosheets, thereby ensuring the performance of the entire device.

[0069] As an optional implementation method, such as Figure 2 As shown, etching the dummy gate and the adjacent channel layer until the sacrificial layer is exposed includes:

[0070] Step 510: Etch the dummy gate and the adjacent channel layer sequentially;

[0071] In some embodiments, since the dummy gate is typically made of a different material than the channel layer, it is usually etched in two steps using different methods. First, the dummy gate is etched to expose the channel layer, and then the exposed channel layer is etched.

[0072] Step 520: Form a first dielectric film layer using the same material as the second sidewall;

[0073] In some embodiments, during the etching process, the etched channel layer forms a cavity below the first sidewall. Typically, a small amount of residue remains, which will be used to insulate the ring gate from the source and drain during subsequent ring gate fabrication. However, since the residual size of the channel layer is difficult to control, to avoid short circuits due to insufficient residue, this embodiment uses the same material as the second sidewall to form the first dielectric film layer. The first dielectric film layer will at least fill the space above the second sidewall after the channel layer etching is completed.

[0074] Step 530: Etch the region of the first dielectric film layer corresponding to the sacrificial layer. During the etching process, retain the first dielectric film layer corresponding to the second sidewall.

[0075] In some embodiments, since the formation of the first dielectric film layer will cover the entire surface of the device, it is necessary to etch the first dielectric film layer. In the structure after etching, the first dielectric film layer corresponding to the second sidewall is retained.

[0076] As an optional implementation, etching the sacrificial layer to form the gate ring fabrication space includes:

[0077] The sacrificial layer is chemically etched or atomically etched to remove it, forming a ring gate fabrication space.

[0078] In some embodiments, since the sacrificial layer is located in the space surrounding the channel layer, its structure has a partially obscured portion. In order to successfully etch the sacrificial layer, chemical etching or atomic layer etching is required.

[0079] As an optional implementation method, such as Figure 3 As shown, forming a channel stack by sequentially and alternately forming two or more channel layers and one or more sacrificial layers on a substrate includes:

[0080] Step 110: Silicon-germanium film and silicon film are alternately formed on silicon-on-insulator substrate by epitaxy, wherein the silicon-germanium film is a sacrificial layer and the silicon film is a channel layer;

[0081] In some embodiments, the silicon film layer has the characteristics of a channel layer and can be used as a channel layer, while the silicon-germanium film layer can exhibit a selectivity ratio with the silicon film layer during the etching process, which is more conducive to etching the silicon-germanium film layer while retaining the silicon film layer.

[0082] Step 120: The channel stack is etched using a dry etching process to form a fin-shaped channel stack extending along a first direction.

[0083] In some embodiments, since a channel stack is formed across the entire surface of the substrate during epitaxial growth, the channel stack needs to be etched to form a fin shape in order to fabricate the device. The fin-shaped channel stack is advantageous for forming a dummy gate across the channel stack.

[0084] As an optional implementation method, such as Figure 4 As shown, forming a dummy gate across the channel stack on the substrate includes:

[0085] Step 210: A second dielectric film layer is formed on the substrate surface and the channel stack;

[0086] In some embodiments, when forming the second dielectric film layer, a cover is formed on the substrate and the channel stack, and a conformal structure is formed from the surface of the substrate to the surface of the channel stack, thereby covering the sidewalls of the channel stack.

[0087] Step 220: Based on the pattern shape of the channel stack, the second dielectric film layer is etched to form a dummy gate that has a step along the first direction with the channel stack and crosses the channel stack along the second direction.

[0088] In some embodiments, when etching the second dielectric film layer, the size of the retained portion in the first direction is smaller than the size of the channel stack in the first direction, thereby forming a step from the channel stack to the second dielectric film layer; the size of the retained portion in the second direction is larger than the size of the channel stack in the second direction, thereby forming a dummy gate across the channel stack. The axis of the dummy gate in the first direction is aligned with the axis of the channel stack in the first direction, and the axis of the dummy gate in the second direction is aligned with the axis of the channel stack in the second direction.

[0089] As an optional implementation method, such as Figure 5 As shown, forming a first sidewall on the surface of the dummy fence includes:

[0090] Step 230: A third dielectric film layer is formed on the surface of the dummy gate, the channel stack and the substrate, wherein the third dielectric film layer has an etching selectivity ratio with the second dielectric film layer;

[0091] In some embodiments, during the formation of the third dielectric film, it covers the dummy gate, the channel stack, and the substrate surface to form a conformal structure, thereby also covering the sides of the dummy gate and the channel stack. The third dielectric film has an etching selectivity ratio with the second dielectric film, which allows the third dielectric film to be etched without damaging it during the etching of the dummy gate, i.e., without damaging the first sidewall, which is beneficial for subsequent ring gate formation.

[0092] Step 240: Etch the third dielectric film layer to form a first sidewall that is aligned with the channel stack side surface along the first direction, surrounds the dummy gate side surface, and covers the dummy gate upper surface.

[0093] In some embodiments, when etching the third dielectric film layer, the retained portion is aligned with the side surface of the channel stack in the first direction, thereby exposing the side surfaces of the channel stack, which allows for subsequent etching of the sacrificial layer to form a recessed structure. Furthermore, since the size of the dummy gate in the first direction is smaller than that of the channel stack in the first direction, after etching, the two sides of the dummy gate perpendicular to the first direction have sufficient thickness to form sidewalls.

[0094] As an optional implementation, etching the sacrificial layer to form a recessed structure on the side surface of the channel stack includes:

[0095] The exposed sidewalls of the sacrificial layer are etched inward to form a concave structure; wherein the etching depth is equal to the thickness of the first sidewall.

[0096] In some embodiments, since the ring gate is formed by occupying the space of the dummy gate and the sacrificial layer during the formation process, in this embodiment, setting the etching depth to be equal to the thickness of the first sidewall helps to form a ring gate with consistent dimensions in the first direction.

[0097] As an optional implementation method, such as Figure 6 As shown, forming a second sidewall within the concave structure includes:

[0098] Step 310: Form a first dielectric film layer, wherein the thickness of the first dielectric film layer is not less than the depth of the concave structure;

[0099] In some embodiments, during the formation of the first dielectric film layer, the entire surface of the device is covered as the upper surfaces of each portion are covered and the conformal structure is formed. To fill the recessed structure, the thickness of the first dielectric film layer is set to be not less than the depth of the recessed structure.

[0100] Step 320: Etch the first dielectric film layer to form a second sidewall aligned with the channel layer in a first direction.

[0101] In some embodiments, during the etching process of the first dielectric film layer, all the parts outside the concave structure are etched away, and only the part inside the concave structure is retained as the second sidewall.

[0102] As an optional implementation, before etching the dummy gate and the adjacent channel layer, the method further includes:

[0103] The device is planarized to remove the third dielectric film layer on top of the dummy gate, exposing the upper surface of the dummy gate.

[0104] In some embodiments, since the top of the dummy gate is covered when the third dielectric film is formed, at least a portion of the top of the dummy gate is also retained during the etching process. Before etching the dummy gate, the top-covering third dielectric film needs to be planarized first to expose the dummy gate before etching can be performed.

[0105] As an optional implementation, a ring-shaped dielectric metal gate is fabricated within the ring gate fabrication space to form a ring gate device, comprising:

[0106] Using atomic layer deposition or vapor phase deposition, a ring-shaped high-k dielectric metal gate is formed within the fabrication space of the ring gate.

[0107] In some embodiments, since the ring gate fabrication space is an irregularly shaped space formed around the channel layer, atomic layer deposition or vapor deposition is required to fabricate a high-k dielectric metal gate in this space.

[0108] like Figure 7-18 As shown, an exemplary implementation method is provided to illustrate the technical solution provided by the present invention:

[0109] First, SiGe and Si layers are epitaxially grown sequentially on an SOI (Silicon On Insulator) wafer. The Si layer determines the number of nanowires that can be fabricated. Since the top channel layer needs to be removed after device fabrication, and the device must retain at least one channel layer, at least two Si layers are used in this embodiment. In this embodiment, the SiGe layer serves as a sacrificial layer, and the Si layer serves as the channel layer. After the stack is formed, its structure is as follows... Figure 7 As shown. To fabricate the stacked layers to meet device requirements, photolithography and etching are necessary. Dry etching can be used as an example. After etching, a channel stack is formed, with the structure shown below. Figure 8 As shown. A dummy gate is formed by depositing a film, such as a polysilicon film, and etching the polysilicon film. A second film, such as a silicon dioxide film, is deposited and etched to form a first sidewall. The structure after forming the first sidewall is as shown. Figure 9 As shown. After the first sidewall is formed, the sacrificial layer is etched to create an inwardly recessed structure, such as... Figure 10 As shown. After forming the recessed structure, a second sidewall is formed by depositing a film, such as a silicon nitride film, and etching the silicon nitride film. The structure after forming the second sidewall is as follows. Figure 11 As shown. During the formation of the sidewalls, a high-selectivity anisotropic etching method can be used. During the etching process, the film layer on the horizontal plane is etched away rapidly, while the film layer on the vertical plane is etched away at a slower rate. After forming the second sidewall, the source and drain regions are formed through epitaxial growth. After the source and drain are formed, the structure is as follows. Figure 12 As shown. After forming the source and drain, the device is planarized, for example by chemical mechanical polishing, to remove the silicon dioxide film layer on top of the dummy gate. Then, the dummy gate is removed by etching, for example by wet etching. The structure after removing the dummy gate is shown. Figure 13 As shown. After removing the dummy gate, if the channel layer is in contact with the dummy gate, it needs to be removed by etching. For example, atomic layer etching (ALT) can be used to remove the top channel layer. The structure after removing the top channel layer is shown below. Figure 14As shown. After removing the dummy gate and the top channel layer, to avoid short circuits caused by source / drain exposure after channel layer removal during subsequent gate ring formation, a new dielectric film is formed on the device. For example, a silicon nitride or silicon oxynitride film can be formed using atomic layer deposition. After forming the new dielectric film, anisotropic etching is performed to remove the film layer outside the corresponding region of the second sidewall. At this point, the device structure is as follows. Figure 15 As shown. After completing the above steps, the sacrificial layer is exposed, and it can then be etched. Etching methods include dry etching, wet atomic layer etching, or hydrogen chloride gas reaction etching. After etching, the space occupied by the dummy gate and the sacrificial layer forms a cavity, the structure of which is shown below. Figure 16 As shown. A high-k dielectric metal gate is then grown within the space containing the dummy gate and the sacrificial layer, forming a ring-shaped metal gate, the structure of which is as follows. Figure 17 As shown. After completing the above steps, a dielectric film layer, such as a silicon dioxide dielectric film layer, is formed. Holes are then created in the dielectric film layer, and metal plugs are formed to form the final device. The device structure is as follows. Figure 18 As shown.

[0110] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for eliminating channel damage in ring-gate nanosheets, characterized in that, The method includes: Two or more channel layers and one or more sacrificial layers are sequentially and alternately formed on the substrate to form a channel stack; A dummy gate is formed on the substrate across the channel stack, and a first sidewall is formed on the surface of the dummy gate; The sacrificial layer is etched to form a concave structure on the side surface of the channel stack, and a second sidewall is formed within the concave structure. Source and drain electrodes are fabricated on both sides of the channel stack, respectively; When the channel layer in the channel stack comes into contact with the dummy gate, the entire dummy gate and the top channel layer adjacent to the dummy gate are etched until the sacrificial layer is exposed; then the sacrificial layer is etched to form the ring gate fabrication space. An annular metal gate is fabricated within the annular gate fabrication space to form an annular gate device.

2. The method according to claim 1, characterized in that, Etching the entire layer of the dummy gate and the channel layer adjacent to the top of the dummy gate until the sacrificial layer is exposed includes: The entire layer of the dummy gate and the top channel layer adjacent to the dummy gate is etched sequentially; The first dielectric film layer is formed using the same material as the second sidewall; The region of the first dielectric film layer corresponding to the sacrificial layer is etched, and during the etching process, the first dielectric film layer corresponding to the area above the second sidewall is retained.

3. The method according to claim 1, characterized in that, Etching the sacrificial layer to form the gate ring fabrication space includes: The sacrificial layer is chemically etched or atomically etched to remove it, forming a ring gate fabrication space.

4. The method according to claim 1, characterized in that, Forming a channel stack by sequentially and alternately forming two or more channel layers and one or more sacrificial layers on a substrate includes: Silicon-germanium film and silicon film are alternately formed on an insulator-on-silicon substrate by epitaxy, wherein the silicon-germanium film is a sacrificial layer and the silicon film is a channel layer; The channel stack is etched using a dry etching process to form a fin-shaped channel stack extending along a first direction.

5. The method according to claim 1, characterized in that, Forming a dummy gate across the channel stack on the substrate includes: A second dielectric film layer is formed on the substrate surface and the channel stack; Based on the pattern shape of the channel stack, the second dielectric film layer is etched to form a dummy gate that has a step along the first direction with the channel stack and crosses the channel stack along the second direction.

6. The method according to claim 5, characterized in that, Forming a first sidewall on the surface of the dummy fence includes: A third dielectric film layer is formed on the surface of the dummy gate, the channel stack, and the substrate, wherein the third dielectric film layer has an etching selectivity ratio with the second dielectric film layer; The third dielectric film layer is etched to form a first sidewall that is aligned with the side surface of the channel stack along a first direction, surrounds the side surface of the dummy gate, and covers the upper surface of the dummy gate.

7. The method according to claim 1, characterized in that, Etching the sacrificial layer to form a recessed structure on the side surface of the channel stack includes: The exposed sidewalls of the sacrificial layer are etched inward to form a concave structure; wherein the etching depth is equal to the thickness of the first sidewall.

8. The method according to claim 1, characterized in that, Forming a second sidewall within the recessed structure includes: A first dielectric film layer is formed, wherein the thickness of the first dielectric film layer is not less than the depth of the concave structure; The first dielectric film layer is etched to form a second sidewall aligned with the channel layer in a first direction.

9. The method according to claim 6, characterized in that, Before etching the entire layer of the dummy gate and the top channel layer adjacent to the dummy gate, the process further includes: The device is planarized to remove the third dielectric film layer on top of the dummy gate, exposing the upper surface of the dummy gate.

10. The method according to claim 1, characterized in that, Fabricating an annular metal gate within the annular gate fabrication space to form an annular gate device includes: An annular metal gate is formed within the fabrication space using atomic layer deposition or vapor phase deposition.

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