Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises a first sampling circuit, which is provided with an output end and is used for generating a first differential signal according to a signal to be compared and a first reference signal under the control of a first control signal and a clock signal; a second sampling circuit, which is provided with an output end and is connected with the output end of the first sampling circuit, and is used for generating a second differential signal according to the signal to be compared and a second reference signal under the control of a second control signal and the clock signal, wherein the first reference signal is greater than the second reference signal; and an output circuit, which is provided with an input end and is connected with the output end of the first sampling circuit, and is used for amplifying and latching a voltage signal of the output end of the first sampling circuit or a voltage signal of the output end of the second sampling circuit, and outputting a comparison result. According to the application, the sampling circuit is selected according to the influence trend of the signal to be compared, and the inter-symbol interference of the comparator can be eliminated.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuits, in particular to a comparator and a decision feedback equalization circuit. BACKGROUND

[0002] Nowadays, people's demand for mobile devices such as mobile phones, tablets and various wearable accessories has greatly increased, which greatly enriches our daily life and work.

[0003] However, due to the limited battery life, higher requirements are put forward for the power consumption of each component in the mobile device. Dynamic random access memory (DRAM) is an essential component in mobile devices, so DRAM also needs to achieve lower operating voltage and lower energy consumption. Among them, the comparator is an important device for realizing the data read and write of DRAM, and the existing comparator cannot meet the current use demand. SUMMARY

[0004] The present application provides a comparator and a decision feedback equalization circuit, aiming to eliminate the inter-symbol interference of the comparator.

[0005] An embodiment of the present application provides a comparator, comprising:

[0006] A first sampling circuit having an output end, configured to generate a first differential signal according to a to-be-compared signal and a first reference signal under the control of a first control signal and a clock signal;

[0007] A second sampling circuit having an output end, the output end of the second sampling circuit being connected with the output end of the first sampling circuit, and the second sampling circuit being configured to generate a second differential signal according to the to-be-compared signal and a second reference signal under the control of a second control signal and the clock signal; wherein the first reference signal is greater than the second reference signal;

[0008] An output circuit having an input end, the input end of the output circuit being connected with the output end of the first sampling circuit, and the output circuit being configured to amplify and latch a voltage signal of the output end of the first sampling circuit or a voltage signal of the output end of the second sampling circuit, and output a comparison result.

[0009] Another embodiment of the present application provides a decision feedback equalization circuit, comprising the comparator in the above embodiment, which is sequentially marked as a first comparator, a second comparator, a third comparator and a fourth comparator;

[0010] The first input end of the first comparator is configured to receive the to-be-compared signal, the second input end is configured to receive the first reference signal, the third input end is configured to receive the second reference signal, the fourth input end and the fifth input end are connected with the output end of the fourth comparator and are configured to receive the first control signal and the second control signal, and the sixth input end is configured to receive the first clock signal.

[0011] a second comparator, a first input terminal of which is used for receiving the signal to be compared, a second input terminal of which is used for receiving the first reference signal, a third input terminal of which is used for receiving the second reference signal, a fourth input terminal and a fifth input terminal of which are connected with the output terminal of the first comparator and are used for receiving the first control signal and the second control signal, and a sixth input terminal of which is used for receiving the second clock signal;

[0012] a third comparator, a first input terminal of which is used for receiving the signal to be compared, a second input terminal of which is used for receiving the first reference signal, a third input terminal of which is used for receiving the second reference signal, a fourth input terminal and a fifth input terminal of which are connected with the output terminal of the second comparator and are used for receiving the first control signal and the second control signal, and a sixth input terminal of which is used for receiving the third clock signal;

[0013] a fourth comparator, a first input terminal of which is used for receiving the signal to be compared, a second input terminal of which is used for receiving the first reference signal, a third input terminal of which is used for receiving the second reference signal, a fourth input terminal and a fifth input terminal of which are connected with the output terminal of the third comparator and are used for receiving the first control signal and the second control signal, and a sixth input terminal of which is used for receiving the fourth clock signal.

[0014] The comparator and the decision feedback equalization circuit provided by the embodiments of the present application comprise a first sampling circuit, a second sampling circuit and an output circuit, wherein the first sampling circuit outputs a first differential signal according to the first reference signal and the signal to be compared under the control of the first control signal and the clock signal, and the second sampling circuit outputs a second differential signal according to the second reference signal and the signal to be compared under the control of the second control signal and the clock signal. The first reference signal is greater than the second reference signal, when the signal to be compared is greatly affected by the inter-symbol interference, the greater first reference signal is used to sample the signal to be compared, when the signal to be compared is slightly affected by the inter-symbol interference, the smaller second reference signal is used to sample the signal to be compared, so as to ensure that the polarity of the differential signal generated by the signal to be compared before being affected is the same as the polarity of the differential signal generated by the signal to be compared after being affected, so that the output circuit can output a more accurate comparison result, thereby eliminating the inter-symbol interference. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 a structural block diagram of the comparator provided by an embodiment of the present application;

[0016] Figure 2 a specific circuit diagram of the comparator provided by an embodiment of the present application;

[0017] Figure 3 a specific circuit diagram of the comparator provided by an embodiment of the present application;

[0018] Figure 4A structure block diagram of a decision feedback equalization circuit is provided for an embodiment of the present application.

[0019] Figure 5 A timing diagram of a decision feedback equalization circuit is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0020] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to all alternative embodiments, as would be understood by persons skilled in the art. To the extent that they do not particularize to the application, the following description of exemplary embodiments refers only to specific arrangements that do not limit the application in any way. Rather, they merely exemplify all aspects of the application, as outlined by the appended claims.

[0021] As shown in FIG. 1, an embodiment of the present application provides a comparator, which includes a first sampling circuit 101, a second sampling circuit 102, and an output circuit 103. Figure 1

[0022] The first sampling circuit 101, the second sampling circuit 102, and the output circuit 103 are each provided with an input end and an output end, and the first sampling circuit 101 and the second sampling circuit 102 are further provided with a control end. The control end of the first sampling circuit 101 is configured to receive a first control signal and a clock signal, and the input end of the first sampling circuit 101 is configured to receive a signal to be compared and a first reference signal, so that the first sampling circuit 101 generates a first differential signal according to the signal to be compared and the first reference signal under the control of the first control signal and the clock signal.

[0023] The control end of the second sampling circuit 102 is configured to receive a second control signal and a clock signal, and the input end of the second sampling circuit 102 is configured to receive the signal to be compared and a second reference signal, so that the second sampling circuit 102 generates a second differential signal according to the signal to be compared and the second reference signal under the control of the second control signal and the clock signal.

[0024] The output end of the second sampling circuit 102 is connected to the output end of the first sampling circuit 101, and the input end of the output circuit 103 is also connected to the output end of the first sampling circuit 101, so that the output circuit 103 amplifies and latches the voltage signal of the output end of the first sampling circuit 101 or the voltage signal of the output end of the second sampling circuit 102, and outputs a comparison result.

[0025] ​The first reference signal is greater than the second reference signal. When the to-be-compared signal is affected and its amplitude becomes larger, the first control signal controls the first sampling circuit 101 to sample the to-be-compared signal and the first reference signal to generate a first differential signal, and the second control signal controls the second sampling circuit 102 to stop sampling. When the to-be-compared signal is affected and its amplitude becomes smaller, the first control signal controls the first sampling circuit 101 to stop sampling, and the second control signal controls the second sampling circuit 102 to sample the to-be-compared signal and the second reference signal to generate a second differential signal. In this way, when the to-be-compared signal is affected and its amplitude becomes smaller, the second reference signal with a smaller amplitude is used, and when the to-be-compared signal is affected and its amplitude becomes larger, the first reference signal with a larger amplitude is used, so as to ensure that the polarity of the differential signal generated by the to-be-compared signal before being affected is the same as the polarity of the differential signal generated by the to-be-compared signal after being affected, so that the output circuit 103 can output a more accurate comparison result.

[0026] In an embodiment, the first sampling circuit 101 includes a first sampling unit 1011 and a first control unit 1012, and the first sampling unit 1011 and the first control unit 1012 are each provided with an input end and an output end, and the first sampling unit 1011 is further provided with a control end. The input end of the first control unit 1012 is used to receive a first control signal and a clock signal to control the working mode of the first sampling unit 1011 according to the first control signal and the clock signal. The working mode of the first sampling unit 1011 includes a sampling mode. The output end of the first control unit 1012 is connected with the control end of the first sampling unit 1011, and the first sampling unit 1011 is used to generate a first differential signal according to the to-be-compared signal and the first reference signal when working in the sampling mode.

[0027] In an embodiment, the second sampling circuit 102 includes a second sampling unit 1021 and a second control unit 1022, and the second sampling unit 1021 and the second control unit 1022 are each provided with an input end and an output end, and the second sampling unit 1021 is further provided with a control end. The input end of the second control unit 1022 is used to receive a second control signal and a clock signal to control the working mode of the second sampling unit 1021 according to the second control signal and the clock signal. The working mode of the second sampling unit 1021 includes a sampling mode. The output end of the second control unit 1022 is connected with the control end of the second sampling unit 1021, and the second sampling unit 1021 is used to generate a second differential signal according to the to-be-compared signal and the second reference signal when working in the sampling mode.

[0028] In the technical solution, the comparator comprises a first sampling circuit 101, a second sampling circuit 102 and an output circuit 103. The first sampling circuit 101 is configured to generate a first differential signal according to a signal to be compared and a first reference signal. The second sampling circuit 102 is configured to generate a second differential signal according to the signal to be compared and a second reference signal. The first sampling circuit 101 or the second sampling circuit 102 is controlled according to an affected condition of the signal to be compared to perform sampling, so as to ensure that the polarities of the differential signals generated before and after the signal to be compared is affected are the same, and the output circuit 103 can output a more accurate comparison result, thereby eliminating the inter-symbol interference.

[0029] As shown in Figure 2 An embodiment of the present application provides a comparator, which comprises six input terminals and two output terminals. The comparator comprises a first sampling circuit 101, a second sampling circuit 102 and an output circuit 103. The first sampling circuit 101 further comprises a first sampling unit 1011 and a first control unit 1012, and the second sampling circuit 102 further comprises a second sampling unit 1021 and a second control unit 1022.

[0030] The input terminal of the first sampling unit 1011 comprises a first input terminal and a second input terminal. The output terminal of the first sampling unit 1011 comprises a first output terminal and a second output terminal. The input terminal of the second sampling unit 1021 comprises a first input terminal and a second input terminal, and the output terminal of the second sampling unit 1021 comprises a first output terminal and a second output terminal. The input terminal of the first control unit 1012 comprises a first input terminal and a second input terminal, and the input terminal of the second control unit 1022 comprises a first input terminal and a second input terminal.

[0031] The first input terminal of the first sampling unit 1011 is used as a first input terminal of the comparator and is configured to receive a first reference signal VREFP. The second input terminal of the second sampling unit 1021 and the second input terminal of the first sampling unit 1011 are both used as a second input terminal of the comparator and are configured to receive a signal to be compared DQ. The first input terminal of the second sampling unit 1021 is used as a third input terminal of the comparator and is configured to receive a second reference signal VREFN. The first input terminal of the first control unit 1012 is used as a fourth input terminal of the comparator and is configured to receive a first control signal D270B. The first input terminal of the second control unit 1022 is used as a fifth input terminal of the comparator and is configured to receive a second control signal D270B. The second input terminal of the first control unit 1012 and the second input terminal of the second control unit 1022 are both used as a sixth input terminal of the comparator and are configured to receive a clock signal CLK.

[0032] The output end of the output circuit 103 further comprises a first output end and a second output end, the first output end of the output circuit 103 serving as a first output end of the comparator, and the second output end of the output circuit 103 serving as a second output end of the comparator.

[0033] The first sampling unit 1011 comprises a first input transistor N1, a second input transistor N2 and a third input transistor N3. The control end of the first input transistor N1 serves as a first input end of the first sampling unit 1011, and is configured to receive the first reference signal VREFP. The first end of the first input transistor N1 serves as a first output end of the first sampling unit 1011. The control end of the second input transistor N2 serves as a second input end of the first sampling unit 1011, and is configured to receive the to-be-compared signal DQ. The first end of the second input transistor N2 serves as a second output end of the first sampling unit 1011. The control end of the third input transistor N3 serves as a control end of the first sampling unit 1011, and is configured to be connected with the output end of the first control unit 1012. The first end of the third input transistor N3 is connected with the second end of the first input transistor N1 and the second end of the second input transistor N2, and the second end of the third input transistor N3 is connected with a ground end.

[0034] In the above technical solution, the first sampling unit 1011 comprises three transistors, two of which are configured to receive the first reference signal VREFP and the to-be-compared signal DQ, and the control end of the other transistor serves as a sampling unit. The first control unit 1012 controls the working mode of the first sampling unit 1011 through the transistor control end of the first sampling unit 1011, and can control the working mode of the first sampling unit 1011 according to the influence on the to-be-compared signal DQ, so as to ensure that the polarities of the differential signals generated by the to-be-compared signal DQ before and after being influenced are the same, and the output circuit 103 can output a more accurate comparison result.

[0035] The first control unit 1012 comprises a first AND gate circuit, which is provided with a first input end, a second input end and an output end. The first input end of the first AND gate circuit serves as a first input end of the first control unit 1012, and is configured to receive the first control signal D270. The second input end of the first AND gate circuit serves as a second input end of the first control unit 1012, and is configured to receive the clock signal CLK. The output end of the first AND gate circuit serves as an output end of the first control unit 1012, and is configured to be connected with the control end of the first sampling unit 1011.

[0036] In the technical solution, the first control unit 1012 comprises a first AND gate circuit, and the first control unit 1012 outputs a calculation result DSEL by performing AND calculation on the first control signal D270 and the clock signal CLK through the first AND gate circuit, and controls the working mode of the first sampling unit 1011 by using the calculation result DSEL, so as to control the working mode of the first sampling unit 1011 according to the first control signal D270 and the clock signal CLK.

[0037] The second sampling unit 1021 comprises a fourth input transistor N4, a fifth input transistor N5 and a sixth input transistor N6. The control end of the fourth input transistor N4 is used as the first input end of the second sampling unit 1021, and is used for receiving the second reference signal VREFN. The first end of the fourth input transistor N4 is used as the first output end of the second sampling unit 1021. The control end of the fifth input transistor N5 is used as the second input end of the second sampling unit 1021, and is used for receiving the to-be-compared signal DQ. The first end of the fifth input transistor N5 is used as the second output end of the second sampling unit 1021. The control end of the sixth input transistor N6 is used as the control end of the second sampling unit 1021, and is connected with the output end of the second control unit 1022. The first end of the sixth input transistor N6 is connected with the second end of the fourth input transistor N4 and the second end of the fifth input transistor N5, and the second end of the sixth input transistor N6 is connected with the ground end.

[0038] The second control unit 1022 comprises a second AND gate circuit, and the second AND gate circuit is provided with a first input end, a second input end and an output end. The first input end of the second AND gate circuit is used as the first input end of the second control unit 1022, and is used for receiving the second control signal D270B. The second input end of the second AND gate circuit is used as the second input end of the second control unit 1022, and is used for receiving the clock signal CLK. The output end of the second AND gate circuit is used as the output end of the second control unit 1022, and is connected with the control end of the second sampling unit 1021.

[0039] In the technical solution, the second control unit 1022 comprises a second AND gate circuit, and the second control unit 1022 outputs a calculation result DSELB by performing AND calculation on the second control signal D270B and the clock signal CLK through the second AND gate circuit, and controls the working mode of the second sampling unit 1011 by using the calculation result DSELB, so as to control the working mode of the second sampling unit 1011 according to the second control signal D270B and the clock signal CLK.

[0040] The first control signal D270 and the second control signal D270B are a pair of inverse signals. That is, when the first control signal D270 is high, the second control signal D270B is low. When the first control signal D270 is low, the second control signal D270B is high. Thus, the first sampling unit 101 or the second sampling unit 102 is controlled to work in the sampling mode.

[0041] In an embodiment, the first input transistor N1 to the sixth input transistor N6 are of the same type. When the first input transistor N1 to the sixth input transistor N6 are N-type transistors, the drain of the N-type transistor is the first end, and the gate of the N-type transistor is the control end.

[0042] When the to-be-compared signal DQ is affected and its amplitude becomes large, the first control signal is high, and the second control signal is low. When the clock signal CLK arrives, the first AND gate circuit outputs high, and the second AND gate circuit outputs low. The third input transistor N3 is turned on, and the sixth input transistor N6 is turned off. The first sampling unit 1011 works in the sampling mode, and the second sampling unit 1021 works in the idle mode, that is, the second sampling unit 1021 stops sampling. When the first sampling unit 1011 works in the sampling mode, the first reference signal VREFP pulls the drain voltage of the first input transistor N1, and the to-be-compared signal DQ pulls the drain voltage of the second input transistor N2. The amplitudes of the first reference signal VREFP and the to-be-compared signal DQ are different, and the pulling ability of the transistors is also different. A first differential signal is generated between the drain of the first input transistor N1 and the drain of the second input transistor N2. For example, when the to-be-compared signal DQ is affected and its amplitude becomes large, because the first reference signal VREFP with a large amplitude is selected, it can be ensured that the drain voltage of the first input transistor N1 is greater than the drain voltage of the second input transistor N2 when the first reference signal VREFP is greater than the to-be-compared signal DQ. Thus, it can be ensured that the polarity of the differential signal generated by the to-be-compared signal DQ before being affected is the same as the polarity of the differential signal generated by the to-be-compared signal DQ after being affected.

[0043] When the to-be-compared signal DQ is affected and its amplitude becomes small, the first control signal is low and the second control signal is high. When the clock signal CLK arrives, the first AND gate circuit outputs low and the second AND gate circuit outputs high, the third input transistor N3 is cut off and the sixth input transistor N6 is turned on. The first sampling unit 1011 works in the idle mode and the second sampling unit 1021 works in the sampling mode. When the second sampling unit 1021 works in the sampling mode, the second reference signal VREFN pulls the drain voltage of the fourth input transistor N4 and the to-be-compared signal DQ pulls the drain voltage of the fifth input transistor N5. When the amplitudes of the second reference signal VREFN and the to-be-compared signal DQ are different, the pulling ability of the transistors is also different, and the second differential signal is generated at the drain of the fourth input transistor N4 and the drain of the fifth input transistor N5. For example, when the to-be-compared signal DQ is affected and its amplitude becomes small, the second reference signal VREFN with small amplitude is selected, and the second reference signal VREFN is still ensured to be smaller than the to-be-compared signal DQ, the drain voltage of the fourth input transistor N4 is smaller than the drain voltage of the fifth input transistor N5, so as to ensure that the polarity of the differential signal generated by the to-be-compared signal DQ before being affected is the same as the polarity of the differential signal generated by the to-be-compared signal DQ after being affected.

[0044] In an embodiment, the first control signal and the second control signal are determined according to the trend of the to-be-compared signal DQ being affected. When the trend of the to-be-compared signal DQ being affected is to become large, the first control signal is high and the second control signal is low. When the trend of the to-be-compared signal DQ being affected is to become small, the first control signal is low and the second control signal is high.

[0045] The output circuit 103 includes a first output transistor N7, a second output transistor N8, a third output transistor N9, a fourth output transistor N10, a fifth output transistor P3, a sixth output transistor P4 and a seventh output transistor P5. The input end of the output circuit 103 includes a first input end and a second input end, and the output end of the output circuit 103 includes a first output end and a second output end.

[0046] The control end of the first output transistor N7 is the first input end of the output circuit 103, which is used to be connected with the first output end of the first sampling unit 1011. The first end of the first output transistor N7 is the first output end of the output circuit 103, and the second end of the first output transistor N7 is connected with the ground end. The control end of the second output transistor N8 is the second input end of the output circuit 103, which is used to be connected with the second output end of the first sampling unit 1011. The first end of the second output transistor N8 is the second output end of the output circuit 103, and the second end of the second output transistor N8 is connected with the ground end.

[0047] The first end of the third output transistor N9 is connected with the first end of the first output transistor N7, the second end of the third output transistor N9 is connected with the second end of the first output transistor N7, and the control end of the third output transistor N9 is connected with the first end of the fourth output transistor N10. The first end of the fourth output transistor N10 is connected with the first end of the second output transistor N8, the second end of the fourth output transistor N10 is connected with the second end of the second output transistor N8, and the control end of the fourth output transistor N10 is connected with the first end of the third output transistor N9. The second end of the fifth output transistor P3 is connected with the first end of the third output transistor N9, and the control end of the fifth output transistor P3 is connected with the first end of the fourth output transistor N10. The second end of the sixth output transistor P4 is connected with the first end of the fourth output transistor N10, and the control end of the sixth output transistor P4 is connected with the first end of the third output transistor N9.

[0048] The control end of the seventh output transistor P5 is used for receiving a clock signal CLK, the first end of the seventh output transistor P5 is connected with a power supply end, and the second end of the seventh output transistor P5 is connected with the first end of the fifth output transistor P3 and the first end of the sixth output transistor P4.

[0049] In an embodiment, the first output transistor N7 to the fourth output transistor N10 are all N-type transistors, and the fifth output transistor P3 to the seventh output transistor P5 are all P-type transistors. Wherein, the drain of the N-type transistor is the first end, the gate of the N-type transistor is the control end, the source of the P-type transistor is the first end, and the gate of the P-type transistor is the control end.

[0050] When a pulse arrives in the clock signal CLK, the seventh output transistor P5 is input with the inverted clock signal CLKB, so that the seventh output transistor P5 is turned on. The output circuit 103 performs amplification processing and latching processing on the voltage signal of the output end of the first sampling circuit 101 or the voltage signal of the output end of the second sampling circuit 102, and outputs the comparison result. Taking the first sampling circuit 101 for sampling and the second sampling circuit 102 for stopping sampling as an example, the control end of the first output transistor N7 receives one of the first differential signals, and the control end of the second output transistor N8 receives the other of the first differential signals. After the two differential signals are amplified by the first output transistor N7 and the second output transistor N8, they are input to the control ends of the third output transistor N9 to the sixth output transistor P4, and after the re-amplification and latching processing of the third output transistor N9 to the sixth output transistor P4, the comparison result is output.

[0051] After the drain voltages of the first output transistor N7 and the second output transistor N8 are amplified and latched by the third output transistor N9 to the sixth output transistor P4, there are two cases for the drain voltages of the first output transistor N7 and the second output transistor N8. In the first case, the drain voltage P0B of the first output transistor N7 is high, and the drain voltage P0 of the second output transistor N8 is low, which represents the output result with the digital "0". In the second case, the drain voltage P0B of the first output transistor N7 is low, and the drain voltage P0 of the second output transistor N8 is high, which represents the output result with the digital "1".

[0052] In the technical solution, the first differential signal or the second differential signal is amplified by two transistors and then amplified and latched by four transistors, so that the accuracy of the output result can be further improved.

[0053] In an embodiment, the comparator further includes a reset circuit 104 connected to the first sampling circuit 101 and the second sampling circuit 102, configured to reset the voltage of the first sampling circuit 101 before the first sampling circuit 101 enters the sampling working mode, and reset the voltage of the second sampling circuit 102 before the second sampling circuit 102 enters the sampling working mode.

[0054] In the technical solution, the output end voltages of the first sampling circuit 101 and the second sampling circuit 102 are reset by the reset circuit 104, so that the output end voltages of the two sampling units can be quickly reset, thereby improving the reaction rate of the comparator.

[0055] In an embodiment, the reset circuit 104 includes a first clocked transistor P1 and a second clocked transistor P2. The control end of the first clocked transistor P1 receives a clock signal CLK, the first end of the first clocked transistor P1 is connected to a power supply end, and the second end of the first clocked transistor P1 is connected to the first end of the first input transistor N1 and the first end of the fourth input transistor N4. The control end of the second clocked transistor P2 receives the clock signal CLK, the first end of the second clocked transistor P2 is connected to the power supply end, and the second end of the second clocked transistor P2 is connected to the first end of the second input transistor N2 and the first end of the fifth input transistor N5.

[0056] In an embodiment, the first clocked transistor P1 and the second clocked transistor P2 are P-type transistors, the source of the P-type transistor is the first end, and the gate of the P-type transistor is the control end.

[0057] Before the pulse comes in the clock signal CLK, the control ends of the first clock transistor P1 and the second clock transistor P2 receive signals at low level, the first clock transistor P1 and the second clock transistor P2 are turned on, the first clock transistor P1 pulls the voltage of the drain of the first input transistor N1 and the drain of the fourth input transistor N4 to the voltage of the power supply end, and the second clock transistor P2 pulls the voltage of the drain of the second input transistor N2 and the drain of the fifth input transistor N5 to the voltage of the power supply end.

[0058] In the technical solution, two AND gate circuits generate signals for controlling the working modes of the two sampling units according to the control signal and the clock signal CLK, and when the trend of the to-be-compared signal DQ is to decrease, the first sampling unit 1011 is controlled to work in the sampling mode, and when the trend of the to-be-compared signal DQ is to increase, the second sampling unit 1021 is controlled to work in the sampling mode, so that the polarity of the differential signal generated by the to-be-compared signal DQ before being affected is the same as the polarity of the differential signal generated by the to-be-compared signal DQ after being affected, thereby ensuring that the output circuit 103 can accurately output the comparison result according to the differential signal and eliminating the code interference.

[0059] As shown in Figure 3 An embodiment of the present application provides a comparator, which comprises a first sampling circuit 101, a second sampling circuit 102 and an output circuit 103. The first sampling circuit 101 is further provided with a first sampling unit 1011 and a first control unit 1012, and the second sampling circuit 102 is further provided with a second sampling unit 1021 and a second control unit 1022.

[0060] The first sampling unit 1011 comprises a first input transistor P1, a second input transistor P2 and a third input transistor P3. The connection relationship of the transistors in the first sampling unit 1011 is the same as that shown in Figure 2 and will not be repeated here. The second sampling unit 1021 comprises a fourth input transistor P4, a fifth input transistor P5 and a sixth input transistor P6.

[0061] The connection relationship of the transistors in the second sampling unit 1021 is the same as that shown in Figure 2 and will not be repeated here. The output circuit 103 comprises a first output transistor P7, a second output transistor P8, a third output transistor P9, a fourth output transistor P10, a fifth output transistor N3, a sixth output transistor N4 and a seventh output transistor N5. The connection relationship of the transistors in the output circuit 103 is the same as that shown in Figure 2 and will not be repeated here.

[0062] It should be noted that when the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. The first output transistor P7 to the fourth output transistor P10 are all P-type transistors, and the fifth output transistor N3 to the seventh output transistor N5 are all N-type transistors, wherein the drain of the P-type transistor is the first terminal, the gate of the P-type transistor is the control terminal, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0063] It should also be noted that the second terminal of the third input transistor P3 and the second terminal of the sixth input transistor P6 are connected to the power supply terminal, and the first terminal of the seventh output transistor N5 is connected to the ground terminal.

[0064] The working principles of the first control unit 1012 and the second control unit 1022 are described as follows:

[0065] When the to-be-compared signal DQ is affected and its amplitude becomes large, the first control signal D270B is at a low level, and the second control signal D270 is at a high level. When the clock signal CLK arrives, the first AND gate circuit outputs a low level, the third input transistor N3 is turned on, the second AND gate circuit outputs a high level, and the sixth input transistor N6 is turned off. The first sampling unit 1011 works in the sampling mode, and the second sampling unit 1021 works in the idle mode.

[0066] When the to-be-compared signal DQ is affected and its amplitude becomes small, the first control signal D270B is at a high level, and the second control signal D270 is at a low level. When the clock signal CLK arrives, the first AND gate circuit outputs a high level, the third input transistor N3 is turned off, the second AND gate circuit outputs a low level, and the sixth input transistor N6 is turned on. The first sampling unit 1011 works in the sampling mode, and the second sampling unit 1021 works in the idle mode.

[0067] In an embodiment, the comparator further comprises a reset circuit 104, which comprises a first clocked transistor P1 and a second clocked transistor P2. The connection mode of the transistors in the reset circuit 104 is the same as that in the first control unit 1012 and the second control unit 1022, which will not be described herein again. The first clocked transistor P1 and the second clocked transistor P2 are N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. It should also be noted that the first terminal of the first clocked transistor P1 and the second clocked transistor P2 is connected to the ground terminal. Figure 2

[0068] ​Before the pulse arrives in the clock signal, the inverted clock signal CLKB is input to the first clock transistor P1 and the second clock transistor P2, so as to pull the first ends of the first input transistor N1, the second input transistor N2, the fourth input transistor N4 and the fifth input transistor N5 to low level, so as to realize the reset of the first sampling circuit 101 and the second sampling circuit 102.

[0069] As shown in Figure 4 An embodiment of the present application provides a decision feedback equalization circuit, which comprises four comparators, each of which is provided with six input ends and two output ends, and the four comparators are sequentially marked as a first comparator 100, a second comparator 200, a third comparator 300 and a fourth comparator 400.

[0070] The first input end of the first comparator 100 is used for receiving a to-be-compared signal DQ, the second input end of the first comparator 100 is used for receiving a first reference signal VREFP, the third input end of the first comparator 100 is used for receiving a second reference signal VREFN, the fourth input end and the fifth input end of the first comparator 100 are connected with the output end of the fourth comparator 400 and are used for receiving a first control signal and a second control signal, and the sixth input end of the first comparator 100 is used for receiving a first clock signal CLK_0.

[0071] The first input end of the second comparator 200 is used for receiving the to-be-compared signal DQ, the second input end of the second comparator 200 is used for receiving the first reference signal VREFP, the third input end of the second comparator 200 is used for receiving the second reference signal VREFN, the fourth input end and the fifth input end of the second comparator 200 are connected with the output end of the first comparator 100 and are used for receiving the first control signal and the second control signal, and the sixth input end of the second comparator 200 is used for receiving a second clock signal CLK_90.

[0072] The third comparator 300, the first input end of the third comparator 300 is used for receiving the to-be-compared signal DQ, the second input end of the third comparator 300 is used for receiving the first reference signal VREFP, the third input end of the third comparator 300 is used for receiving the second reference signal VREFN, the fourth input end and the fifth input end of the third comparator 300 are connected with the output end of the second comparator 200 and are used for receiving the first control signal and the second control signal, and the sixth input end of the third comparator 300 is used for receiving a third clock signal CLK_180.

[0073] The fourth comparator 400 has a first input terminal for receiving the signal DQ to be compared, a second input terminal for receiving the first reference signal VREFP, a third input terminal for receiving the second reference signal VREFN, a fourth and fifth input terminal connected to the output terminal of the third comparator 300 for receiving the first and second control signals, and a sixth input terminal for receiving the fourth clock signal CLK_D270.

[0074] In an embodiment, the structure of the comparators in the decision feedback equalization circuit is as shown in FIG. 4, wherein the fifth input terminal of the first comparator 100 is connected to the second output terminal of the fourth comparator 400, and the sixth input terminal of the first comparator 100 is connected to the first output terminal of the fourth comparator 400. Figure 2

[0075] In an embodiment, the structure of the comparators in the decision feedback equalization circuit is as shown in FIG. 4, wherein the fifth input terminal of the first comparator 100 is connected to the second output terminal of the fourth comparator 400, and the sixth input terminal of the first comparator 100 is connected to the first output terminal of the fourth comparator 400. Figure 3

[0076] The working principle of the decision feedback equalization circuit is described as follows: when the first output terminal of the fourth comparator 400 outputs a low signal P270B and the second output terminal outputs a high signal P270, i.e. the result of the comparator is digital "1", it indicates that the signal DQ to be compared received by the fourth comparator 400 is relatively large, and the trend of the influence on the signal DQ to be compared received by the first comparator 100 is to make the signal DQ to be compared larger. Then, the first comparator 100 generates a first differential signal according to the signal DQ to be compared and the first reference signal VREFP which is relatively large in value, and generates a comparison result according to the first differential signal.

[0077] When the first output terminal of the fourth comparator 400 outputs a high signal P270B and the second output terminal outputs a low signal P270, i.e. the result of the comparator is digital "0", it indicates that the signal DQ to be compared received by the fourth comparator 400 is relatively small, and the trend of the influence on the signal DQ to be compared received by the first comparator 100 is to make the signal DQ to be compared smaller. Then, the first comparator 100 generates a second differential signal according to the signal DQ to be compared and the second reference signal VREFN which is relatively small in value, and generates a comparison result according to the second differential signal.

[0078] The working principles of the second comparator 200 to the fourth comparator 400 are the same as that of the first comparator 100, which will not be described herein.

[0079] ​​In one embodiment, the phase of the first clock signal CLK_0 is 90° earlier than the phase of the second clock signal CLK_90, the phase of the first clock signal CLK_0 is 180° earlier than the phase of the third clock signal CLK_180, and the phase of the first clock signal CLK_0 is 270° earlier than the phase of the fourth clock signal CLK_D270.

[0080] In one embodiment, the voltage switching time at the output terminals of the first comparator 100 to the fourth comparator 400 is less than the time interval between the first clock signal CLK_0 and the second clock signal CLK_90. When the switching time of the output voltage of the fourth comparator 400 is less than 1UI, where 1UI represents the time interval between the first clock signal CLK_0 and the second clock signal CLK_90, it can be ensured that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, thereby allowing the first comparator 100 to eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0081] In one embodiment, the decision feedback equalization circuit further includes a first register 500, a second register 600, a third register 700, and a fourth register 800. The input of the first register 500 is connected to the output of the first comparator 100, and the first register 500 stores the comparison result generated by the first comparator 100. The input of the second register 600 is connected to the output of the second comparator 200, and the second register 600 stores the comparison result generated by the second comparator 200. The input of the third register 700 is connected to the output of the third comparator 300, and the third register 700 stores the comparison result generated by the third comparator 300. The input of the fourth register 800 is connected to the output of the fourth comparator 400.

[0082] like Figure 5 As shown, taking the first comparator 100 as an example, the signal timing is explained. When the clock signal arrives, the signal to be compared, DQ, and the output signals of the two AND gate circuits also arrive. After being processed by the first comparator 100, the output signal is output through the output terminal of the comparator to show the comparison result. Then, the first register 500 saves the data.

[0083] In the above technical solution, by cascading four comparators together, that is, connecting the output of the previous comparator to the input of the current comparator, the sampling circuit in the current comparator is controlled by the output of the previous comparator, so as to eliminate the influence of the previous signal to be compared DQ on the current signal to be compared DQ, thereby improving the accuracy of the comparator comparison result. After storing the comparison result in four registers, the data D0, D90, D180 and D270 are output, which can realize the continuous output of multiple comparison results.

[0084] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0085] It is to be understood that the application is not limited to the precise construction herein disclosed and shown in the drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the claims that follow.

Claims

1. A comparator, characterized by The application relates to a differential signal comparison circuit. The first sampling circuit is provided with an output end for generating a first differential signal according to a to-be-compared signal and a first reference signal under the control of a first control signal and a clock signal, and comprises a first sampling unit and a first control unit; the first sampling unit is provided with a control end for generating the first differential signal according to the to-be-compared signal and the first reference signal when working in a sampling mode; the output end of the first control unit is connected with the control end of the first sampling unit, and the first control unit is used for controlling the working mode of the first sampling unit according to the first control signal and the clock signal; wherein the working mode comprises the sampling mode; the first control unit particularly comprises a first AND gate circuit, the first input end of the first AND gate circuit is used for receiving the first control signal, the second input end of the first AND gate circuit is used for receiving the clock signal, and the output end of the first AND gate circuit serves as the output end of the first control unit. The second sampling circuit is provided with an output end, and the output end of the second sampling circuit is connected with the output end of the first sampling circuit, and is used for generating a second differential signal according to the to-be-compared signal and a second reference signal under the control of a second control signal and the clock signal; wherein the first reference signal is greater than the second reference signal; the second sampling circuit comprises a second sampling unit and a second control unit; the second sampling unit is provided with a control end for generating the second differential signal according to the to-be-compared signal and the second reference signal when working in a sampling mode; the output end of the second control unit is connected with the control end of the second sampling unit, and the second control unit is used for controlling the working mode of the second sampling unit according to the second control signal and the clock signal; wherein the working mode comprises the sampling mode; the first control signal and the second control signal are mutually opposite signals; the second control unit particularly comprises a second AND gate circuit, the first input end of the second AND gate circuit is used for receiving the second control signal, the second input end of the second AND gate circuit is used for receiving the clock signal, and the output end of the second AND gate circuit serves as the output end of the second control unit. The output circuit is provided with an input end, and the input end of the output circuit is connected with the output end of the first sampling circuit; when the to-be-compared signal is greatly interfered by inter-symbol interference, the output circuit is used for amplifying and latching the voltage signal of the output end of the first sampling circuit and outputting a comparison result; when the to-be-compared signal is slightly interfered by inter-symbol interference, the output circuit is used for amplifying and latching the voltage signal of the output end of the second sampling circuit and outputting a comparison result.

2. The comparator of claim 1, wherein, The first sampling unit comprises: a first input transistor, the control end of the first input transistor is used for receiving the first reference signal, and the first end of the first input transistor serves as the first output end of the first sampling unit; a second input transistor, the control end of the second input transistor is used for receiving the to-be-compared signal, and the first end of the second input transistor serves as the second output end of the first sampling unit; a third input transistor, the control end of the third input transistor serves as the control end of the first sampling unit, the first end of the third input transistor is connected with the second end of the first input transistor and the second end of the second input transistor, and the second end of the third input transistor is connected with a grounding end or a power supply end.

3. The comparator of claim 1, wherein, The second sampling unit comprises: a fourth input transistor, a control terminal of which is arranged to receive the second reference signal, and a first terminal of which is arranged to be a first output terminal of the second sampling unit; a fifth input transistor, a control terminal of which is arranged to receive the signal to be compared, and a first terminal of which is arranged to be a second output terminal of the second sampling unit; a sixth input transistor, a control terminal of which is arranged to be a control terminal of the second sampling unit, a first terminal of which is connected to a second terminal of the fourth input transistor and a second terminal of the fifth input transistor, and a second terminal of which is connected to a ground terminal or a power supply terminal.

4. The comparator of claim 2, wherein, The first input transistor to the sixth input transistor are of the same type.

5. The comparator of claim 4, wherein, when the first input transistor to the sixth input transistor are N-type transistors, a drain of the N-type transistor is the first terminal, and a gate of the N-type transistor is the control terminal; when the first input transistor to the sixth input transistor are P-type transistors, a drain of the P-type transistor is the first terminal, and a gate of the P-type transistor is the control terminal.

6. The comparator of claim 1, wherein, The output circuit comprises: a first output transistor, a control terminal of which is arranged to be a first input terminal of the output circuit, a first terminal of which is arranged to be a first output terminal of the output circuit, and a second terminal of which is connected to a ground terminal or a power supply terminal; a second output transistor, a control terminal of which is arranged to be a second input terminal of the output circuit, a first terminal of which is arranged to be a second output terminal of the output circuit, and a second terminal of which is connected to a ground terminal or a power supply terminal; a third output transistor, a first terminal of which is connected to the first terminal of the first output transistor, and a second terminal of which is connected to the second terminal of the first output transistor; a fourth output transistor, a first terminal of which is connected to the first terminal of the second output transistor, and a second terminal of which is connected to the second terminal of the second output transistor; a fifth output transistor, a second terminal of which is connected to the first terminal of the third output transistor, a control terminal of which is connected to the control terminal of the third output transistor, and a control terminal of which is further connected to the first terminal of the fourth output transistor; a sixth output transistor, a second terminal of which is connected to the first terminal of the fourth output transistor, a control terminal of which is connected to the control terminal of the fourth output transistor, and a control terminal of which is further connected to the first terminal of the third output transistor; a seventh output transistor, a control terminal of which is arranged to receive the clock signal, a first terminal of which is connected to a power supply terminal or a ground terminal, and a second terminal of which is connected to the first terminal of the fifth output transistor and the first terminal of the sixth output transistor.

7. The comparator of claim 6, wherein, the first output transistor to the fourth output transistor are N-type transistors, and the fifth output transistor to the seventh output transistor are P-type transistors, wherein a drain of the N-type transistor is the first terminal, a gate of the N-type transistor is the control terminal, a source of the P-type transistor is the first terminal, and a gate of the P-type transistor is the control terminal; or the first output transistor to the fourth output transistor are P-type transistors, and the fifth output transistor to the seventh output transistor are N-type transistors, wherein a drain of the P-type transistor is the first terminal, a gate of the P-type transistor is the control terminal, a source of the N-type transistor is the first terminal, and a gate of the N-type transistor is the control terminal. The comparator further comprises:

8. The comparator of claim 1, wherein, ​ A reset circuit is connected to the first sampling circuit and the second sampling circuit, and is configured to reset voltages of the first sampling circuit and the second sampling circuit.

9. The comparator of claim 8, wherein, The reset circuit comprises: A first clocked transistor, a control terminal of which receives the clock signal, a first terminal of which is connected to a power supply terminal or a ground terminal, and a second terminal of which is connected to a first terminal of the first input transistor and a first terminal of the fourth input transistor; A second clocked transistor, a control terminal of which receives the clock signal, a first terminal of which is connected to a power supply terminal or a ground terminal, and a second terminal of which is connected to a first terminal of the second input transistor and a first terminal of the fifth input transistor.

10. A decision feedback equalization circuit, comprising: The comparator comprises four comparators as claimed in any one of claims 1 to 9, which are sequentially marked as a first comparator, a second comparator, a third comparator, and a fourth comparator; The first comparator, a first input terminal of which is configured to receive the signal to be compared, a second input terminal of which is configured to receive the first reference signal, a third input terminal of which is configured to receive the second reference signal, a fourth input terminal and a fifth input terminal of which are connected to an output terminal of the fourth comparator, and are configured to receive a first control signal and a second control signal, and a sixth input terminal of which is configured to receive a first clock signal; The second comparator, a first input terminal of which is configured to receive the signal to be compared, a second input terminal of which is configured to receive the first reference signal, a third input terminal of which is configured to receive the second reference signal, a fourth input terminal and a fifth input terminal of which are connected to an output terminal of the first comparator, and are configured to receive the first control signal and the second control signal, and a sixth input terminal of which is configured to receive a second clock signal; The third comparator, a first input terminal of which is configured to receive the signal to be compared, a second input terminal of which is configured to receive the first reference signal, a third input terminal of which is configured to receive the second reference signal, a fourth input terminal and a fifth input terminal of which are connected to an output terminal of the second comparator, and are configured to receive the first control signal and the second control signal, and a sixth input terminal of which is configured to receive a third clock signal; The fourth comparator, a first input terminal of which is configured to receive the signal to be compared, a second input terminal of which is configured to receive the first reference signal, a third input terminal of which is configured to receive the second reference signal, a fourth input terminal and a fifth input terminal of which are connected to an output terminal of the third comparator, and are configured to receive the first control signal and the second control signal, and a sixth input terminal of which is configured to receive a fourth clock signal.

11. The decision feedback equalization circuit of claim 10, wherein: a phase of the first clock signal is 90° earlier than a phase of the second clock signal; a phase of the first clock signal is 180° earlier than a phase of the third clock signal; a phase of the first clock signal is 270° earlier than a phase of the fourth clock signal.

12. The decision feedback equalization circuit of claim 10, wherein: a voltage transition time of the output terminals of the first comparator to the fourth comparator is less than a time interval between the first clock signal and the second clock signal.

13. The decision feedback equalization circuit of any one of claims 10 to 12, wherein, The decision feedback equalization circuit further comprises: a first register, an input terminal of which is connected to the output terminal of the first comparator; a second register, an input terminal of which is connected to the output terminal of the second comparator; a third register having an input connected to an output of the third comparator; a fourth register having an input connected to an output of the fourth comparator.

Images