Image sensor with control circuit

Abstract

Embodiments of this disclosure relate to an image sensor having control circuitry. An image sensor includes a pixel array inside and on top of a substrate. The control circuitry is configured to apply a voltage potential to the substrate. During a first phase, the control circuitry applies a ground potential to the substrate. During a second phase, the control circuitry applies a potential that is positive relative to the ground potential to the substrate.

Description

[0001] priority

[0002] This application claims priority to French patent application No. 2109100, filed on August 31, 2021, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This invention generally relates to sensors, and more specifically, to image sensors. Background Technology

[0004] Sensors, especially image sensors, are being used more and more frequently and are standard in many electronic devices, such as mobile phones (smartphones).

[0005] Especially in the case of global shutter image sensors, the circuitry of an image sensor pixel includes one or more transfer gates capable of transferring voltage or charge between storage locations within the pixel. To avoid significant leakage current during this transfer, it is generally desirable to drive the gates with a voltage that switches between positive and negative levels. The disadvantage of this drive is that it requires high power from the power supply circuitry delivering these voltages, especially for significant switching frequencies. This results in significant power consumption.

[0006] There is a need to improve existing image sensors. Summary of the Invention

[0007] The embodiments overcome all or part of the shortcomings of known image sensors, particularly image sensors of the indirect time-of-flight and / or global shutter type.

[0008] An embodiment provides an image sensor including: a pixel array inside and on top of a substrate; and control circuitry configured to apply to the substrate: a ground potential during a first phase; and a potential that is positive relative to the ground potential during a second phase.

[0009] An embodiment provides a method for controlling such an image sensor, the image sensor including: a pixel array inside and on top of a substrate; and control circuitry; wherein in the method, the control circuitry is configured to apply to the substrate: a ground potential during a first phase; and a potential that is positive relative to the ground potential during a second phase.

[0010] According to an embodiment, each pixel includes: a first region configured to generate charge from light emission excitation, and at least two components, each component including: a second region configured to store charge originating from the first region; and a first transfer gate configured to control charge transfer between the first region and the second region.

[0011] According to an embodiment, the control circuit is configured to allow, for each first transfer gate of each component of each pixel, to be set to a conductive state by applying a third potential to the first transfer gate, and to be set to a non-conductive state by applying a fourth potential less than the third potential to the first transfer gate.

[0012] According to an embodiment, a first potential is determined such that when the first potential is applied to the substrate and a fourth potential is applied to the first transfer gate, the first transfer gate is not conductive, and the fourth potential is equal to or less than the potential of the substrate.

[0013] According to an embodiment, the control circuit is configured to lower the fourth potential between the second stage and the first stage.

[0014] According to an embodiment, each pixel includes a second circuit that couples a memory component to at least one conductive line. The second circuit includes a second transfer gate that is driven by a control circuit and configured to allow charge stored at a level in a second region to be transferred to a sensing node. The control circuit is configured to reduce the value of a first potential by a fifth potential applied to the second transfer gate between a second phase and a first phase.

[0015] According to an embodiment, the second circuit includes: a first transistor having a drain coupled to a first sensing node; a second transistor having a control gate coupled to the first node; a third transistor connected between a wire and the source of the second transistor, and a control circuit configured to decrease by a value of a first potential between a second stage and a first stage: a sixth potential applied to a second transfer gate; and a seventh potential and an eighth potential for controlling the first transistor.

[0016] According to an embodiment, the control circuit includes: a fourth PMOS transistor configured to be controlled independently of a fifth NMOS transistor, the drain of the fourth transistor being coupled to the drain of the fifth transistor at a level at the second node, and the source of the fourth transistor being further coupled to a power rail; the source of the fifth transistor being further coupled to ground; a first switch connected between the second and fourth nodes; a second switch connected between ground and the fourth node; a second capacitor element connected between the third and fourth nodes; a voltage source configured to deliver a first potential, the source being connected between ground and the third switch; a third switch connected between the voltage source and the third node; a fourth switch connected between ground and the third node; and a first transfer gate coupled to the second node.

[0017] According to an embodiment, between the second stage and the first stage, the fourth transistor and the fifth transistor are driven such that the fourth transistor is in a non-conductive state and the fifth transistor is in a conductive state; then, the fourth transistor and the fifth transistor are driven independently to be in a non-conductive state; then, the third switch is set to a non-conductive state; then, the second switch is set to a non-conductive state; then, the first switch and the fourth switch are set to a conductive state.

[0018] According to an embodiment, the first stage and the second stage alternate in time, and between the first stage and the second stage, the first switch and the fourth switch are set to a non-conductive state; then, the second switch is set to a conductive state; then, the third switch is set to a conductive state; then, the fourth transistor and the fifth transistor are driven to conduct alternately.

[0019] According to an embodiment, the second stage corresponds to the stage of transferring and storing charge generated by the first region of each pixel in at least one region of the second region of the pixel; and the first stage corresponds to the stage of reading the state of the charge stored in the storage region.

[0020] According to one embodiment, the image sensor is of the indirect time-of-flight type. Attached Figure Description

[0021] The foregoing features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, in which specific embodiments are given by way of illustration rather than limitation, wherein:

[0022] Figure 1 An image sensor according to an embodiment of this specification is illustrated schematically;

[0023] Figure 2A It is shown Figure 1 A timing diagram of an example of the driving signals in an image sensor;

[0024] Figure 2B This illustrates an embodiment according to this specification. Figure 1 Timing diagram of the driving signals in the image sensor;

[0025] Figure 3A According to the embodiments of this specification Figure 1 A cross-sectional view of the image sensor;

[0026] Figure 3B According to another embodiment of this specification Figure 1 A cross-sectional view of the image sensor;

[0027] Figure 4 An example of a pixel in an image sensor according to an embodiment of this specification is illustrated schematically;

[0028] Figure 5 An embodiment according to this specification is illustrated schematically. Figure 1 and Figure 4 The control circuit of the image sensor; and

[0029] Figure 6 It is shown Figure 5 A timing diagram of an example of signals in a control circuit. Detailed Implementation

[0030] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0031] For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0032] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0033] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or when referring to relative position qualifiers such as the terms “above,” “below,” “over,” “under,” etc., or when referring to orientation qualifiers such as “horizontal,” “vertical,” etc., refer to the orientation shown in the figure.

[0034] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “around” indicate within 10%, preferably within 5%.

[0035] Figure 1 An image sensor 2 according to an embodiment of this specification is schematically shown. The image sensor 2 includes a pixel array 100 and a control circuit 20.

[0036] Image sensor 2 is, for example, a global shutter image sensor. In some cases, image sensor 2 is an indirect time-of-flight (“iToF”) type sensor, configured to determine an embossed image of the scene to be captured. For example, each pixel of array 100 includes one or more photodiodes.

[0037] The control circuit 20 is powered, for example, by a positive power supply voltage rail VDD and a ground potential rail GND. The control circuit 20 is configured, for example, to transmit control signals to the pixels of array 100. For instance, the control circuit is configured to transmit a base plate potential Vpixsub and at least one transfer gate control voltage VTSFR. For example, the pixels of array 100 include one or more transfer gates controlled by the transfer gate control voltage, allowing voltage or charge transfer between storage locations within the pixel. The base plate potential determines the bias under the transfer gate and also corresponds to the potential of the anode of the photodiode.

[0038] Figure 2A This indicates the process during the integration and readout phases. Figure 1 The timing diagram of the driving signals in image sensor 2, particularly the potential Vpixsub and voltage VTSFR, is shown. For example, the integration phase is a phase shared by all pixels of array 100. During the integration phase, charge is generated by light in the pixel by photodiodes and is stored, for example, in a storage location within the pixel. During the readout phase, for example, the signal representing the light-generated charge of each pixel is read out line by line.

[0039] exist Figure 2A In the example, the potential Vpixsub remains grounded during the integration and readout phases. During the integration and readout phases, the voltage VTSFR switches between a positive level of, for example, 2V (VTSFR_HI) and a negative level of, for example, between -0.3V and -1.3V (VTSFR_LO) to selectively activate and disable the transfer gate of the pixel.

[0040] The voltage level VTSFR_LO is used, for example, to disable the transfer gates, i.e., to keep them non-conductive. Using a negative level has the advantage of reducing leakage current of these transfer gates. However, the disadvantage of the control circuit 20 generating positive and negative voltages for the signal VTSFR is that the circuit is complex and the power and power consumption provided by the circuit are high, especially for significant switching frequencies. This is particularly true for these iToF type image sensors.

[0041] Figure 2B This illustrates an embodiment according to this specification. Figure 1 During the integration and readout phases in an image sensor Figure 1 The timing diagram of the driving signals in image sensor 2, specifically the potential Vpixsub and voltage VTSFR.

[0042] exist Figure 2BIn the example, the potential Vpixsub remains at a positive level Vpixsub1 during the integration phase and at a level Vpixsub2, which is lower than Vpixsub1, during the readout phase. Level Vpixsub2 is, for example, ground. During both the integration and readout phases, the voltage VTSFR switches between a level VTSFR_HI, for example, 2V, and a level VTSFR_LO, which is lower than VTSFR_HI. Level VTSFR_LO is, for example, ground during the integration phase. In some cases, level VTSFR_LO is lower during the readout phase than during the integration phase; for example, it may be a negative voltage in the range of -0.3 to -1.3V.

[0043] The advantage of using a positive base potential during the integration phase is that it allows the low level of voltage VTSFR_LO to be grounded (0V), while ensuring that the transfer gate is disabled and therefore non-conductive, as voltage VTSFR_LO remains below the base potential Vpixsub1. Grounding VTSFR_LO eliminates the need for control circuitry 20 to generate a negative power supply. This is particularly advantageous at high switching frequencies, as the power to be supplied is determined by CV. 2 The value of f is determined, where C is the capacitance of the control line, V is the voltage amplitude, and f is the switching frequency. Switching such a current from a positive to a negative power supply requires the use of a charge pump that consumes a significant amount of energy. Furthermore, the base potential Vpixsub1 is static during the integration phase, and the generation of this positive potential has a limited impact on power consumption. Regarding the generation of the negative voltage VTSFR_LO during the readout phase, the power required to maintain the non-conductive state of the transfer gate is very low, or even zero, allowing for a simple solution to generate this voltage.

[0044] The advantage of using a ground base potential during the readout phase is that this potential is noise-free by definition. If the signal reference is Vpixsub1 instead of ground, the reference noise will not be zero, but will be particularly limited by the power supply rejection of voltage Vpixsub1.

[0045] Now we will combine Figure 3A and 3B Describe a specific example of applying base potential levels Vpixsub1 and Vpixsub2 to the pixels of image sensor 2.

[0046] Figure 3A According to the embodiments of this specification Figure 1 A cross-sectional view of image sensor 2.

[0047] exist Figure 3AIn the cross-sectional view, a substrate 40 and two pixels 10 are visible. In this example, a first region 40a (in other words, a first substrate 40a) is bonded to the substrate 40 by, for example, molecular bonding. An array 100 of pixels 10 of the image sensor 2 is arranged inside and on top of the first region 40a of the substrate 40 of the image sensor 2. In other words, the first region 40a forms the substrate for the pixels 10. The remainder of the substrate 40 may include multilayer microelectronic components such as transistors and vias.

[0048] The first region 40a and the substrate 40 are formed, for example, in a semiconductor material, and may be the same or different between the first region 40a and the rest of the substrate 40.

[0049] The first region 40a is electrically insulated from the rest of the substrate 40, for example, by an insulating layer. Therefore, it is possible for different potentials to exist at the level of the first region 40a and at the level of the rest of the substrate 40.

[0050] The control circuit 20 of the image sensor 2 enables a potential Vpixsub1 to be applied to the first region 40a during the integration phase, this potential being positive, for example, relative to the potential applied to the substrate 40. The potential applied to the substrate 40 may be equal to the ground potential (GND). During the readout phase, the control circuit 20 of the image sensor 2 is able to apply a potential Vpixsub2 to the first region 40a, this potential being, for example, equal to the ground potential (GND) of the substrate 40. In this example, the substrate 40 includes the control circuit 20.

[0051] Figure 3B According to another embodiment of the present invention Figure 1 A cross-sectional view of image sensor 2.

[0052] exist Figure 3B In the cross-sectional view, we can see the base 40 and three pixels 10.

[0053] An array 100 of pixels 10 of image sensor 2 is arranged inside and on top of the first region 40a of the base 40 of image sensor 2.

[0054] The substrate 40 and the first region 40a are formed, for example, in a semiconductor material, and may be the same or different between the first region 40a and the rest of the substrate 40.

[0055] The first region 40a is electrically insulated from the rest of the substrate 40. Therefore, it is possible for different potentials to exist at the level of the first region 40a and at the level of the rest of the substrate 40.

[0056] exist Figure 3BIn the example shown, to obtain electrical insulation of the first region 40a from the rest of the substrate 40, an insulating structure or trench 40b surrounds each pixel 10 individually. The insulating structure 40b may also surround the entire pixel array 100. The insulating trench 40b spans the entire thickness of the substrate 40 to ensure electrical insulation.

[0057] In the example, structure 40b is a capacitive deep trench insulation structure and corresponds to a trench filled with a conductive material that is insulated from the substrate by an electrically insulating layer. In other examples not shown, these structures are deep trench insulation (DTI) structures, corresponding to trenches completely filled with an insulator.

[0058] During the integration phase, the control circuit 20 of the image sensor 2 is able to apply a potential Vpixsub1 to the first region 40a, where the potential Vpixsub1 is positive, for example, relative to the potential (GND) of the substrate 40.

[0059] During the readout phase, the control circuit 20 of the image sensor 2 enables the application of a potential, for example, equal to the potential (GND) of the substrate 40, to the first region 40a, called Vpixsub2.

[0060] Figure 4 schematically shown Figure 1 The circuitry of image sensor 2. More specifically, Figure 4 An example of pixel 10 of image sensor 2 in the case of indirect time-of-flight type pixels is shown.

[0061] Image sensor 2 includes an array 100 of pixels 10 (one of which is composed of...) Figure 4 (shown) and control circuit 20.

[0062] exist Figure 4 In the illustrated embodiment, each pixel 10 of the array includes a light conversion region (PD), such as a photodiode, preferably a pinned photodiode. Electrons accumulate on the cathode of the photodiode, and light-generating holes discharge to the substrate.

[0063] In the example shown, where the useful light-generating charge, i.e., the charge that has already accumulated in the first region PD, is electrons, the anode of the photodiode PD is arranged to contact a node N11 that applies a potential Vpixsub1 or a potential Vpixsub2 in a local portion of the pixel-level substrate.

[0064] Pixel 10 includes at least two identical circuit components, for example Figure 4The example shows two components, E1 and E2, which are defined by dashed lines. Each component E1, E2 includes a storage region referred to as a second region (mem1, mem2) and a transfer gate (TGmem1, TGmem2) that couples the storage region of the component to the cathode of a photodiode. For example, in components E1 and E2, the transfer gates TGmem1 and TGmem2 are configured to transfer charge between the cathode of the photodiode and the storage regions mem1 and mem2.

[0065] exist Figure 4 In the example, each memory region mem1, mem2 is implemented by a pinned diode. In each component E1, E2, the memory regions mem1, mem2 are configured to store charge. Transfer gates TGmem1, TGmem2 enable charge transfer between the photodiode PD and the memory regions mem1, mem2. The anodes of the diodes in the memory regions mem1, mem2 are connected to nodes 108 where potentials Vpixsub1 and Vpixsub2 are applied.

[0066] Each transfer gate TGmem1, TGmem2 receives, for example, a control signal (VTGmem1, VTGmem2) formed by control potentials VTGmemHI1, VTGmemHI2 or control potentials VTGmemLO1, VTGmemLO2 from the control circuit 20.

[0067] For example, the transfer gates TGmem1 and TGmem2 are configured to be turned on when potentials VTGmemHI1 and VTGmemHI2 are applied thereon.

[0068] For example, the transfer gates TGmem1 and TGmem2 are further configured to be in a turn-off state when potentials VTGmemLO1 and VTGmemLO2 are applied thereon.

[0069] exist Figure 4 In the example shown, pixel 10 includes an anti-halo device (TAB). For example, the device TAB is a transistor that receives a potential (VAB) on its gate. The device TAB is connected between the cathode of the photodiode PD and the node that applies the power supply potential VDD to pixel 10.

[0070] exist Figure 4 In the example, pixel 10 further includes a second circuit 30 (composed of... Figure 4 (Delimited by dashed lines in the diagram). The second circuit 30 couples the components E1 and E2 of pixel 10 to one or more wires V, for example, shared by all pixels in the same column of the pixel array. X .exist Figure 4 In the example, the second circuit 30 is connected to a single wire V. XWhen pixel 10 is selected during the second readout phase (e.g., when all pixels in the same row of the pixel array are selected), the second circuit 30 is configured to deliver a signal representing the state of the pixel's memory areas mem1 and mem2 to the line V to which the second circuit 30 is connected. X Above. These signals, for example, represent the number of charges transferred from region PD to each of regions mem1 and mem2 during the integration phase prior to the readout phase.

[0071] The second circuit 30 also includes transfer devices, such as transfer gates TGread1 and TGread2, which are driven by the control circuit 20 and configured to allow the transfer of charge stored at the levels of regions mem1 and mem2.

[0072] Transfer gates TGread1 and TGread2 are configured to transfer charge between memory regions mem1 and mem2 and the sensing node SN of circuit 30, respectively.

[0073] Transfer gates TGread1 and TGread2 receive control signals VTGread1 and VTGread2, respectively. As an example, potentials VTGread_LO1 and VTGread_LO2 block transfer gates TGRead1 and TGRead2, respectively, making node SN electrically insulated from memory regions mem1 and mem2. The potentials VTGReadHI1 and VTGReadHI2 of signals VTGread1 and VTGread2 conduct transfer gates TGread1 and TGread2, such that the potential of node SN is determined by the amount of charge previously present in memory regions mem1 and mem2, respectively. Potentials VTGReadHI1 and VTGReadHI2 are, for example, identical. Similarly, potentials VTGreadLO1 and VTGreadLO2 are identical.

[0074] exist Figure 4 In the example, the second circuit 30 also includes a transistor RST. The transistor RST is connected between node SN and node 120 to which a reset potential VRST, for example equal to potential VDD, is applied. The transistor RST receives a control signal RST. As an example, the potential RSTH1 of the signal RST turns on the transistor RST, for example, resetting node SN to potential VRST, and the potential of the signal RST (RSTLO) turns off the transistor RST, making node SN electrically isolated from node 120.

[0075] exist Figure 4 In the example, the second circuit 30 also includes a connection to wire V. X The transistor TRS is located between the source of transistor SF in the second circuit 30.

[0076] The gate of transistor SF is coupled (e.g., connected) to node SN, its source is coupled (e.g., connected) to transistor TRS, and its drain is coupled (e.g., connected) to node 122 where a potential (e.g., potential VDD) is applied.

[0077] Transistor TRS receives a control signal RS on its gate. As an example, a first level or state of signal RS turns on transistor TRS and couples to line V. X Current source ( Figure 4 (not shown in the image) is activated, causing transistor SF to operate as a source follower, and line V... X The potential on the line is then determined by the potential of node SN. The second level of signal RS turns on transistor TRS, causing line V to... X The potential on the node is independent of the potential of node SN.

[0078] During the integration phase of light reflected from the scene to be captured, each control signal VTGmem1, VTGmem2 periodically switches between potentials VTGmemHI1, VTGmemHI2 and VTGmemLO1, VTGmemLO2, respectively. Potentials VTGmemHI1 and VTGmemHI2 are, for example, identical. Similarly, potentials VTGmemLO1 and VTGmemLO2 are, for example, identical. When the first gate is conductive, the photogenerated charge accumulated in region PD is transferred to the memory region associated with the transfer gate. For example, when control signals VTGmem1, VTGmem2 are applied to gates TGmem1, TGmem2 respectively at potentials VTGmemHI1, VTGmemHI2, the charge accumulated in region PD is attracted below the gate, and then the control signals switch to potentials VTGmemLO1, VTGmemLO2, causing these charges to be transferred to memory regions mem1, mem2, respectively.

[0079] In the example, the integration phase includes multiple charge transfer phases.

[0080] Each of the transfer gates TGmem1 and TGmem2 is alternately set to a non-conductive state (no charge transfers from region PD to the corresponding storage region mem1 or mem2) and a conductive state (charge transfers from region PD to the corresponding storage region mem1 or mem2) at frequencies, for example, greater than 50 MHz, preferably on the order of one or several hundred MHz. The necessary supply power increases with this frequency. The levels of signals VTGmem1 and VTGmem2 are generated, for example, like the level of the voltage VTRSF described above, and therefore the generation of these signals does not require the use of a positive power supply alternating with a negative power supply.

[0081] Control signals VTGmem1 and VTGmem2 are configured to alternately transfer charge accumulated in region PD to each memory region of pixel 10, as is known to those skilled in the art. Specifically, it is known to those skilled in the art that control signals VTGmem1 and VTGmem2 are phase-shifted and configured such that while charge is being transferred to one of these regions mem1 and mem2, no charge is being transferred to the other of memory regions mem1 or mem2. In one example, control signal VTGmem1 is high only when control signal VTGmem2 is low, and control signal VTGmem2 is high only when control signal VTGmem1 is low. In another example, the pulses of each control signal VTGmem1 and VTGmem2 have the same width.

[0082] In the example, the value of potential Vpixsub1 is determined such that when potential Vpixsub1 is locally applied to the level base of pixel 10 and the gate is at potentials VTGmemLO1 and VTGmemLO2, the transfer gates TGmem1 and TGmem2 are not conductive.

[0083] As an example, the potential Vpixsub1 is positive and less than 1.5V, and for example, approximately equal to 0.3V. Potential Vpixsub1 is applied to the entire substrate of pixel 10, thus forming the substrate voltage of transfer gates TGmem1 and TGmem2. When transfer gates TGmem1 and TGmem2 receive a control potential equal to ground potential GND, they become non-conductive. When transfer gates TGmem1 and TGmem2 receive a control potential greater than a positive threshold, they become conductive.

[0084] In the example, control circuit 20 includes a voltage regulator or voltage source configured to deliver voltage Vpixsub1. Preferably, control circuit 20 is directly connected to a reference ground potential GND.

[0085] In the example shown in Table 1, the control circuit 20 lowers the values ​​of potentials VPGmemLO1 and VPGmemLO2 by the value of potential Vpixsub1 between the integration and readout phases. An advantage of this implementation is that even if the substrate at the level of pixel 10 is locally at a potential of 0V, in other words, at ground potential GND, potentials VPGmemLO1 and VPGmemLO2 remain below this potential. This makes it possible to determine that gates TGmem1 and TGmem2 are effectively and robustly in a non-conductive state during the readout phase.

[0086] Table 1

[0087]

[0088] The advantage associated with the fact that potentials VTGmemLO1 and VTGmemLO2 are grounded during the integration phase is that no negative voltage is required.

[0089] During the readout phase, although the potentials VTGmemLO1 and VTGmemLO2 are negative, the power supplied by the power supply at the gate levels TGmem1 and TGmem2 is low or even zero, because there is no gate switching during the readout phase and therefore no current is consumed.

[0090] Taking this fact into account, according to the example, during the readout phase, potentials VTGmemLO1 and VTGmemLO2 are capacitively applied.

[0091] In an example that can be combined with the preceding examples, particularly the example in Table 1, control circuit 20 lowers the values ​​of potentials VPGReadLO1 and VPGReadLO2 to the value of potential Vpixsub1 between the integration and readout phases. This makes it possible to determine that potentials VPGReadLO1 and VPGReadLO2 effectively follow the local bias of the substrate at the level of pixel 10, i.e., maintain a relative voltage at the level of pixel 10. The potential changes are illustrated in Table 2 in conjunction with the example in Table 1.

[0092] Table 2

[0093]

[0094]

[0095] In an example that can be combined with the examples in Tables 1 and 2, the control circuit 20 lowers the values ​​of potentials VPGReadHI1 and VPGReadHI2 and potential Vpixsub1 between the integration and readout phases. This allows for maintaining a relative voltage at the level of pixel 10.

[0096] Between the integration and readout phases, the control potentials RSTH1 and RSTL0 of the first transistor RST can optionally be reduced to the value of potential Vpixsub1. This allows for maintaining a relative voltage at the level of pixel 10. Table 3 illustrates this situation.

[0097] Table 3

[0098]

[0099] exist Figure 4 and Figure 5In the example, the transfer gate, switch, and transistor are preferably MOS type.

[0100] Figure 5 An embodiment according to this specification is illustrated schematically. Figure 1 and 4 The control circuit 20 for the image sensor. Figure 5 The example is based on the situation where, during the readout phase, the power supplied by the power sources at gate levels TGmem1 and TGmem2 is preferably zero, respectively.

[0101] Specifically, Figure 5 A portion of control circuitry 20 is shown, which is configured to generate a voltage VTGmem1 (pixels are not fully shown; only transistors TGmem1 of some pixels are shown) applied to the transfer gate TGmem1 of the pixels included in pixel column 500. Control circuitry 20 is also configured to generate a potential Vpixsub applied to the substrate of the pixels in pixel column 500, and particularly to the substrate node of the transfer gate TGmem1. Figure 5 An example with two pixel columns 500 is shown, although in practice there can be hundreds or thousands of columns 500 powered by the control circuitry 20.

[0102] Parasitic capacitance C2 exists, for example, in each pixel column 500, between the transfer gate TGmem1 and the base nodes of these transfer gates TGmem1 (corresponding to base region 40a). Furthermore, capacitive elements C4 exist between the base nodes of the transfer gates TGmem1 in all pixel columns 500 and the rest of the substrate (corresponding to general substrate 40). Although Figure 5 Not shown, but control circuit 20 may include, for example, similar circuitry to generate voltage VTGmem2 applied to the gate of transistor TGmem2 of the pixels of pixel column 500.

[0103] Circuit 20 includes a pair of transistors T4 and T5 in each pixel column 500, series-coupled between the power rail VDD and the ground rail GND. Transistor T4 is, for example, a PMOS transistor, and transistor T5 is, for example, an NMOS transistor, and they are series-coupled, for example, through their drains. An intermediate node N2 between transistors T4 and T5 is coupled (e.g., connected) to the transfer gate TGmem1 of the pixel in the corresponding pixel column 500, and delivers a voltage VTGmem1. Transistors T4 and T5 are controlled independently of each other. For example, control circuit 20 includes a driver circuit 22 configured to generate signals ST4 and ST5 to drive the gates of transistors T4 and T5 in each column, for example, via inverters.

[0104] The control circuit 20 also includes a switch K1 in each column that couples node N2 to node N4. The control circuit 20 also includes a switch K3 that couples node N4 to the ground potential rail GND, and a switch K2 connected between node N3 and the ground potential rail GND. Node N3 is coupled (e.g., connected) to the base node of the pixel in each pixel column, specifically the base node of transistor TGmem1, and delivers a potential Vpixsub. Node N3 is also coupled to a voltage source 21 via switch K4, which is coupled to ground, for example. The voltage source 21 is configured to generate a potential Vpixsub1, for example, approximately 300 mV. A capacitor element C1 is connected, for example, between node N3 and node N4. This capacitor element C1 is formed, for example, by a capacitor external to the control circuit 20. Switches K1, K2, K3, and K4 are controlled, for example, by corresponding control signals SK1, SK2, SK3, and SK4, which are generated, for example, by the driver circuit 22. Switches K1, K2, K3, and K4 are formed, for example, by transistors (e.g., MOS type).

[0105] During the integration phase of the pixels in pixel column 500, switches K1 and K2 are, for example, in the off state, while switches K3 and K4 are, for example, in the on state, causing node N3 and therefore the potential Vpixsub to be at level Vpixsub1. Within each pixel column 500, transistors T4 and T5 are alternately driven to activate and deactivate transfer gate TGmem1.

[0106] To propagate to the readout stage, control switches K1 through K4 reduce the potential Vpixsub to, for example, 0V, and the voltage VTGmem1 to, for example, -300mV. Reference will now be made. Figure 6 A further detailed explanation is needed.

[0107] Figure 6 It is shown Figure 5 A timing diagram of an example of the signals in the control circuit 20. Figure 6 Specifically, an example is shown of the voltage signal VTGmem1 based on the activation of transistors T4 and T5 by control signals ST4 and ST5, and the activation of switches K1, K2, K3, and K4 by control signals SK1, SK2, SK3, and SK4. By convention, when the control signals are high, [the voltage signal VTGmem1 is used in conjunction with the control signals ST4 and ST5]. Figure 6 The described switch is in the ON state, although it can be reversed in practice.

[0108] Figure 6The diagram illustrates several switching cycles of transistors T4 and T5 during the final portion of the integration phase. At the end of the integration phase, signals ST4 and ST5 are high, causing output VTGmem1 to be low; signals SK1 and SK2 are, for example, low, causing switches K1 and K2 to be in a non-conductive state; and signals SK3 and SK4 are, for example, high, causing switches K3 and K4 to be in a conductive state. Transistors T4 and T5 are alternately driven to activate and deactivate the transfer gate TGmem1.

[0109] When transitioning from the integration phase to the readout phase, Figure 6 At time t1, transistors T4 and T5 are independently driven into a non-conductive state by setting the gate voltage ST4 of transistor T4 to a high state and the gate voltage ST5 of transistor T5 to a low state. In other words, the power stage formed by transistors T4 and T5 must be set to a high-impedance state.

[0110] Then, at time t2 after time t1, signal SK4 goes low to sample the voltage across capacitor C1 equal to Vpixsub1.

[0111] Then, at time t3 after time t2, signal SK3 goes low to cause capacitor C1 to float.

[0112] Then, at time t4 after time t3, signals SK1 and SK2 go high successively or simultaneously, causing node N3 to be grounded (0V), and voltage VTGmem1 becomes approximately the negative of the voltage level delivered by voltage source 21. For example, if the voltage level delivered by voltage source 21 is approximately 300mV, then voltage VTGmem1 becomes approximately -300mV. The readout phase can then begin, during which transistors T4 and T5 remain off.

[0113] Between the integration and readout phases, the potential generated by voltage source 21 is sampled from capacitor C1 by turning off switch K4. During the readout phase, capacitor C1 maintains a negative potential VTGmemLO. For this purpose, the value of C1 is relatively high, for example, several μF depending on the size of the pixel array.

[0114] At the end of the readout phase, a new integration phase can be initiated by a sequence opposite to the sequence applied between times t1 and t4. Specifically, at time t5, signals SK1 and SK2 go low successively or simultaneously. Then, at time t6 after time t5, signal SK3 goes high. At time t7 after time t6, signal SK4 goes high. The integration phase begins at time t8 after time t7, and transistors T4 and T5 are driven alternately to activate and deactivate the transfer gate TGmem1.

[0115] Finite state machines are used, for example, to realize different potential, current, or voltage changes according to different phases via, for example, different electronic circuits involved.

[0116] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. Furthermore, although embodiments and variations in which each memory region is a pinned diode have been described, adapting these embodiments and variations to cases in which each memory region is a capacitive element, for example by modifying circuit 30, is within the capabilities of those skilled in the art.

[0117] Furthermore, the described embodiments and variations are not limited to combinations Figure 4 An example of circuit 30 described. Other output circuitry providing pixel 10 will be within the capabilities of those skilled in the art, for example, circuit 30, which includes a first component associated with memory region mem1 and coupled to the first line V via a transistor SF assembled as a source follower and a selection transistor TRS. X The first sensing node SN, and the second component associated with the memory region mem2, are coupled to the second line V via the transistor SF, assembled as a source follower, and the selection transistor TRS. X The second sensing node SN.

[0118] Finally, based on the functional indications given above, especially for capacitive applications of potential, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An image sensor, comprising: Pixel array inside and on top of the substrate; as well as The control circuit is configured as follows: During the first phase of pixel operation, a grounded first potential is applied to the substrate to read charge from the pixel; as well as During the second phase of pixel operation, a second potential higher than the first potential is applied to integrate the charge in the pixel. Each pixel includes: The first region is configured to generate charge in response to luminescence excitation; and At least two circuit components, each circuit component comprising: The second region is configured to store the charge generated by the first region; and A first transfer gate is configured to control the transfer of charge from the first region to the second region. The control circuitry is configured to control each transfer gate of each circuit component for each pixel: The first transfer gate is set to a conductive state by applying a third potential, and The first transfer gate is set to a non-conductive state by applying a fourth potential lower than the third potential. The second potential is controlled such that when the second potential is applied to the substrate and the fourth potential is applied to the first transfer gate, the first transfer gate is non-conductive, and the fourth potential is equal to or less than the potential of the substrate.

2. The image sensor of claim 1, wherein the control circuit is configured to reduce the fourth potential between the second stage and the first stage.

3. The image sensor according to claim 1, The charge integrated by the first region in the second stage is transferred and stored in at least one region of the second region; and The charge read in the first stage corresponds to the state of the charge stored in the second region.

4. The image sensor according to claim 1, wherein the image sensor is an indirect time-of-flight type.

5. An image sensor, comprising: Pixel array inside and on top of the substrate; as well as The control circuit is configured as follows: During the first phase of pixel operation, a grounded first potential is applied to the substrate to read charge from the pixel; as well as During the second phase of pixel operation, a second potential higher than the first potential is applied to integrate the charge in the pixel. Each pixel includes: The first region is configured to generate charge in response to luminescence excitation; and At least two circuit components, each circuit component comprising: The second region is configured to store the charge generated by the first region; and A first transfer gate is configured to control the transfer of charge from the first region to the second region. Each pixel includes a second circuit coupling the circuit assembly to at least one conductive line, the second circuit including a second transfer gate driven by the control circuit and configured to transfer charge stored at a level in the second region to the first node; and The control circuit is configured to reduce the value of the second potential between the second stage and the first stage by a fifth potential applied to the second transfer gate.

6. The image sensor according to claim 5, wherein the second circuit comprises: The first transistor has a drain coupled to the first node; The second transistor has a control gate coupled to the first node; as well as The third transistor is connected between the wire and the source of the second transistor; The control circuit is configured to operate between the second stage and the first stage: The sixth potential applied to the second transfer gate is reduced by the value of the second potential; as well as The seventh and eighth potentials used to control the first transistor are reduced by the value of the second potential.

7. An image sensor, comprising: Pixel array inside and on top of the substrate; as well as The control circuit is configured as follows: During the first phase of pixel operation, a grounded first potential is applied to the substrate to read charge from the pixel; as well as During the second phase of pixel operation, a second potential higher than the first potential is applied to integrate the charge in the pixel. Each pixel includes: The first region is configured to generate charge in response to luminescence excitation; and At least two circuit components, each circuit component comprising: The second region is configured to store the charge generated by the first region; and A first transfer gate is configured to control the transfer of charge from the first region to the second region. The control circuit includes: A fourth transistor, independent of the control of the fifth transistor; The drain of the fourth transistor is coupled to the drain of the fifth transistor at the second node; The source of the fourth transistor is also coupled to a power supply voltage rail. The source of the fifth transistor is also coupled to ground; A first switch connected between the second node and the fourth node; A second switch connected between the ground and the fourth node; A second capacitor element connected between the third node and the fourth node; A voltage source is configured to deliver the second potential; The voltage source is connected between the ground and the third switch, and the third switch is connected between the voltage source and the third node; and A fourth switch connected between the ground and the third node; The first transfer gate is coupled to the second node.

8. The image sensor of claim 7, wherein between the second stage and the first stage: The fourth transistor and the fifth transistor are driven such that the fourth transistor is in a non-conductive state and the fifth transistor is in a conductive state; Then the fourth transistor and the fifth transistor are independently driven to be in a non-conductive state; Then the third switch is set to a non-conductive state; Then the second switch is set to a non-conductive state; and Then, the first switch and the fourth switch are set to the conductive state.

9. The image sensor of claim 8, wherein the first stage and the second stage alternate in time, and wherein, Between the first phase and the second phase: The first switch and the fourth switch are set to a non-conductive state; Then the second switch is set to the conductive state; Then the third switch is set to the conductive state; as well as Then the fourth transistor and the fifth transistor are driven to conduct electricity alternately.

10. An image sensor, comprising: A pixel matrix in and on the substrate, each pixel including a first region and a memory region, the first region being configured to generate charge from photoexcitation, and the memory region being configured to store the charge generated by the first region; as well as The control circuit is configured as follows: During the first phase, a first potential grounded is applied to the substrate, and during the first phase, a control signal lower than a first voltage grounded is used to control the transistor to be turned off in order to transfer charge to the memory region; as well as During the second phase, a second potential higher than the first potential is applied, and during the second phase, a control signal at a second voltage grounded is used to control the transistor to turn off in order to transfer charge to the memory region; The second stage is an integration stage, during which the charge generated by the first region of each pixel is transferred and stored in the memory region of the pixel; as well as The first stage is a reading stage, during which the state of charge at a level stored in the memory region is read from the pixel.

11. The image sensor of claim 10, wherein each pixel comprises: At least two circuit components, each circuit component comprising: Memory area; and The transistor used for transferring charge is configured to control the transfer of charge from the first region and the memory region.

12. A method for controlling an image sensor, wherein the image sensor includes a pixel matrix in and on a substrate, each pixel including a first region and a memory region, the first region being configured to generate charge from photoexcitation, and the memory region being configured to store the charge generated by the first region, the method comprising: During the first phase, a first potential grounded is applied to the substrate, and during the first phase, a control signal lower than a first voltage grounded is used to control the transistor to be turned off in order to transfer charge to the memory region; as well as During the second phase, a second potential higher than the first potential is applied, and during the second phase, a control signal at a second voltage grounded is used to control the transistor to turn off in order to transfer charge to the memory region; The second stage is an integration stage, during which the charge generated by the first region of each pixel is transferred and stored in the memory region of the pixel; as well as The first stage is a reading stage, during which the state of the charge at a level stored in the memory region is read from the pixel.

Images