Method for forming an MRAM device and MRAM device

Abstract

The present invention relates to a method for forming an MRAM device and an MRAM device. In the forming method, an MTJ stack is formed above a lower metal layer on a semiconductor substrate, and an MTJ component is formed by a first etching, exposing a part of the bottom electrode layer or a part of the via hole below the MTJ stack. Then, through an oxidation treatment, the conductive redeposits on the sidewalls of the MTJ component and the exposed part of the bottom electrode layer or the part of the via hole around the MTJ component are oxidized. Subsequently, a second etching with an incident etching angle less than 45° is performed to remove the oxide layer formed on the sidewalls of the MTJ component. The smaller incident etching angle of the second etching facilitates the sufficient removal of the oxide layer on the sidewalls of the MTJ component and the sidewall damage part that may affect the performance of the MTJ component, ensuring the reliability of the MTJ component.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a method for forming an MRAM device and an MRAM device. Background Art

[0002] A magnetoresistive random access memory (hereinafter referred to as an MRAM device) is a new type of non-volatile memory, and its core component is a magnetic tunnel junction (hereinafter referred to as an MTJ component). The MTJ component mainly includes a stacked fixed layer, a tunneling barrier layer, and a free layer. Generally, the fixed layer has a fixed (or "pinned") magnetic orientation, and the free layer has a variable (or "free") magnetic orientation that can be switched between two or more different magnetic polarities. Due to the magnetic tunneling effect, the resistance of the MTJ component changes with the variable magnetic polarity. In operation, the spin transfer torque (STT) effect can be used to change or switch the magnetic polarity and achieve information storage.

[0003] When forming the MTJ component, generally, a stack for constructing the MTJ component is first formed above a metal layer formed on a semiconductor substrate, and then the stack is etched to form a plurality of discrete MTJ components. Some of the metal materials generated during the etching process will be deposited on the sidewalls of the MTJ component, which may cause the fixed layer and the free layer of the MTJ component to be connected across the tunneling barrier layer, resulting in short circuit points in the MRAM device. In order to avoid the short circuit problem caused by the metal materials redeposited on the sidewalls of the MTJ component, US Patent No. US11031548B2 discloses a method for reducing the mixing of materials on the sidewalls of the MTJ by oxidation. Among them, the metal materials redeposited on the sidewalls of the MTJ component are first oxidized, and then the sidewalls of the MTJ component are etched with an ion beam etch (IBE) at a relatively large incident etching angle (such as 50° to 90°) to remove the sidewall oxide layer of the MTJ component and the damaged part of the sidewall of the MTJ component.

[0004] However, in MRAM devices at advanced process nodes, the pitch between multiple laterally arranged MTJ components on a semiconductor substrate is small, and there is a shadow block when etching the sidewalls of the MTJ component at a relatively large incident etching angle, resulting in difficulty in completely removing the sidewall oxide layer and the damaged part of the sidewall of the MTJ component by the above method, which is not conducive to the reliability of the MTJ component. Summary of the Invention

[0005] In order to reduce the risk of short circuit points in the MRAM device and ensure the reliability of the MTJ component at the same time, the present invention provides a method for forming an MRAM device and an MRAM device.

[0006] On the one hand, the present invention provides a method for forming at least one MRAM device, the method comprising:

[0007] Forming a first dielectric layer above a lower metal layer on a semiconductor substrate;

[0008] Forming a via hole penetrating the first dielectric layer and a bottom electrode layer, the bottom electrode layer filling the via hole and covering the first dielectric layer, the bottom electrode layer being connected to the lower metal layer through the via hole;

[0009] Forming an MTJ stack on the bottom electrode layer;

[0010] Performing a first etching on the MTJ stack to form an MTJ component corresponding to the via hole and exposing a part of the bottom electrode layer around the MTJ component, wherein, through the first etching, conductive redeposits are formed on the sidewalls of the MTJ component;

[0011] Performing an oxidation treatment, by oxidizing the conductive redeposits, forming a sidewall oxide layer on the sidewalls of the MTJ component, and, by oxidizing the part of the bottom electrode layer exposed around the MTJ component, forming a bottom surface oxide layer around the MTJ component, the unoxidized bottom electrode layer located below the MTJ component and the bottom surface oxide layer constituting the bottom electrode; and

[0012] Performing a second etching to remove the sidewall oxide layer, the incident etching angle of the second etching being less than 45°.

[0013] On the other hand, the present invention provides an MRAM device formed by the above method, the MRAM device comprising:

[0014] A first dielectric layer formed above a lower metal layer on a semiconductor substrate;

[0015] A via hole penetrating the first dielectric layer;

[0016] A bottom electrode layer filling the via hole and covering the first dielectric layer, the bottom electrode layer being connected to the lower metal layer through the via hole;

[0017] An MTJ component formed on the bottom electrode layer;

[0018] A hard mask formed on the MTJ component;

[0019] A top electrode formed on the hard mask and connected to the MTJ component;

[0020] A coating material layer formed on the sidewalls of the MTJ component, the exposed surface of the bottom electrode layer, and the exposed surface of the first dielectric layer; and

[0021] A second dielectric layer is formed on the encapsulating material layer, and the second dielectric layer covers the MTJ component and fills the gap around the MTJ component.

[0022] In another aspect, the present invention provides a method for forming at least one MRAM device, the method comprising:

[0023] Forming a first dielectric layer above a lower metal layer on a semiconductor substrate and forming a via hole penetrating the first dielectric layer;

[0024] Forming an MTJ stack on the first dielectric layer;

[0025] Performing a first etching on the MTJ stack to form an MTJ component corresponding to a central region of the via hole and exposing a part of the via hole around the MTJ component, wherein, by the first etching, conductive redeposits are formed on sidewalls of the MTJ component;

[0026] Performing an oxidation treatment to form a sidewall oxide layer on sidewalls of the MTJ component by oxidizing the conductive redeposits, and forming a bottom surface oxide layer around the MTJ component by oxidizing a part of the via hole exposed around the MTJ component; and

[0027] Performing a second etching to remove the sidewall oxide layer, and an incident etching angle of the second etching is less than 45°.

[0028] In the method for forming an MRAM device provided by the present invention, after stacking an MTJ stack above a lower metal layer on a semiconductor substrate and forming an MTJ component by a first etching, a part of a bottom electrode layer or a part of the via hole below the MTJ stack is exposed, and then the conductive redeposits formed on sidewalls of the MTJ component and a part of the bottom electrode layer or a part of the via hole exposed around the MTJ component are oxidized by an oxidation treatment, and then a second etching with an incident etching angle less than 45° is performed to remove the oxide layer formed on sidewalls of the MTJ component. The incident etching angle of the second etching is small, which is convenient for fully removing the oxide layer on sidewalls of the MTJ component and damaged parts that may affect the performance of the MTJ component, ensuring the reliability of the MTJ component. In addition, since a part of the bottom electrode layer or a part of the via hole exposed around the MTJ component is oxidized, the etching products redeposited on sidewalls of the MTJ component by the second etching are not conductive, and the risk of short circuit points in the MRAM device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic flowchart of a method for forming an MRAM device according to an embodiment of the present invention.

[0030] Figures 2A to 2J is a cross-sectional schematic view of multiple steps of a method for forming an MRAM device according to an embodiment of the present invention.

[0031] Figures 3A to 3I is a cross-sectional schematic view of multiple steps of a method for forming an MRAM device according to another embodiment of the present invention. Detailed Description of the Invention

[0032] The magnetoresistive random access memory and the forming method thereof according to the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in the specification are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the spatially relative terms are intended to cover different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the drawings is inverted or positioned in other different ways (such as rotated), the exemplary term "on" may also include "under" and other orientation relationships. If the components in the drawings are the same as the components already labeled, although these components can be easily recognized in all the figures, for the sake of clearer description of the labels, the same components will not be labeled and described in all the drawings and the following text.

[0033] In an MRAM device, MTJ components can be formed between adjacent metal layers on a semiconductor substrate, and multiple MTJ components arranged horizontally can be formed between the adjacent metal layers. The distance between the multiple MTJ components is reduced at advanced process nodes. The aspect ratio of the MTJ component is related to the height of the MTJ component. In this case, due to the shadow block during ion beam etching, it is difficult to remove the oxide layer and the sidewall damage part formed on the sidewall of the MTJ component through a large incident etching angle (such as 50° - 90°, where the incident etching angle is defined as the angle between the incident direction of the ion beam and the normal direction of the semiconductor substrate). On the other hand, if the incident etching angle is reduced, the metal material exposed on the bottom surface of the gap between the multiple MTJ components will be etched too much, and the conductive etching products will redeposit on the sidewalls of the MTJ components, increasing the risk of short circuit points in the MRAM device.

[0034] In the method for forming at least one MRAM device according to an embodiment of the present invention, after etching the MTJ stack to form the MTJ component, a part of the bottom electrode layer or a part of the via hole located below the MTJ stack is exposed. Then, an oxidation treatment is first performed, which not only oxidizes the conductive redeposits on the sidewalls of the MTJ component, but also oxidizes the exposed part of the bottom electrode layer or the part of the via hole. Then, the sidewalls of the MTJ component are etched with a smaller incident etching angle (less than 45°). In this way, even if the gap around the MTJ component is narrow, the ion beam is convenient to enter, which is beneficial to removing the oxide layer and the damaged part of the sidewalls formed on the sidewalls of the MTJ component, and can still ensure the reliability of the MTJ component at advanced process nodes. In addition, the oxidation treatment oxidizes a part of the bottom electrode layer or a part of the via hole around the MTJ component, and there is basically no exposed metal material around the MTJ component. After the second etching at a smaller angle, the etching products redeposited on the sidewalls of the MTJ component are mainly insulating materials, reducing the risk of short-circuit points in the MRAM device.

[0035] Figure 1 It is a schematic flow chart of a method for forming an MRAM device according to an embodiment of the present invention. Figures 2A to 2J It is a cross-sectional schematic diagram of multiple steps of a method for forming an MRAM device according to an embodiment of the present invention. The following refers to Figure 1 and Figures 2A to 2J to describe the method for forming an MRAM device according to an embodiment. The MRAM device is, for example, sandwiched between two adjacent metal layers on a semiconductor substrate. In the following embodiments, the two adjacent metal layers are respectively referred to as the lower metal layer and the upper metal layer.

[0036] As Figure 2A shown, first, a first dielectric layer 10, a via hole 11 penetrating the first dielectric layer 10, and a bottom electrode layer 12 are formed above the lower metal layer M on a semiconductor substrate (not shown). The bottom electrode layer 12 fills the via hole 11 and covers the first dielectric layer 10. The bottom electrode layer 12 is connected to the lower metal layer M through the via hole 11. x x connected.

[0037] The lower metal layer M xIt can be a metal interconnect layer above the semiconductor substrate, so it is represented by the subscript x. The first dielectric layer 10 can be made of, for example, undoped silicate glass or oxide (such as silicon oxide) or other suitable materials. The size of the via 11 can be determined according to the design of the MRAM device. Here, the via 11 is, for example, a small-aperture via. To prevent the metal material in the via 11 from being exposed and etched in the subsequent second etching process, the aperture of the via 11 is, for example, smaller than the lateral dimension of the MTJ component or the bottom electrode to be formed on the via 11. The bottom electrode layer 12 can include one or a combination of two or more of titanium nitride, tantalum nitride, titanium, tantalum, and aluminum.

[0038] As Figure 2B shown, then, an MTJ stack 13 is stacked on the first dielectric layer 10. The MTJ stack 13 is used to form an MTJ component, which includes the functional layers of the MTJ component. Exemplarily, the MTJ stack 13 includes a seed layer 131 (Seed layer, SL), a pinned layer 132 (Pin Layer, PL), a tunneling barrier layer 133, a free layer 134 (Free Layer, FL), and a capping layer 135 (Cap). Each functional layer can be made of known materials. For example, the tunneling barrier layer 133 is made of magnesium oxide (MgO). After stacking the MTJ stack 13, a hard mask layer 14 (HM) can further be deposited on the MTJ stack 13. The hard mask layer 14 is, for example, made of a metal material.

[0039] As Figure 2C shown, then, through a photolithography process and an etching process (such as reactive ion etching (RIE)), the hard mask layer 14 is patterned to define the range of the MTJ component. Here, the patterned hard mask layer 14 can be used as the top electrode connected to the MTJ component in the MRAM device. In another embodiment, a top electrode can also be formed on the hard mask layer 14, and the top electrode is connected to the MTJ component.

[0040] As Figure 2DAs shown, then, using the patterned hard mask layer 14 as a mask, a first etching (which may include appropriate over-etching) is performed to remove part of the MTJ stack 13, and MTJ components 13a are formed corresponding to the vias 11. Through this first etching, a part of the bottom electrode layer 12 outside the coverage of the MTJ components 13a is exposed. The first etching can be performed by reactive ion etching (RIE) or ion beam etching (IBE). Since ion beam etching introduces less chemical gas, ion beam etching is preferably used. The incident etching angle of this first etching is, for example, less than 30°, for example, vertical etching (i.e., the incident etching angle is equal to 0°). Thus, the sidewalls of the MTJ components 13a are perpendicular or nearly perpendicular to the main surface of the semiconductor substrate. The first etching can remove a part of the thickness of the bottom electrode layer 12. During the etching process, part of the metal material removed from the MTJ stack 13 and the bottom electrode layer 12 and some other etching products will be deposited on the sidewalls of the MTJ components 13a and the hard mask layer 14 to form redeposition. Conductive redeposits 15 are formed on the sidewalls of the MTJ components 13a, and there are also damages on the sidewalls of the MTJ components 13a caused by the first etching. The conductive redeposits 15 and the damaged parts of the sidewalls of the MTJ components 13a need to be removed, otherwise, short circuits and reliability problems as described in the background art are likely to occur.

[0041] Optionally, a plurality of vias 11 are formed in the first dielectric layer 10 on the lower metal layer M x . After the first etching, a plurality of MTJ components 13a can be formed corresponding to each of the vias 11 respectively. Part of the bottom electrode layer 12 around each MTJ component 13a is exposed in the gaps between the plurality of MTJ components 13a. To avoid excessive etching of the first dielectric layer 10 during the subsequent second etching process and affect the overall process on the semiconductor substrate, after the first etching is completed, the bottom electrode layer 12 between the plurality of MTJ components 13a remains in a state where it is not etched through. Referring to Figure 2D , after this first etching, in the part of the bottom electrode layer 12 exposed around the MTJ components 13a, the part of the bottom electrode layer 12 farther from the corresponding MTJ component 13a has a relatively thinner thickness, and this relatively thinner part of the bottom electrode layer 12 surrounds the corresponding MTJ component 13a. Exemplarily, the thickness (i.e., the minimum thickness) of the thinnest region of the bottom electrode layer 12 is less than or equal to 10 nm, and more specifically, for example, about 5 nm.

[0042] Such as Figure 2EAs shown, then, an oxidation treatment is performed, for example, oxygen (O2), ozone (O3), an inert gas or plasma containing oxygen (O2) or ozone (O3) is used to heat or non-heat the semiconductor substrate after the above-mentioned first etching, so that the conductive redeposition 15 located on the side wall of the MTJ component 13a and the magnetic material exposed to the oxidizing atmosphere on the side wall of the MTJ component 13a are oxidized, and a side wall oxide layer 16 is formed on the side wall of the MTJ component 13a. The oxidation treatment can also be completed during the above-mentioned first etching process. The oxidation treatment also causes the bottom electrode layer 12 exposed around the MTJ component 13a to be oxidized from the surface to a partial depth inside, and a bottom surface oxide layer 17 is formed around the MTJ component 13a. In this embodiment, through the oxidation treatment, at least the bottom electrode layer 12 in the thinner area of ​​the bottom electrode layer 13a exposed around the MTJ component 13a is completely oxidized, so that the connection of the bottom electrode layer 13a between adjacent MTJ components 13a is blocked. The exposed thicker area of ​​the bottom electrode layer 13a may not be completely oxidized, but only the surface layer may be oxidized. After the oxidation treatment, the unoxidized bottom electrode layer 12 is located below the MTJ component 13a and the bottom oxide layer 17, and this part of the bottom electrode layer 12 constitutes the bottom electrode 12a corresponding to the MTJ component 13a.

[0043] like Figure 2F As shown, a second etching is then performed to remove the sidewall oxide layer 16, and the incident etching angle of the second etching is less than 45°. The second etching is, for example, ion beam etching (IBE). The incident etching angle of the second etching is small, so that the ion beam can easily irradiate the gap around the MTJ component 13a, avoiding shadow blocking, and can be applied to MRAM device processes of different process nodes.

[0044] Optionally, the second etching has a larger incident etching angle than the first etching to facilitate etching the side wall of the MTJ component 13a. In addition, the etching power of the second etching can be smaller than the etching power of the first etching to avoid damaging the MTJ component 13a. After the second etching, the side wall oxide layer 16 located on the side wall of the MTJ component 13a is basically removed, and the damaged part of the side wall of the MTJ component 13a can also be removed, which can improve the reliability of the MTJ component 13a.

[0045] In this embodiment, the second etching will simultaneously etch the bottom oxide layer 17 around the MTJ component 13a, such that at least a part of the bottom oxide layer 17 is removed. For example, the bottom oxide layer 17 in some areas can be etched through to expose the first dielectric layer 10. During this process, at least a part of the etching products formed by etching the bottom oxide layer 17 may be deposited on the sidewalls of the MTJ component 13a to form a re-deposited oxide 17a. Since the bottom oxide layer 17 is an insulating material, the re-deposition caused by etching the bottom oxide layer 17 will not increase the risk of forming a short circuit point in the MRAM device. After this second etching, a relatively thin residue of the bottom oxide layer 17 (e.g., less than 5 nm) can be retained around the MTJ component 13a.

[0046] As Figure 2G shown, optionally, after completing the second etching, an additional etching, i.e., the third etching, can be performed. The incident etching angle of the third etching is, for example, greater than the incident etching angle of the second etching. The incident etching angle of the third etching can be greater than 45° to remove the re-deposited oxide 17a formed on the sidewalls of the MTJ component 13a after the second etching. The etching power of the third etching can be less than or equal to the etching power of the second etching. During the third etching process, the remaining bottom oxide layer 17 around the MTJ component 13a is etched, and a small amount of deposition is formed on the sidewalls of the MTJ component 13a. Since the bottom oxide layer 17 is an insulating material, it will not increase the risk of forming a short circuit point in the MRAM device. After the third etching, the coverage of the bottom electrode 12a below the MTJ component 13a is reduced, which can ensure the reliability of the interlayer dielectric (ILD) subsequently filled in the gaps between the MTJ components 13a.

[0047] Next, a coating process can be performed on the above MTJ component 13a. As Figure 2H shown, first, a coating material layer 18 is conformally formed on the top surface of the semiconductor substrate after completing the second etching (or completing the third etching). The coating material layer 18 can be made of, such as, SiN x , SiON, SiO x , SiC, SiCN or other suitable materials. Then, a second dielectric layer 19 is formed on the coating material layer 18. The second dielectric layer 19 covers the MTJ component 13a and fills the gaps around the MTJ component 13a. After that, the top surface of the second dielectric layer 19 is planarized (such as chemical mechanical polishing, CMP).

[0048] As Figure 2IAs shown, then, using a photolithography process and an etching process, an opening 19a exposing the top electrode is formed on the surface of the second dielectric layer 19. Here, the hard mask layer 14 serves as the top electrode. The width of the opening 19a may be greater than the width of the MTJ component 13a. The encapsulating material layer 18 may also be exposed by the opening 19a, and the exposed surface of the encapsulating material layer 18 is substantially flush with the exposed surface of the top electrode.

[0049] As Figure 2J shown, then, a metal material is deposited in the opening 19a and on the top surface of the second dielectric layer 19, and a planarization process is performed to remove the excess metal material, leaving the metal material within the opening 19a. The metal material within the opening 19a is the upper metal layer M x+1 , and the upper metal layer M x+1 can serve as the upper contact end of the MTJ component 13a.

[0050] Figures 3A to 3I is a cross-sectional schematic diagram of multiple steps of a method for forming an MRAM device according to another embodiment of the present invention. The following will refer to Figures 3A to 3I to describe the method for forming an MRAM device in this another embodiment. In the following, components or processes that are substantially the same as those in the above embodiment will not be described repeatedly.

[0051] As Figure 3A shown, first, a first dielectric layer 20 and a via hole 21 penetrating the first dielectric layer 20 are formed above a lower metal layer M x on a semiconductor substrate (not shown). In this embodiment, the aperture of the via hole 21 is larger than the lateral dimension of the MTJ component to be formed above it. The via hole 21 includes, for example, tantalum nitride (TaN) filled in the through hole. The MTJ component to be formed is formed corresponding to the central region of the via hole 21 and is in electrical contact with the via hole 21.

[0052] As Figure 3B shown, then, an MTJ stack 22 is stacked on the first dielectric layer 20. The MTJ stack 22 is used to form an MTJ component and includes each functional layer of the MTJ component. In another embodiment, the MTJ stack 22 may include a bottom electrode layer located between the seed layer 221 and the first dielectric layer 20. After stacking the MTJ stack 22, a hard mask layer 23 (HM) may further be deposited on the MTJ stack 22.

[0053] As Figure 3C shown, then, the hard mask layer 23 is patterned through a photolithography process and an etching process (such as reactive ion etching (RIE)) to define the range of the MTJ component. As Figure 3DAs shown, then, using the patterned hard mask layer 23 as a mask, a first etching (which may include appropriate over-etching) is performed. Specifically, each layer of the MTJ stack 22 and the bottom electrode layer selectively formed between the MTJ stack 22 and the first dielectric layer 21 are etched layer by layer to remove a part of the MTJ stack 22 and form an MTJ component 22a corresponding to the central region of the via 21, and other regions of the via 21 are not covered by the MTJ component 22a and thus are exposed. This first etching can be carried out by reactive ion etching or ion beam etching, for example, ion beam etching here. The incident etching angle of the first etching is, for example, less than 30°, for example, vertical etching (i.e., the incident etching angle is equal to 0°), and the sidewall of the formed MTJ component 22a is perpendicular or nearly perpendicular to the main surface of the semiconductor substrate. After the first etching, conductive redeposits 24 are formed on the sidewalls of the MTJ component 22a.

[0054] As Figure 3E shown, then an oxidation treatment is carried out. For example, the semiconductor substrate after the above first etching is heated or non-heated using oxygen, ozone, an inert gas containing oxygen or ozone, or a plasma, so that the conductive redeposits 24 on the sidewalls of the MTJ component 22a and the magnetic materials on the sidewalls of the MTJ component 22a exposed to the oxidation atmosphere are oxidized, and a sidewall oxide layer 25 is formed on the sidewalls of the MTJ component 22a. The oxidation treatment can also be completed during the above first etching process. The oxidation treatment also causes the exposed via 21 to be oxidized from the surface to a certain depth inside, and a bottom surface oxide layer 26 (with a thickness of about 5 nm to 10 nm) is formed around the MTJ component 22a. Since the exposed part of the via 21 is oxidized, there is no exposed metal material around the MTJ component 22a.

[0055] As Figure 3F shown, then a second etching is carried out to remove the sidewall oxide layer 25, and the incident etching angle of the second etching is less than 45°. This second etching uses, for example, ion beam etching. The incident etching angle of the second etching is small, so that the ion beam can easily enter the gap around the MTJ component 22a and irradiate the sidewalls of the MTJ component 22a, avoiding shadow blocking, and can be applied to the formation of MRAM devices at different process nodes. Optionally, the incident etching angle of the second etching is larger than that of the above first etching to facilitate etching the sidewalls of the MTJ component 22a. In addition, the etching power of the second etching can be less than that of the above first etching to reduce the risk of damage to the MTJ component 22a.

[0056] After the second etching, the sidewall oxide layer 25 is basically removed, and the damaged part on the sidewall of the MTJ component 22a can also be removed, which can improve the reliability of the MTJ component 22a. In this embodiment, the second etching etches the bottom oxide layer 26 around the MTJ component 22a, so that at least part of the thickness of the bottom oxide layer 26 is removed. During this process, the etching products generated by etching the bottom oxide layer 26 may be deposited on the sidewall of the MTJ component 22a to form a redeposited oxide 26a. Since the bottom oxide layer 26 is an insulating material, the redeposition caused by etching the bottom oxide layer 26 does not increase the risk of forming a short circuit point in the MRAM device. After the second etching, a part of the bottom oxide layer 26 (with a thickness of about 5 nm, for example) may remain around the MTJ component 22a, and this part of the bottom oxide layer 26 covers the bottom of the MTJ component 22a in the form of a sidewall.

[0057] Optionally, after completing the second etching, the incident etching angle can be increased to perform a third etching. The incident etching angle of the third etching is, for example, greater than 45° to remove the redeposited oxide 26a formed on the sidewall of the MTJ component 22a after the second etching. The etching power of the third etching can be less than or equal to the etching power of the second etching.

[0058] Next, a coating process can be performed on the MTJ component 22a. As Figure 3G shown, first, a coating material layer 27 is conformally formed on the top surface of the semiconductor substrate after completing the second etching (or completing the third etching), and then a second dielectric layer 28 is formed on the coating material layer 27, so that the second dielectric layer 28 covers the MTJ component 22a and fills the gap around the MTJ component 22a. After that, the upper surface of the second dielectric layer 28 is planarized (such as chemical mechanical polishing, CMP).

[0059] As Figure 3H shown, then, using a photolithography process and an etching process, an opening 28a exposing the top electrode is formed on the top surface of the second dielectric layer 28. Here, the hard mask layer 23 is used as the top electrode of the MTJ component 22a. The width of the opening 28a can be greater than the width of the MTJ component 22a. The coating material layer 27 can also be exposed by the opening 28a, and the exposed surface of the coating material layer 27 is substantially flush with the exposed surface of the top electrode.

[0060] As Figure 3I shown, then, a metal material is deposited in the opening 28a and on the top surface of the second dielectric layer 28, and a planarization process is performed to remove the excess metal material, leaving the metal material in the opening 28a. The metal material in the opening 28a is the upper metal layer M x+1 and the upper metal layer M x+1 can be used as the upper contact end of the MTJ component 22a.

[0061] An embodiment of the present invention provides a method for forming at least one MRAM device. Among them, a MTJ stack is stacked above a lower metal layer M on a semiconductor substrate. After forming a MTJ component by a first etching, a part of the bottom electrode layer 12 or a part of the via 21 below the MTJ stack is exposed. Then, through an oxidation treatment, the conductive re-deposits on the sidewalls of the MTJ component and the exposed part of the bottom electrode layer or the via around the MTJ component are oxidized. Then, a second etching with an incident etching angle less than 45° is performed to remove the oxide layer on the sidewalls of the MTJ component. The incident etching angle of the second etching is small, and the influence of shadow blocking is small, which is convenient for fully removing the oxide layer on the sidewalls of the MTJ component and the sidewall damage part that may affect the performance of the MTJ component, ensuring the reliability of the MTJ component. In addition, since the periphery of the MTJ component is the oxide of the bottom electrode layer or the via, the etching products of the second etching deposited on the sidewalls of the MTJ component are not conductive, which can reduce the risk of short-circuit points in the MRAM device. x It should be noted that the various embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same and similar parts among the various embodiments can be understood by referring to each other.

[0062] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments according to the technical essence of the present invention without departing from the technical solutions of the present invention all belong to the protection scope of the technical solutions of the present invention.

[0063] ​

Claims

1. A method of forming at least one MRAM device, characterized in that, The method includes: forming a first dielectric layer over a lower metal layer on a semiconductor substrate; forming a via hole penetrating the first dielectric layer and a bottom electrode layer, the bottom electrode layer filling the via hole and covering the first dielectric layer, the bottom electrode layer being connected to the lower metal layer through the via hole; forming an MTJ stack on the bottom electrode layer; performing a first etching on the MTJ stack to form MTJ components corresponding to the via holes and exposing a part of the bottom electrode layer around the MTJ components, wherein, through the first etching, conductive redeposits are formed on sidewalls of the MTJ components; performing an oxidation treatment, by oxidizing the conductive redeposits, forming sidewall oxide layers on sidewalls of the MTJ components, and, by oxidizing the part of the bottom electrode layer exposed around the MTJ components, forming bottom surface oxide layers around the MTJ components, and the unoxidized bottom electrode layer located below the MTJ components and the bottom surface oxide layers constitutes a bottom electrode; and performing a second etching to remove the sidewall oxide layers, the incident etching angle of the second etching being less than 45°.

2. The method according to claim 1, wherein After completing the second etching, the method includes: performing a third etching to remove etching products redeposited on sidewalls of the MTJ components through the second etching, the incident etching angle of the third etching being greater than the incident etching angle of the second etching.

3. The method according to claim 1, characterized in that After completing the second etching, the method includes: forming a cladding material layer along a top surface of the semiconductor substrate after completing the second etching; forming a second dielectric layer on the cladding material layer, the second dielectric layer covering the MTJ components and filling gaps around the MTJ components; performing a planarization treatment on a top surface of the second dielectric layer; forming an opening in the second dielectric layer, the opening exposing a top electrode formed above and connected to the MTJ components; and forming an upper metal layer in the opening.

4. The method according to claim 1, characterized in that, A plurality of the via holes are formed in the first dielectric layer; through the first etching, a plurality of the MTJ components are formed corresponding to the plurality of the via holes, and a part of the bottom electrode layer is exposed in a gap between the plurality of the MTJ components; through the oxidation treatment, a metal material exposed in a gap between the plurality of the MTJ components is oxidized.

5. The method according to claim 1, wherein Before performing the oxidation treatment, a minimum thickness of the bottom electrode layer is less than or equal to 10 nm.

6. The method according to claim 1, wherein A pore diameter of the via hole is less than a lateral dimension of the bottom electrode.

7. An MRAM device formed by the method as described in claim 1, characterized in that, The MRAM device includes: a first dielectric layer formed over a lower metal layer on a semiconductor substrate; a via hole penetrating the first dielectric layer; a bottom electrode layer filling the via hole and covering the first dielectric layer, the bottom electrode layer being connected to the lower metal layer through the via hole; an MTJ component formed on the bottom electrode layer; a hard mask formed on the MTJ component; a top electrode formed on the hard mask and connected to the MTJ component; a cladding material layer formed on sidewalls of the MTJ components, an exposed surface of the bottom electrode layer, and an exposed surface of the first dielectric layer; and A second dielectric layer is formed on the encapsulation material layer, and the second dielectric layer covers the MTJ component and fills the gap around the MTJ component.

8. A method of forming at least one MRAM device, characterized in that, The method includes: forming a first dielectric layer above a lower metal layer on a semiconductor substrate and forming a via hole penetrating the first dielectric layer; forming an MTJ stack on the first dielectric layer; performing a first etching on the MTJ stack to form an MTJ component corresponding to a central region of the via hole and exposing a part of the via hole around the MTJ component, wherein, through the first etching, conductive redeposits are formed on sidewalls of the MTJ component; performing an oxidation process, forming a sidewall oxide layer on sidewalls of the MTJ component by oxidizing the conductive redeposits, and forming a bottom surface oxide layer located around the MTJ component by oxidizing a part of the via hole exposed around the MTJ component; and performing a second etching to remove the sidewall oxide layer, and an incident etching angle of the second etching is less than 45°.

9. The method according to claim 8, characterized in that, After completion of the second etching, the method includes: performing a third etching to remove etching products redeposited on sidewalls of the MTJ component through the second etching, and an incident etching angle of the third etching is greater than the incident etching angle of the second etching.

10. The method according to claim 8, wherein After completion of the second etching, the forming method includes: forming an encapsulation material layer along a top surface of the semiconductor substrate after completion of the second etching; forming a second dielectric layer on the encapsulation material layer, and the second dielectric layer covers the MTJ component and fills the gap around the MTJ component; performing a planarization process on a top surface of the second dielectric layer; forming an opening in the second dielectric layer, and the opening exposes a top electrode formed above and connected to the MTJ component; and forming an upper metal layer in the opening.

11. The method according to claim 8, wherein A plurality of the via holes are formed in the first dielectric layer; through the first etching, a plurality of the MTJ components are formed corresponding to the plurality of the via holes, and a part of each of the via holes is exposed in a gap between the plurality of the MTJ components; through the oxidation process, a metal material exposed in the gap between the plurality of the MTJ components is oxidized.

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