Design of scanning electron microscope image anchored array

Abstract

A scanning electron microscope receives a results file for a wafer from an optical inspection system. The results file includes anchor points on the wafer. A defect review image at the anchor points on the wafer is generated using the scanning electron microscope. A design fragment is aligned to the defect review image at the anchor points, resulting in an aligned defect review image. Defect detection is performed using the aligned defect review image.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to provisional patent application U.S. Application No. 63 / 067,824, filed August 19, 2020, the disclosure of which is hereby incorporated by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to semiconductor defect inspection. BACKGROUND

[0004] Evolution of the semiconductor manufacturing industry places increasingly stringent requirements on yield management and, in particular, metrology and inspection systems. Critical dimensions continue to shrink, but the industry needs to reduce the time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to resolving the problem determines the return on investment for semiconductor manufacturers.

[0005] Manufacturing semiconductor devices, such as logic and memory devices, typically includes processing semiconductor wafers using a large number of manufacturing processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor manufacturing process that involves transferring a pattern from a photomask to a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices can be manufactured in an arrangement on a single semiconductor wafer, which are then separated into individual semiconductor devices.

[0006] Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits (ICs). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause device failure. For example, as the dimensions of semiconductor devices decrease, the detection of defects of decreasing size has become necessary because even relatively smaller defects can cause undesirable variations in the semiconductor devices.

[0007] However, as design rules shrink, semiconductor manufacturing processes can operate closer to the performance limits of the process. Additionally, as design rules shrink, even smaller defects can affect the electrical parameters of the device, driving more sensitive inspection. With shrinking design rules, the population of potential yield-related defects detected by inspection increases significantly, as does the population of disruptive point defects detected by inspection. Therefore, more defects can be detected on the wafer, and correcting the process to eliminate all defects can be difficult and expensive. Determining which defects actually affect the device's electrical parameters and yield allows process control methods to focus on those defects while largely ignoring others. Furthermore, under smaller design rules, process-induced failures tend to be systematic in some cases. That is, process-induced failures tend to occur at predetermined design patterns that are typically repeated many times within the design. Eliminating spatially systematic, electrically related defects can impact yield.

[0008] Scanning electron microscope (SEM) tools often fail to align an image to the design at the target location due to repeating patterns (i.e., cells) within the array region. Alignment often locks onto an incorrect repeating pattern, leading to reports of defective, incorrect coordinates. The cell size needs to be larger than the combined uncertainty in the optical inspection system (e.g., a broadband plasma (BBP) tool) and the stage in the SEM. For example, the cell size may need to be larger than (250 nm + 125 nm) x 2 = 750 nm for successful alignment at the target location. In this example, 250 nm is for the SEM and 125 nm is for the optical inspection system, but those values ​​can vary depending on the specific system. This value is multiplied by 2 because the cell size takes into account whether the value can be in a positive or negative direction. Typically, the cell size is smaller than this uncertainty.

[0009] Current technology relies on semiconductor manufacturers to provide design anchor locations. SEM tools obtain a list of design anchor locations from the semiconductor manufacturer and, for each defect target, find the nearest anchor location. They move the stage to the anchor location, capture the image and design, perform alignment to the design, and then move to the target location adjusted by alignment corrections found at the anchor point. However, SEM tools lack an automated method for analyzing the design to determine anchor locations. Semiconductor manufacturers may not provide anchor locations for all layers in the semiconductor device. The anchor locations provided by the semiconductor manufacturer may also differ from the design layers used to inspect the target location.

[0010] Therefore, there is a need for improved systems and technologies for semiconductor defect inspection. Summary of the Invention

[0011] In a first embodiment, a method is provided. The method includes receiving a result file of a wafer from an optical inspection system at a scanning electron microscope (SEM). The result file contains anchor points on the wafer. A defect inspection image is generated at the anchor points on the wafer using the SEM. A design fragment is aligned to the defect inspection image at the anchor points, thereby generating an aligned defect inspection image. Defects are detected in the aligned defect inspection image.

[0012] The method may include determining the anchor point using the optical inspection system. The optical inspection system may generate pixel-pair design alignment image patches and select the anchor point from the pixel-pair design alignment image patches. A generative adversarial network (GAN) may be used to select the anchor point from the pixel-pair design alignment image patches. Determining the anchor point may include ranking the pixel-pair design alignment image patches and selecting one of the pixel-pair design alignment image patches as the anchor point.

[0013] The design segment can be a 1mm by 1mm area on the bare die of the wafer.

[0014] The method may include using targets on the defect inspection image to perform fine alignment of the defect inspection image.

[0015] The aligned defect inspection image may have a positional uncertainty of ±25 nm.

[0016] The detection can occur during array mode.

[0017] In a second embodiment, a system is provided. The system includes: a SEM tool comprising a stage configured to hold a wafer; an electron beam source configured to emit electrons toward the wafer; and a detector configured to detect electrons received from the wafer. The system further includes a processor communicating with the SEM, the processor being configured to receive a result file for the wafer from an optical inspection system. The result file includes anchor points on the wafer. The processor is further configured to: generate a defect inspection image at the anchor points on the wafer; align a design fragment to the defect inspection image at the anchor points, thereby generating an aligned defect inspection image; and detect defects in the aligned defect inspection image.

[0018] The system may include the optical inspection system. The optical inspection system may be configured to generate pixel-pair design alignment image blocks and select the anchor points from the pixel-pair design alignment image blocks.

[0019] The system may include a GAN unit configured to select the anchor point from the pixel-pair design aligned image block.

[0020] The design segment can be a 1mm by 1mm area on the bare die of the wafer.

[0021] The processor may be further configured to perform fine alignment of the defect inspection image using targets on the defect inspection image.

[0022] The aligned defect inspection image may have a positional uncertainty of ±25 nm.

[0023] In a third embodiment, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium contains one or more programs configured to perform the following steps on one or more processors. The steps include receiving a result file for a wafer from an optical inspection system. The result file contains anchor points on the wafer. The steps further include: generating a defect inspection image at the anchor points on the wafer; aligning a design fragment to the defect inspection image at the anchor points to generate an aligned defect inspection image; and detecting defects in the aligned defect inspection image.

[0024] The optical inspection system can be configured to generate pixel-pair design alignment image blocks, and the anchor point can be selected from the pixel-pair design alignment image blocks.

[0025] The anchor point can be selected from the pixel pair design alignment image block using GAN.

[0026] The anchor point can be received from the optical inspection system via a result file using SEM.

[0027] The one or more programs may be further configured to perform fine alignment of the defect inspection image using targets on the defect inspection image.

[0028] The aligned defect inspection image may have a positional uncertainty of ±25 nm. Attached Figure Description

[0029] For a more complete understanding of the nature and purpose of this disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 It is a flowchart of the method according to this disclosure; and

[0031] Figure 2 It is a block diagram of the system according to this disclosure. Detailed Implementation

[0032] Although the claimed subject matter will be described with reference to specific embodiments, other embodiments (including those not providing all the advantages and features set forth herein) are also within the scope of this disclosure. Various structural, logical, process, and electronic changes can be made without departing from the scope of this disclosure. Therefore, the scope of this disclosure is defined only by reference to the appended claims.

[0033] Using the embodiments disclosed herein, an SEM image is aligned to the design at a location near the target, and then the stage is moved to the target location for defect detection. Pixel-to-Design Alignment (PDA) of the target can be reused to obtain the anchoring positions of all array targets. If the anchoring point is 1 mm to 2 mm from the target location, then the stage inaccuracy of ±125 nm can be reduced to approximately ±25 nm.

[0034] Figure 1 This is a flowchart of method 100. In 101, the SEM tool receives the wafer's result file from an optical inspection system (e.g., a BBP inspection system). The result file contains anchor points on the wafer. In this example, the result file is a KLARF file used by KLA Corporation, which may contain defect locations, features extracted from images taken at those locations, image patches, defect classifications, or other information.

[0035] Each (array) defect location can have an anchor location added to the results file. These defect locations can be added as new defect locations, but each defect location can have its own coarse bin code to identify it as an anchor point. While disclosed for arrays, the anchor locations can be used in stochastic designs where sparse geometry around the defect location renders alignment at the defect site ineffective.

[0036] Anchor points can be determined using an optical inspection system. For example, an optical inspection system can generate pixel-to-design aligned image blocks. The optical inspection system can perform pixel-to-design alignment and save the image blocks and design fragments.

[0037] Anchor points are selected from pixel-to-design aligned image patches. In this example, a GAN is used to select anchor points from pixel-to-design aligned image patches. Determining anchor points may involve ranking the pixel-to-design aligned image patches and selecting one of them as the anchor point. The GAN can be trained on samples of representative patterns using design fragments and corresponding optical and SEM images. Ranking can be based on the alignment quality and uniqueness metrics of the image patches. The better alignment quality and uniqueness can be selected.

[0038] Therefore, the optical inspection system can present a design fragment at each pixel pair at the design location or sub-selected location. The optical inspection system can determine whether the location is suitable for SEM alignment, which can be analogous to ranking based on image quality and uniqueness metrics. If a trained GAN network is available for this layer, SEM look-alike images can be generated for further analysis of alignment suitability. A GAN can be used with the design file as input to generate SEM look-alike images.

[0039] In this example, the optical inspection system can perform a process, which can be an offline process, that renders one or more design fragments as black and white images at the SEM image scale (e.g., 2nm pixel size). The optical inspection system can determine whether a location is a suitable alignment target. Aspects of the rendered images (e.g., pattern repetition, image contrast, noise, or other factors) can be considered to determine whether a location is suitable for SEM alignment. A fit matrix for each target can be generated. The Graphical Design System (GDS) location of the selected target can be saved as part of the recipe for the optical inspection tool. GDS is a format that can be used to store semiconductor device designs.

[0040] In this example, a target is selected for each 1μm x 1μm grid. For a 30mm x 30mm die, this results in 900 GDS locations. A GAN or design rendering can be used to perform sub-selection of GDS locations. Pixel-pair design alignment locations can be stored. During runtime, the pixel-pair design alignment location closest to each defect can be added to the location to capture inspection images.

[0041] The optical inspection system can also add anchor points to the results file.

[0042] Once alignment correction is found at the anchor point, the optical inspection system can adjust the target position within the target image frame. Based on the alignment correction, offsets may exist in the X and Y directions.

[0043] Optical inspection systems can also apply location filters to reduce obfuscation points. Accurate defect coordinates can be used to apply design-defined areas of interest. Location filters can be applied to areas of interest that can be defined in the GDS to avoid specific structures.

[0044] At 102, SEM is used to generate defect inspection images at anchor points on the wafer.

[0045] In step 103, a GAN is used to align the design fragment to the defect inspection image at the anchor point. This produces an aligned defect inspection image. For example, the design fragment could be a 1mm x 1mm area on a bare die on the wafer, and could be the size of the inspection image. Of course, the design fragment can be other sizes. Fine alignment of the defect inspection image can be performed using targets on the defect inspection image. Coarse alignment can be performed on the anchor position image, which may not be in a repeating area. Fine alignment can be performed on the defect position image, and may not be aligned to adjacent cells. For example, the design fragment in the input is used to generate a SEM similarity image for alignment.

[0046] In this example, the stage holding the wafer can be moved to a target position for defect detection.

[0047] The aligned defect inspection image may have a positional uncertainty of ±25 nm. This is due to the expected accuracy considering the residual error of the alignment. Accurate defect localization is important for obtaining accurate defect classification based on high-resolution SEM images, ensuring that the correct pixels from the SEM image are used in the classification. Different positional uncertainties can be provided, which can be used in combination with specific applications. A positional uncertainty of ±25 nm provides an improvement over existing systems.

[0048] In step 104, defects are detected in the aligned defect inspection image. This allows for coordinate correction of the defect locations found in the inspection image. Accurate coverage of defects found in SEM inspection and BBP optical images can be provided. The resolution of the SEM tool can be used to classify defects. For example, defect detection can occur during array mode defect detection. Coarse alignment of the SEM can be performed at the nearest anchor point. Fine alignment can be performed at the target location. This is helpful when two defects exist in a single field of view, as incorrect defects can be classified or a search can be performed at incorrect locations without alignment.

[0049] SEM images from all result file locations can be collected into the optical inspection system workstation.

[0050] The fusion of optical inspection tools and SEM tools enables the acquisition of design positions from optical inspection tools during the pixel-pair design alignment setup step, providing a throughput advantage over that of SEM tools alone.

[0051] The results file allows you to add anchor points for each defect. If a defect is within a specific radius, you can add an anchor point for several defects. The radius can vary depending on the cell size and the accuracy of the SEM inspection tool. The accuracy of the SEM inspection tool can also vary depending on the distance between the anchor point and the target location. If defect clusters exist, the radius can be optimized.

[0052] For each defect corresponding to the anchored SEM image, a design fragment can be extracted. The design fragment can be presented (using an image or a GAN) and aligned to the corresponding SEM image. The determined offset can be used to modify the defect location corresponding to the target defect. This reduces the location uncertainty from ±125nm to ±25nm.

[0053] In this example, the die is divided into a 1mm x 1mm grid (or some other predetermined grid cells), and one or more locations within each grid can be selected as anchor points. The grids can be ranked. Therefore, a predictable number of anchor locations are available, and the maximum permissible distance from the target to the anchor location can be satisfied. After successful anchor alignment, the location filter used during defect detection can be adjusted to a smaller value.

[0054] Figure 2 This is a block diagram of an embodiment of system 200. System 200 includes a wafer inspection tool (which includes an electron column 201) configured to generate an image of wafer 204.

[0055] The wafer inspection tool includes an output acquisition subsystem, which comprises at least an energy source and a detector. The output acquisition subsystem may be an electron beam-based output acquisition subsystem. For example, in one embodiment, the energy directed to wafer 204 contains electrons, and the energy detected from wafer 204 contains electrons. In this way, the energy source may be an electron beam source. Figure 2 In one embodiment shown, the output acquisition subsystem includes an electron column 201 coupled to the computer subsystem 202. A stage 210 holds the wafer 204.

[0056] For example Figure 2 As shown, electron column 201 includes electron beam source 203 configured to generate electrons focused onto wafer 204 by one or more elements 205. Electron beam source 203 may include, for example, a cathode source or an emitter tip. The one or more elements 205 may include, for example, a gun lens, an anode, a beam limiting aperture, a gate valve, a beam current selection aperture, an objective lens, and a scanning subsystem, all of which may include any such suitable elements known in the art.

[0057] Electrons returning from wafer 204 (e.g., secondary electrons) can be focused onto detector 207 by one or more elements 206. One or more elements 206 may include, for example, a scanning subsystem, which may be the same scanning subsystem included in element 205.

[0058] The electronic column 201 may also include any other suitable elements known in the art.

[0059] although Figure 2The electron beam 201 is shown configured such that electrons are guided to the wafer 204 at an oblique incident angle and scattered from the wafer 204 at another oblique angle. However, the electron beam can be guided to and scattered from the wafer 204 at any suitable angle. Furthermore, the electron beam-based output acquisition subsystem can be configured to generate images of the wafer 204 using multiple modes (e.g., with different illumination angles, collection angles, etc.). These multiple modes of the electron beam-based output acquisition subsystem can differ in terms of any image generation parameters of the output acquisition subsystem.

[0060] As described above, computer subsystem 202 may be coupled to detector 207. Detector 207 may detect electrons returning from the surface of wafer 204, thereby forming an electron beam image of wafer 204. The electron beam image may include any suitable electron beam image. Computer subsystem 202 may be configured to use the output of detector 207 and / or the electron beam image to perform any of the functions described herein. Computer subsystem 202 may be configured to perform any additional steps described herein. System 200 (containing Figure 2 The output acquisition subsystem shown can be further configured as described in this document.

[0061] It should be noted that the information provided in this article... Figure 2 The configuration of the electron beam-based output acquisition subsystem that can be used in the embodiments described herein is explained in general terms. The configuration of the electron beam-based output acquisition subsystem described herein can be modified to optimize the performance of the output acquisition subsystem, as is typically done when designing commercial output acquisition systems. Alternatively, the system described herein can be implemented using existing systems (e.g., by adding the functionality described herein to an existing system). For some such systems, the methods described herein may provide optional functionality for the system (e.g., in addition to other system functionalities). Alternatively, the system described herein may be designed as a completely new system.

[0062] Although the output acquisition subsystem has been described above as an electron beam-based output acquisition subsystem, it can also be an ion beam-based output acquisition subsystem. This output acquisition subsystem can be as follows: Figure 2 The configuration shown is typical, with the exception that the electron beam source can be replaced by any suitable ion beam source known in the art. Additionally, the output acquisition subsystem can be any other suitable ion beam-based output acquisition subsystem, such as those included in commercially available focused ion beam (FIB) systems, helium ion microscopy (HIM) systems, and secondary ion mass spectrometry (SIMS) systems.

[0063] The computer subsystem 202 includes a processor 208 and an electronic data storage unit 209. The processor 208 may include a microprocessor, a microcontroller, or other devices.

[0064] Computer subsystem 202 may be coupled to components of system 200 in any suitable manner (e.g., via one or more transmission media, which may include wired and / or wireless transmission media) such that processor 208 can receive output. Processor 208 may be configured to use the output to perform certain functions. A wafer inspection tool may receive instructions or other information from processor 208. Processor 208 and / or electronic data storage unit 209 may optionally communicate electronically (not described) with another wafer inspection tool, wafer metrology tool, or wafer inspection tool to receive additional information or send instructions.

[0065] Processor 208 communicates electronically with a wafer inspection tool (e.g., detector 207). Processor 208 can be configured to process images generated using measurements from detector 207. For example, the processor can perform an embodiment of method 100.

[0066] The computer subsystem 202, other systems, or other subsystems described herein may be part of a variety of systems, including personal computer systems, graphics computers, mainframe computer systems, workstations, network appliances, Internet appliances, or other devices. The subsystem or system may also include any suitable processor known in the art, such as a parallel processor. Additionally, the subsystem or system may include a platform with high-speed processing and software, either as a standalone or networked tool.

[0067] The processor 208 and electronic data storage unit 209 may be housed in or be part of the system 200 or another device. In an example, the processor 208 and electronic data storage unit 209 may be part of a separate control unit or in a centralized quality control unit. Multiple processors 208 or electronic data storage units 209 may be used.

[0068] Processor 208 can be implemented in any combination of hardware, software, and firmware. Furthermore, its functions as described herein can be executed by a single unit or divided among different components, each of which can then be implemented in any combination of hardware, software, and firmware. The program code or instructions of processor 208 for implementing the various methods and functions can be stored in a readable storage medium, such as the memory in electronic data storage unit 209 or other memory.

[0069] If system 200 comprises more than one computer subsystem 202, the different subsystems can be coupled to each other, enabling the transmission of images, data, information, instructions, etc., between the subsystems. For example, a subsystem can be coupled to an additional subsystem via any suitable transmission medium, which can include any suitable wired and / or wireless transmission medium known in the art. Two or more of such subsystems can also be effectively coupled via a shared computer-readable storage medium (not shown).

[0070] Processor 208 may be configured to perform certain functions using the output of system 200 or other outputs. For example, processor 208 may be configured to send output to electronic data storage unit 209 or another storage medium. Processor 208 may be further configured as described herein.

[0071] In this example, processor 208 is configured to receive a result file for the wafer from an optical inspection system (e.g., optical inspection system 211). The result file contains anchor points on the wafer. Processor 208 generates a defect inspection image at the anchor points on wafer 204; aligns a design fragment to the defect inspection image at the anchor points, thereby generating an aligned defect inspection image; and detects defects in the aligned defect inspection image. The design fragment may be a 1mm x 1mm area on the bare die of wafer 204. The aligned defect inspection image may have a positional uncertainty of ±25nm. The 1mm x 1mm area can be used based on the accuracy of the SEM inspection tool and the capabilities of the image content around the defect, thus allowing the image processing algorithm to align and perform defect detection and classification. Smaller design fragment sizes are possible, and 1mm x 1mm is merely an example.

[0072] In this example, the optical inspection system 211 can be configured to generate pixel-pair design alignment image blocks. Anchor points are selected from the pixel-pair design alignment image blocks. The GAN unit in the computer subsystem 202 or the optical inspection system 211 can be configured to select anchor points from the pixel-pair design alignment image blocks. The GAN unit can be a processor (e.g., processor 208) or can be operated by it.

[0073] The processor 208 can be further configured to perform fine alignment of the defect inspection image using targets on the defect inspection image.

[0074] The processor 208 can also be configured to align the SEM image to the design at a location near the target. The processor 208 can send instructions to the stage 210 to move it to the target location for defect detection.

[0075] Processor 208 or computer subsystem 202 may be part of a defect inspection system, testing system, metrology system, or some other type of system. Therefore, the embodiments disclosed herein describe configurations that may be customized in several ways for systems with varying capabilities that are more or less suitable for different applications.

[0076] Processor 208 may be configured according to any of the embodiments described herein. Processor 208 may also be configured to perform other functions or additional steps using the output of system 200 or using images or data from other sources.

[0077] Processor 208 can be communicatively coupled to any of the various components or subsystems of system 200 in any manner known in the art. For example, computer subsystem 202 may be coupled to optical inspection system 211. Furthermore, processor 208 may be configured to receive and / or acquire data or information from other systems (e.g., inspection results from inspection systems (e.g., inspection tools), remote databases containing design data, and the like) via a transmission medium (which may include wired and / or wireless portions). In this manner, the transmission medium can serve as a data link between processor 208 and other subsystems of system 200 or systems external to system 200.

[0078] The various steps, functions, and / or operations of the system 200 and methods disclosed herein are implemented by one or more of the following: electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controls / switches, microcontrollers, or computing systems. Program instructions for implementing methods such as those described herein may be transmitted via or stored on a carrier medium. The carrier medium may include, for example, read-only memory, random access memory, magnetic disks or optical disks, non-volatile memory, solid-state memory, magnetic tape, and similar storage media. The carrier medium may include, for example, transmission media such as wires, cables, or wireless transmission links. For example, the various steps described throughout this disclosure may be implemented by a single processor 208 (or computer subsystem 202) or alternatively by multiple processors 208 (or multiple computer subsystems 202). Furthermore, different subsystems of system 200 may include one or more computing or logic systems. Therefore, the foregoing description should not be construed as a limitation of this disclosure, but is merely illustrative.

[0079] In this example, a non-transitory computer-readable storage medium containing one or more programs is provided. The programs are configured to perform the following steps on one or more processors. First, results for a wafer are received from an optical inspection system. The result file contains anchor points on the wafer. Second, a defect inspection image is generated at the anchor points on the wafer. Third, a design fragment is aligned to the defect inspection image at the anchor points, thereby generating an aligned defect inspection image. Fourth, defects in the aligned defect inspection image are detected. The aligned defect inspection image may have a positional uncertainty of ±25 nm.

[0080] The optical inspection system can be configured to generate pixel-pair design alignment image blocks, and anchor points can be selected from these image blocks. In this example, a GAN is used to select anchor points from the pixel-pair design alignment image blocks.

[0081] Anchor points are received from the optical inspection system via SEM results files.

[0082] One or more programs can be further configured to perform fine alignment of the defect inspection image using targets on the defect inspection image.

[0083] The steps of the methods described in the various embodiments and examples disclosed herein are sufficient to carry out the methods of the present invention. Therefore, in the embodiments, the methods are essentially composed of a combination of the steps of the methods disclosed herein. In another embodiment, the method consists of such steps.

[0084] Each of the steps in the method may be performed as described herein. The method may also include any other steps that can be performed by a processor and / or computer subsystem or system described herein. Such steps may be performed by one or more computer systems that may be configured according to any of the embodiments described herein. Additionally, the method described above may be performed by any of the system embodiments described herein.

[0085] Although this disclosure has been described with respect to one or more specific embodiments, it will be understood that other embodiments of this disclosure may be made without departing from the scope of this disclosure.

Claims

1. An inspection method, comprising: An optical inspection system is used to determine the anchor points for alignment performed by scanning electron microscope tools; The scanning electron microscope tool receives a result file of the wafer from the optical inspection system, wherein the result file contains the anchor point, the location of the defect on the wafer, and the defect classification at the defect location; The scanning electron microscope tool is used to generate defect inspection images at the anchor point; Aligning a design fragment to the defect inspection image at the anchor point, thereby generating an aligned defect inspection image, wherein the design fragment includes a region on the wafer; and Defects are detected in the aligned defect inspection image, and The optical inspection system generates a pixel-pair design alignment image block and selects the anchor point from the pixel-pair design alignment image block.

2. The inspection method of claim 1, wherein a generative adversarial network is used to select the anchor point from the pixel pair design alignment image block.

3. The inspection method according to claim 1, wherein determining the anchor point comprises: ranking the pixel pair design alignment image blocks, and selecting one of the pixel pair design alignment image blocks as the anchor point.

4. The inspection method according to claim 1, wherein the design segment is a 1 mm by 1 mm area on the bare die of the wafer.

5. The inspection method of claim 1, further comprising using a target on the defect inspection image to perform fine alignment of the defect inspection image.

6. The inspection method according to claim 1, wherein the aligned defect inspection image has a positional uncertainty of ±25 nm.

7. The inspection method according to claim 1, wherein the detection occurs during array mode.

8. An inspection system comprising: Scanning electron microscope tools, which include: A stage configured to hold the wafer; An electron beam source configured to emit electrons toward the wafer; and A detector configured to detect electrons received from the wafer; A processor, which communicates electronically with the scanning electron microscope tool, is configured to: Receives a result file for a wafer from an optical inspection system, wherein the result file includes anchor points for alignment performed by the scanning electron microscope tool, defect locations on the wafer, and defect classifications at the defect locations, wherein the optical inspection system is configured to determine the anchor points; Generate a defect inspection image at the anchor point on the wafer; Aligning a design fragment to the defect inspection image at the anchor point, thereby generating an aligned defect inspection image, wherein the design fragment includes a region on the wafer; and Defects are detected in the aligned defect inspection image, and The optical inspection system is configured to generate pixel-pair design alignment image blocks and select the anchor point from the pixel-pair design alignment image blocks.

9. The inspection system of claim 8, further comprising a generative adversarial network unit configured to select the anchor point from the pixel-pair design aligned image block.

10. The inspection system of claim 8, wherein the design segment is a 1 mm by 1 mm area on a bare die on the wafer.

11. The inspection system of claim 8, wherein the processor is further configured to perform fine alignment of the defect inspection image using a target on the defect inspection image.

12. The inspection system of claim 8, wherein the aligned defect inspection image has a positional uncertainty of ±25 nm.

13. A non-transitory computer-readable storage medium containing one or more programs, said programs being configured to perform the following steps on one or more processors: Receives a result file for a wafer from an optical inspection system, wherein the result file includes anchor points for alignment performed by a scanning electron microscope tool, defect locations on the wafer, and defect classifications at the defect locations, wherein the optical inspection system is configured to determine the anchor points; Generate a defect inspection image at the anchor point on the wafer; Aligning a design fragment to the defect inspection image at the anchor point, thereby generating an aligned defect inspection image, wherein the design fragment includes a region on the wafer; and Defects are detected in the aligned defect inspection image. The optical inspection system is configured to generate pixel-pair design alignment image blocks and select the anchor point from the pixel-pair design alignment image blocks.

14. The non-transitory computer-readable storage medium of claim 13, wherein a generative adversarial network is used to select the anchor point from the pixel pair design aligned image block.

15. The non-transitory computer-readable storage medium of claim 13, wherein the one or more programs are further configured to perform fine alignment of the defect inspection image using a target on the defect inspection image.

16. The non-transitory computer-readable storage medium of claim 13, wherein the aligned defect inspection image has a positional uncertainty of ±25 nm.

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