Display panel

Abstract

A display panel includes a pixel array and a gate driver. The specification of the pixel array is X*Y pixels. The pixel array includes Y gate lines and a plurality of auxiliary gate lines. A part of these auxiliary gate lines is electrically coupled to the Y gate lines, and another part of these auxiliary gate lines is electrically isolated from these gate lines. (Y+Z) gate driving circuits in the gate driver respectively correspond to these auxiliary gate lines, where Z is a positive integer.

Description

Technical Field

[0001] The present disclosure relates to a display panel, and particularly to a display panel suitable for any cutting ratio. Background Art

[0002] In some embodiments, after fabricating pixels, a gate driver, and corresponding traces of the same size on a large glass substrate, the large glass substrate is cut to obtain one or more panels.

[0003] In order to independently drive the panels cut from the large glass substrate, a corresponding number of gate drivers need to be provided on the large glass substrate so that the one or more cut panels can operate independently. Moreover, the number of gate driving circuits included in each gate driver usually depends on the number of pixels in the vertical direction of the large glass substrate, and the number of driving chips depends on the number of pixels in the horizontal direction of the large glass substrate.

[0004] However, if the number of gate drivers is not proportional to the number of driving chips, it will cause problems in the docking of fan-out packaging. Furthermore, if the number of driving circuits in the gate driver is not proportional to the number of driving chips, it will also cause problems in the docking of fan-out packaging. Therefore, how to provide a display panel to solve the above problems is an important issue in the field. Summary of the Invention

[0005] The present disclosure provides a display panel. The display panel includes a pixel array and a gate driver. The pixel array includes Y gate lines and a plurality of auxiliary gate lines. The specification of the pixel array is X*Y pixels. The pixel array includes Y gate lines and a plurality of auxiliary gate lines. A part of the plurality of auxiliary gate lines is electrically coupled to the Y gate lines, and another part of the plurality of auxiliary gate lines is electrically isolated from the Y gate lines. The gate driver includes (Y+Z) gate driving circuits, and the (Y+Z) gate driving circuits respectively correspond to the plurality of auxiliary gate lines, where Z is a positive integer.

[0006] In summary, the display panel provided by the present disclosure includes redundant gate driving circuits, thereby improving the problem of docking with driving chips. Moreover, the redundant gate driving circuits will have corresponding auxiliary gate lines. Therefore, the redundant vertical auxiliary gate lines in the display panel of the present disclosure are electrically insulated from the horizontal gate lines, further reducing the influence of redundant traces on the pixel array. Brief Description of the Drawings

[0007] To make the above and other objects, features, advantages, and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows:

[0008] Figure 1ASchematic diagram of a display panel shown in some embodiments of the present disclosure document.

[0009] Figure 1B Schematic diagram of a gate driver shown in some embodiments of the present disclosure document.

[0010] Figure 2 Schematic diagram of the circuit layout of a gate driving circuit, a driving chip, an auxiliary gate line, a gate line, a signal line, and a data line group shown in some embodiments of the present disclosure document.

[0011] Figure 3 Schematic diagram of the circuit layout of a gate driving circuit, an auxiliary gate line, a gate line, and a signal line shown in some embodiments of the present disclosure document.

[0012] Figure 4 Schematic diagram of the circuit architecture of a gate driving circuit shown in some embodiments of the present disclosure document.

[0013] Figure 5 Schematic diagram of the circuit architecture of a gate driving circuit shown in some embodiments of the present disclosure document.

[0014] Figure 6 Schematic diagram of the circuit layout of a gate driving circuit, an auxiliary gate line, a gate line, and a signal line shown in some embodiments of the present disclosure document.

[0015] Figure 7 Schematic diagram of the circuit layout of a gate driving circuit, an auxiliary gate line, a gate line, and a signal line shown in some embodiments of the present disclosure document.

[0016] Description of reference numerals:

[0017] To make the above and other objects, features, and advantages of the present disclosure more obvious and understandable, the descriptions of the attached symbols are as follows:

[0018] 30: Through hole

[0019] 31, 32, 33, 34: Traces

[0020] 100: Display panel

[0021] 110: Substrate

[0022] 112, 114, 116: Gate drivers

[0023] 122, 124, 126: Driving chip groups

[0024] 130: Pixel array

[0025] 410, 510: Pull-up control circuits

[0026] 420,520: Pull-up circuit

[0027] 430,440,530,540: Pull-down circuit

[0028] 450,460,550,560: Pull-down control circuit

[0029] GOA, GOAr, GOA(n), GOAr(n): Gate driving circuit

[0030] COF: Driving chip

[0031] G1, G2~Gy-1, Gy: Gate line

[0032] VG1, VG2~VGy-1, VGy, VGp-1, VGp: Auxiliary gate line

[0033] AA: Display area

[0034] D1~Db, Db~Dq: Data line group

[0035] D11~D13, D21~D23: Data line

[0036] BUSL1, BUSL2, DC: Signal line

[0037] HC1, HC2, HC7: Clock signal

[0038] T11, T12, T21, T32~T35, T41~T44, T51~T56, T61~T66: Transistor

[0039] LC1, LC2: Low-frequency clock signal

[0040] Q(n): Operation node

[0041] P(n), K(n): Voltage stabilizing node

[0042] VSS, VSSQ: System low voltage terminal

[0043] Q(n-6), Q(n-2), ST, S(n+6), S(n): Control signal

[0044] Vf: Potential

[0045] G(n): Gate control signal

[0046] SV(n): Voltage stabilizing signal

[0047] R, G, B: Sub-pixel

[0048] PIX: Pixel Detailed Implementation Modes

[0049] The following are detailed descriptions with reference to the accompanying drawings by way of examples. However, the provided examples are not intended to limit the scope covered by the present disclosure, and the description of the structure and operation is not intended to limit its execution order. Any structure formed by recombining elements, as long as the resulting device has equivalent technical effects, falls within the scope covered by the present disclosure. Additionally, the drawings are for illustrative purposes only and are not drawn to the original scale. For ease of understanding, the same or similar elements in the following description will be denoted by the same reference numerals.

[0050] The terms used throughout the specification and claims, unless otherwise specifically noted, generally have their ordinary meanings as used in this field, in the context of the present disclosure, and in the specific context.

[0051] In addition, the terms "comprise", "include", "have", "contain", etc. used in this text are all open-ended terms, meaning "including but not limited to". In addition, the "and / or" used in this text includes any one of the one or more items in the relevant listed items and all combinations thereof.

[0052] In this text, when an element is referred to as "coupled" or "coupled", it may refer to "electrically coupled" or "electrically coupled". "Coupled" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this text to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms.

[0053] Please refer to Figure 1A , Figure 1A which is a schematic diagram of a display panel 100 shown according to some embodiments of the present disclosure document. As Figure 1A shown, the display panel 100 includes a substrate 110, a pixel array 130, gate drivers 112, 114, and 116, and driver chip sets 122, 124, and 126. In some embodiments, the substrate 110 can be implemented by a glass substrate. The pixel array 130 and the gate drivers 112, 114, and 116 are disposed on the substrate 110, and the pixel array 130 is disposed in the display area AA on the substrate 110.

[0054] To reduce the widths of the left and right borders in the display panel, the auxiliary gate lines VG1 to VGy extend from the driver chip sets 122, 124, and 126 on one side (e.g., the upper / lower side) in the display panel 100, so that the gate drivers 112, 114, and 116 disposed on the same side as the driver chip sets 122, 124, and 126 in the display panel 100 are correspondingly connected to the horizontal gate lines G1 to Gy via the vertical auxiliary gate lines VG1 to VGy. Each of the horizontal gate lines G1 to Gy is electrically coupled to the pixels PIX in the same column in the pixel array 130, so that at least one of the gate drivers 112, 114, and 116 transmits the corresponding gate control signal to the horizontal gate lines G1 to Gy via the corresponding one of the auxiliary gate lines VG1 to VGy.

[0055] In an embodiment of the present disclosure, for the complete docking of the fan-out package, a part of the driver chips COF is divided into groups (e.g., 3 groups of driver chip sets 122, 124, and 126) according to the number of gate drivers (e.g., 3 gate drivers 112, 114, and 116) to respectively correspond to each gate driver, and the remaining driver chips COF are implemented as data driver chips that do not need to dock with the gate drivers.

[0056] For example, if the display panel 100 requires a total of 16 driver chips COF to drive 16 * 256 channels (pixel rows), since 16 driver chips COF cannot be evenly corresponded to 3 gate drivers 112, 114, and 116. Therefore, 15 driver chips COF are divided into 3 groups of driver chip sets 122, 124, and 126, so as to respectively correspond to the 3 gate drivers 112, 114, and 116. And the remaining 16th driver chip COF is a data driver chip that does not need to dock with the gate driver.

[0057] Please refer to Figure 1A and Figure 1B , Figure 1B is a schematic diagram of the gate driver 112 shown in some embodiments according to the present disclosure document. As Figure 1B shown, the gate driver 112 includes driving circuits GOA and GOAr.

[0058] The total number of the gate driving circuits GOA and GOAr of the gate driver 112 is determined according to the number of the driver chips COF included in the foregoing driver chip set 122, so that the number of the driving circuits GOA and GOAr in the gate driver 112 is a multiple of the number of the driver chips COF included in the driver chip set 122, and the fan-out package between the gate driver 112 and the driver chips COF included in the corresponding driver chip set 122 can be completely docked.

[0059] Under such an architecture, the total number of gate driving circuits GOA and GOAr is greater than the number of pixel columns / gate lines included in the pixel array 130. Therefore, Y gate driving circuits GOA in the gate driver 112 are electrically coupled to the corresponding gate lines G1 to Gy via the auxiliary gate lines VG1 to VGy, respectively, and the Z gate driving circuits GOAr in the gate driver 112 can be understood by the remaining gate driving circuits. How to configure the remaining gate driving circuits GOAr and their related layouts will be described in detail in subsequent embodiments.

[0060] Specifically, assume that the pixel array 130 has X pixels in the horizontal direction and Y pixels in the vertical direction, and its specification is X*Y pixels. The pixel array 130 includes Y gate lines G1 to Gy, and the gate lines G1 to Gy are electrically coupled to the corresponding Y gate driving circuits GOA via the auxiliary gate lines VG1 to VGy, respectively.

[0061] The total number "(Y + Z)" of the Y gate driving circuits GOA and the Z gate driving circuits GOAr included in the gate driver 112 is implemented as a multiple of the number "M" of the M driving chips COF in the foregoing driving chip group 122. In other words, the "M" is a factor of the "(Y + Z)". And the "M", "Y", and "Z" are all positive integers.

[0062] In this way, the gate driving circuits GOA and GOAr in the gate driver 112 are evenly corresponding / assigned to the driving chips COF in the driving chip group 122, so that the fan-out package between the gate driving circuits GOA and GOAr included in the gate driver 112 and the driving chips COF included in the driving chip group 122 can be completely docked.

[0063] The architectures of the gate drivers 114 and 116 are generally similar to that of the gate driver 112. The gate driving circuits included in the gate drivers 114 and 116 can also be evenly corresponding / assigned to the driving chips COF in the driving chip groups 124 and 126, and the corresponding relationship between the respective gate driving circuits of the gate drivers 114 and 116 and the driving chips COF included in the driving chip groups 124 and 126 is similar to the corresponding relationship between the gate driving circuits GOA and GOAr included in the gate driver 112 and the driving chips COF included in the driving chip group 122, so details are not described herein again.

[0064] In some embodiments, the gate driving circuit GOAr is used to provide a regulated voltage signal. In other embodiments, the gate driving circuit GOAr is electrically isolated from the pixel array 130. The layout and operation mode of the gate driving circuit GOAr and the pixel array 130 will be described in detail in subsequent embodiments.

[0065] Please refer to Figure 2 , Figure 2 , which is a schematic diagram of the circuit layout of the gate driver circuits GOA and GOAr, the driving chip COF, and the auxiliary gate lines VG1 to VGy, gate lines G1 to Gy, signal lines BUSL1, BUSL2, and data line groups D1 to Dq shown in some embodiments of the present disclosure. As Figure 2 shown, the gate driver circuit GOA is electrically coupled to the auxiliary gate lines VG1 to VGy disposed in the display area AA respectively, and the gate driver circuit GOAr is electrically coupled to the auxiliary gate lines VGp-1 to VGp disposed in the display area AA respectively. The auxiliary gate lines VG1 to VGy are electrically coupled to the corresponding gate lines G1 to Gy respectively, and the auxiliary gate lines VG1 to VGy are electrically insulated from the gate lines G1 to Gy.

[0066] The gate driver circuit GOA is electrically coupled to the corresponding signal lines BUSL1 and BUSL2. The signal lines BUSL1 and BUSL2 are used to transmit clock signals HC1 and HC2 respectively. In some embodiments, the display panel 100 may have a greater number of signal lines for transmitting a greater number of clock signals. For example, 7 signal lines are used to transmit 7 clock signals. Therefore, the present disclosure is not limited thereto.

[0067] The driving chips COF included in the driving chip group 122 are electrically coupled to the corresponding data line groups D1 to Db and Db+1 to Dq respectively. The data line group D1 includes data lines D11, D12, and D13. Similarly, the data line group D2 includes data lines D21, D22, and D23, and so on.

[0068] Thus, in the case where the total number of the gate driver circuits GOA and GOAr included in the gate driver 112 is a multiple of the number of the driving chips COF included in the driving chip group 122, the fan-out package between the gate driver circuits GOA and GOAr included in the gate driver 112 and the driving chips COF included in the driving chip group 122 can be completely docked.

[0069] Please also refer to Figure 3 , Figure 3 , which is a schematic diagram of the circuit layout of the gate driver circuits GOA and GOAr, the auxiliary gate lines VG1, VG2, VGp-1, and VGp, gate lines G1 and G2, and signal lines BUSL1 and BUSL2 shown in some embodiments of the present disclosure. As Figure 3 shown

[0070] As shown, vias 30 are provided at the overlapping portions of the trace 31 of the gate driving circuit GOA with the auxiliary gate lines VG1 and VG2, so that the gate driving circuit GOA is electrically coupled to the auxiliary gate lines VG1 and VG2. Vias 30 are provided at the overlapping portions of the trace 33 of the gate driving circuit GOAr with the auxiliary gate lines VGp-1 and VG-p, so that the gate driving circuit GOAr is electrically coupled to the auxiliary gate lines VGp-1 and VG-p.

[0071] Vias 30 are provided at the overlapping portions of the trace 32 of the gate driving circuit GOA with the signal lines BUSL1 and BUSL2, so that the gate driving circuit GOA is electrically coupled to the signal lines BUSL1 and BUSL2. On the other hand, vias are not provided at the overlapping portions of the trace 34 of the gate driving circuit GOAr with the signal lines BUSL1 and BUSL2, so that the gate driving circuit is electrically insulated from the signal lines BUSL1 and BUSL2.

[0072] In some embodiments, each of the data lines D21, D22, and D23 included in the data line group D2 is electrically coupled to the sub-pixels R, G, or B in the same sub-pixel row in the pixel array 130.

[0073] The connection relationships of the data line groups D3, Dq-1, and Dq with the sub-pixels R, G, or B are similar to the connection relationships of the data lines D21, D22, and D23 included in the data line group D2 with the corresponding sub-pixels R, G, or B, so they will not be described herein again.

[0074] Please refer to Figure 3 and Figure 4 , Figure 4 is a schematic diagram of the circuit architecture of the gate driving circuit GOA(n) shown in some embodiments according to the present disclosure document. In Figure 3 the shown gate driving circuit GOA

[0075] each corresponds to Figure 4 the gate driving circuit GOA(n). As Figure 4 shown, the gate driving circuit 0GOA(n) includes a pull-up control circuit 410, a pull-up circuit 420, a pull-down control circuit 450 and 460, a first pull-down circuit 430, and a second pull-down circuit 440.

[0076] The pull-up control circuit 410 includes transistors T12 and T11. The first end of the transistor T12 is used to receive the clock signal HC7, and the second end of the transistor T12 is electrically coupled to the gate terminal of the transistor T11.

[0077] And the gate terminal of the transistor T12 is used to receive the control signal Q(n-6). The transistor T12 is used to conduct the circuit path of the clock signal HC7 to the gate terminal of the transistor T11 according to the control signal Q(n-6).

[0078] The first end of transistor T11 is electrically coupled to the system high voltage terminal VDD, and the second end of transistor T11 is electrically coupled to the operating node Q(n). When transistor T11 is turned on according to the clock signal HC7, the voltage of the system high voltage terminal VDD is transmitted to the operating node Q(n) via transistor T11.

[0079] The pull-up circuit 420 includes transistor T21. The first end of transistor T21 is used to receive the clock signal HC1. The second end of transistor T21 is electrically coupled to the trace 31 for outputting the gate control signal G(n). The gate terminal of transistor T21 is electrically coupled to the operating node Q(n). Transistor T21 is used to turn on or off the circuit path between the clock signal HC1 and the gate control signal G(n) according to the potential of the operating node Q(n).

[0080] When transistor T21 turns on the circuit path between the clock signal HC1 and the gate control signal G(n) and the clock signal HC1 has a high logic level, the gate control signal G(n) has a high logic level, and the gate control signal G(n) is transmitted to the corresponding gate line (e.g., gate line VG1) via the trace 31 and the corresponding auxiliary gate line (e.g., auxiliary gate line VG1), so as to turn on the circuit path for setting the data voltage inside each pixel in the same column of the pixel array 130, as Figure 2 and Figure 3 shown.

[0081] The pull-down control circuit 450 includes transistors T51 to T56. The first end and the gate terminal of transistor T51 are used to receive the low-frequency clock signal LC1. The second end of transistor T51 is electrically coupled to the gate terminal of transistor T53. Transistor T51 is used to turn on the circuit path of the low-frequency clock signal LC1 to the first end of transistor T55 and the gate terminal of transistor T53 according to the low-frequency clock signal LC1.

[0082] The first end of transistor T52 is electrically coupled to the gate terminal of transistor T53. The second end of transistor T52 is electrically coupled to the system low voltage terminal VSSQ. The gate terminal of transistor T52 is electrically coupled to the operating node Q(n). Transistor T52 is used to turn on the circuit path from the gate terminal of transistor T53 to the system low voltage terminal VSSQ according to the potential of the operating node Q(n).

[0083] The first terminal of transistor T53 is used to receive the low-frequency clock signal LC1. The gate terminal of transistor T53 is electrically coupled to the second terminal of transistor T51 and the first terminal of transistor T55. The second terminal of transistor T53 is electrically coupled to the regulated voltage node P(n). When the potential of the operating node Q(n) has a low logic level and transistor T51 is turned on according to the low-frequency clock signal LC1, the low-frequency clock signal LC1 is transmitted to the gate terminal of transistor T53 via transistor T51, enabling transistor T53 to turn on the circuit path of the low-frequency clock signal LC1 to the regulated voltage node P(n), thereby pulling up the potential of the regulated voltage node P(n).

[0084] The first terminal of transistor T55 is electrically coupled to the gate terminal of transistor T53. The gate terminal of transistor T55 is used to receive the control signal Q(n - 2). The second terminal of transistor T55 is electrically coupled to the system low voltage terminal VSSQ. Transistor T55 is used to turn on the circuit path from the gate terminal of transistor T53 to the system low voltage terminal VSSQ according to the control signal Q(n - 2). When the control signal Q(n - 2) has a high logic level, transistor T55 turns on the circuit path from the gate terminal of transistor T53 to the system low voltage terminal VSSQ, turning off the circuit path of the low-frequency clock signal LC1 to the regulated voltage node P(n) by transistor T53.

[0085] Transistors T56 and T54 are both electrically coupled between the regulated voltage node P(n) and the system low voltage terminal VSSQ. The gate terminals of transistors T56 and T54 are used to receive the control signals Q(n - 2) and Q(n) respectively. Transistors T56 and T54 are respectively used to turn on the circuit path between the regulated voltage node P(n) and the system low voltage terminal VSSQ according to the control signals Q(n - 2) and Q(n). When the control signal Q(n - 2) or Q(n) has a high logic level, the corresponding one of transistors T56 and T54 turns on, thereby pulling down the potential of the regulated voltage node P(n).

[0086] The first pull-down circuit 430 includes transistors T32 to T35. The first pull-down circuit 430 is used to pull down the potential of the gate control signal G(n) and pull up the potential of the gate terminal of transistor T11 in the pull-up control circuit 410. The second pull-down circuit 440 includes transistors T41 to T44. The second pull-down circuit 440 is used to pull down the potential of the operating node Q(n). Transistors T44 and T41 respectively turn on the circuit path from the operating node Q(n) to the system voltage terminal VSSQ according to the control signals ST and S(n + 6).

[0087] The regulated voltage node P(n) is electrically coupled to the gate terminals of transistors T42, T32, and T34. When the potential of the regulated voltage node P(n) has a high logic level, transistor T42 conducts the circuit path from the system low voltage terminal VSSQ to the operating node Q(n), causing transistor T21 to turn off the circuit path from the clock signal HC1 to the gate control signal G(n) according to the potential of the operating node Q(n). At this time, transistor T34 conducts the circuit path from the gate terminal of transistor T11 (the potential of the gate terminal of transistor T11 is indicated by the control signal S(n)) to the system low voltage terminal VSSQ. And, transistor T32 conducts the circuit path from the gate control signal G(n) to the system low voltage terminal VSS, outputting the voltage of the system low voltage terminal VSS as the gate control signal G(n).

[0088] The connection relationships among transistors T61 - T66 in the pull - down control circuit 460 are respectively similar to those among transistors T51 - T55 in the pull - down control circuit 450. Compared with the pull - down control circuit 450, the difference in the pull - down control circuit 460 is that the clock signal LC1 is replaced by LC2, and the regulated voltage node P(n) is replaced by K(n). The remaining connection relationships and operating modes of transistors T61 - T66 in the pull - down control circuit 460 are generally similar to those of transistors T51 - T55 in the pull - down control circuit 450, so they will not be elaborated here.

[0089] Similarly, the regulated voltage node K(n) is electrically coupled to the gate terminals of transistors T43, T33, and T35. When the potential of the regulated voltage node P(n) has a high logic level, transistor T43 conducts the circuit path from the system low voltage terminal VSSQ to the operating node Q(n), causing transistor T21 to turn off the circuit path from the clock signal HC1 to the gate control signal G(n) according to the potential of the operating node Q(n). At this time, transistor T35 conducts the circuit path from the gate terminal of transistor T11 (the potential of the gate terminal of transistor T11 is indicated by the control signal S(n)) to the system low voltage terminal VSSQ. And, transistor T33 conducts the circuit path from the gate control signal G(n) to the system low voltage terminal VSS, outputting the voltage of the system low voltage terminal VSS as the gate control signal G(n).

[0090] Please refer to Figure 3 and Figure 5 , Figure 5 is a schematic diagram of the circuit architecture of the gate driving circuit GOAr(n) shown according to some embodiments of the present disclosure. In Figure 3 each of the shown gate driving circuits GOAr corresponds to Figure 5 the gate driving circuit GOAr(n). As Figure 5As shown, the gate driving circuit GOAr(n) includes a pull-up control circuit 510, a pull-up circuit 520, pull-down control circuits 550 and 560, a first pull-down circuit 530, and a second pull-down circuit 540. The pull-up control circuit 510 includes transistors T11 and T12, and the pull-up circuit 520 includes transistor T21.

[0091] In Figure 3 the embodiment, vias are not provided at the overlapping portions of the trace 34 of the gate driving circuit GOAr(n) with the signal lines BUS1 and BUS2, so that the gate driving circuit GOAr(n) is electrically insulated from the signal line BUSL1 for transmitting the clock signal HC1 and the signal line (not shown) of HC7. Therefore, compared with Figure 4 the architecture of the gate driving circuit GOA(n) in

[0092] In this way, the transistor T11 does not operate according to the potential Vf (for example, a low logic level) transmitted by the transistor T12. In the case where the transistor T11 does not operate, the transistor T21 will also remain in the off state.

[0093] In this way, the pull-up control circuit 510 and the pull-up circuit 520 in the gate driving circuit GOAr(n) remain off and do not operate, so as not to pull up the potential of the output terminal of the gate driving circuit GOAr(n).

[0094] In some embodiments, the gate driving circuit GOAr(n) is further used to output a regulated voltage signal SV(n). Specifically, the pull-down control circuits 550, 560 and the pull-down circuits 530, 540 in the gate driving circuit GOAr(n) still operate continuously and provide a regulated voltage signal SV(n) stable at a low logic level to the corresponding auxiliary gate lines (for example, Figure 3 the auxiliary gate lines VGp-1 or VGp shown).

[0095] In Figure 5 the embodiment, the connection relationship and operation mode of the pull-down control circuits 550, 560 and the pull-down circuits 530, 540 in the gate driving circuit GOAr(n) are generally similar to Figure 4 the connection relationship and operation mode of the pull-down control circuits 450, 460 and the pull-down circuits 430, 440 in the gate driving circuit GOA(n) in

[0096] Please refer to Figure 6 , Figure 6Schematic diagram of the gate driving circuit GOA and GOAr, and the auxiliary gate lines VG1, VG2, VGp-1 and VGp, gate lines G1 and G2, and signal lines BUSL1 and BUSL2 shown in some embodiments according to the present disclosure document. In Figure 6 In the embodiment of, vias are not provided at the overlapping portions of the trace 33 of the remaining gate driving circuit GOAr(n) with the auxiliary gate lines VGp-1 and VGp. Therefore, the gate driving circuit GOAr(n) is electrically isolated from the auxiliary gate lines VGp-1 and VGp. In some embodiments, the auxiliary gate lines VGp-1 and VGp are floating wires.

[0097] In Figure 6 In the embodiment of, since the gate driving circuit GOAr(n) is electrically isolated from the auxiliary gate lines VGp-1 and VGp, and the gate driving circuit GOAr(n) is electrically coupled to the signal lines BUSL1 and BUSL2 via the vias 30, signals are still not transmitted to the auxiliary gate lines VGp-1 and VGp.

[0098] In some other embodiments, vias 30 may not be provided at the overlapping portions of the trace 34 of the gate driving circuit GOAr(n) with the signal lines BUSL1 and BUSL2. Therefore, the present disclosure does not take this as a line.

[0099] In Figure 6 the layout of the gate driving circuit GOA(n), gate lines G1 and G2, and auxiliary gate lines VG1, VG2, VGp-1 and VGp is generally similar to Figure 3 the layout of the gate driving circuit GOA(n), gate lines G1 and G2, and auxiliary gate lines VG1, VG2, VGp-1 and VGp in, so it will not be elaborated here.

[0100] Please refer to Figure 7 , Figure 7 Schematic diagram of the circuit layout of the gate driving circuit GOA and GOAr, and the auxiliary gate lines VG1, VG2, VGp-1 and VGp, gate lines G1 and G2, signal lines BUSL1 and BUSL2, and signal line DC shown in some embodiments according to the present disclosure document. In Figure 7 In the embodiment of, vias are not provided at the overlapping portions of the trace 33 of the remaining gate driving circuit GOAr(n) with the auxiliary gate lines VGp-1 and VGp. Therefore, the gate driving circuit GOAr(n) is electrically isolated from the auxiliary gate lines VGp-1 and VGp.

[0101] Furthermore, before entering the display area AA, vias 30 may be provided at the overlapping portions of the auxiliary gate lines VGp-1 and VGp and the signal line DC of the DC signal, so that the auxiliary gate lines VGp-1 and VGp are electrically coupled to the signal line DC of the DC signal, thereby transmitting the DC signal to the auxiliary gate lines VGp-1 and VGp, and further stabilizing the voltage of the auxiliary gate lines VGp-1 and VGp.

[0102] In Figure 7 the embodiment, since the gate driving circuit GOAr(n) is electrically isolated from the auxiliary gate lines VGp-1 and VGp, the gate driving circuit GOAr(n) can be electrically coupled to the signal lines BUSL1 and BUSL2, and still will not output signals to the auxiliary gate lines VGp-1 and VGp.

[0103] In some other embodiments, vias 30 may not be provided at the overlapping portions of the traces 34 of the gate driving circuit GOAr(n) and the signal lines BUSL1 and BUSL2. Therefore, the present disclosure is not limited thereto.

[0104] In Figure 7 the layout of the gate driving circuit GOA(n), the gate lines G1 and G2, and the auxiliary gate lines VG1, VG2, VGp-1 and VGp is generally similar to Figure 3 the layout of the gate driving circuit GOA(n), the gate lines G1 and G2, and the auxiliary gate lines VG1, VG2, VGp-1 and VGp in

[0105] To sum up, the display panel 100 provided in the present disclosure document includes redundant gate driving circuits GOAr, thereby improving the problem of fan-out packaging. Moreover, the redundant gate driving circuits GOAr will have corresponding auxiliary gate lines (for example, the auxiliary gate lines VGp-1 and VGp). In the display panel 100 of the present disclosure document, the redundant vertical auxiliary gate lines VGp-1 and VGp are electrically insulated from the horizontal gate lines G1 to GY, thereby reducing the influence of the redundant traces on the pixel array 130. Furthermore, the present disclosure document can provide a voltage stabilizing signal SV(n) or a DC signal to the redundant vertical auxiliary gate lines VGp-1 and VGp in

[0106] Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the art can make various changes and modifications without departing from the concept and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to what is defined by the claims.

Claims

1. A display panel, comprising: A pixel array, wherein the specification of the pixel array is X*Y pixels, and the pixel array comprises: Y gate lines; and Multiple auxiliary gate lines, wherein a part of the auxiliary gate lines is electrically coupled to the Y gate lines, and another part of the auxiliary gate lines is electrically isolated from the gate lines; and A gate driver, comprising (Y+Z) gate driving circuits, wherein the (Y+Z) gate driving circuits respectively correspond to the auxiliary gate lines, and Z is a positive integer, wherein Z of the (Y+Z) driving circuits included in the gate driver are respectively used to provide a regulated voltage signal to the other part of the auxiliary gate lines.

2. The display panel according to claim 1, wherein Y of the (Y+Z) driving circuits included in the gate driver are respectively electrically coupled to the Y gate lines through a part of the auxiliary gate lines.

3. The display panel according to claim 2, wherein each of the Y driving circuits comprises: A pull-up circuit, configured to be turned on according to the potential of an operation node to output a first clock signal as a gate control signal; A pull-up control circuit, configured to pull up the potential of the operation node according to a first control signal and a second clock signal to turn on the circuit path from the first clock signal to the gate control signal of the pull-up circuit; A pull-down circuit, configured to turn on the circuit path between the gate control signal and a system low voltage terminal according to the potential of a regulated voltage node; and A pull-down control circuit, configured to control the potential of the regulated voltage node according to a second control signal to turn on the circuit path from the gate control signal to the system low voltage terminal of the pull-down circuit.

4. The display panel according to claim 1, wherein the pull-up circuit and the pull-up control circuit of each of the Z driving circuits are respectively electrically isolated from a first clock signal and a second clock signal, so that the pull-up circuit is turned off according to the low logic level of an operation node and electrically isolates the circuit path from the first clock signal to a regulated voltage signal.

5. The display panel according to claim 4, wherein each of the Z driving circuits comprises: A pull-down circuit, configured to turn on the circuit path between the regulated voltage signal and a system low voltage terminal according to the potential of a regulated voltage node; and A pull-down control circuit, configured to control the potential of the regulated voltage node according to a second control signal to turn on the circuit path from the regulated voltage signal to the system low voltage terminal of the pull-down circuit.

6. The display panel according to claim 1, wherein Z of the (Y+Z) driving circuits included in the gate driver are electrically isolated from the other part of the auxiliary gate lines, and the other part of the auxiliary gate lines is used to receive a DC signal.

7. The display panel according to claim 1, wherein the gate driver respectively corresponds to a driving chip group, and the driving chip group comprises M driving chips, and M is a factor of (Y+Z).

8. The display panel according to claim 7, wherein the driving chip group and the gate driver are disposed on the same side of a substrate.

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