Semiconductor device and method for controlling warpage during LAB

Abstract

A semiconductor device has a semiconductor die and a support tape disposed on a back side of the semiconductor die opposite to an active surface of the semiconductor die. A portion of the back side of the semiconductor wafer is removed to reduce its thickness. The semiconductor die is a portion of a semiconductor wafer, and the wafer is singulated to provide the semiconductor die with the support tape disposed on the back side of the semiconductor die. The support tape may be a polyimide tape. A dicing tape is disposed on the support tape. The semiconductor die is disposed on a substrate. A laser shot is projected onto the semiconductor die to bond the semiconductor die to the substrate. The support tape provides stress relief to avoid warping of the semiconductor die during the laser shot. The support tape is removed from the back side of the semiconductor die.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of controlling warpage during LAB. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices are typically connected to a substrate for structural support and electrical interconnection. One known technique for bonding semiconductor devices to a substrate involves laser assisted bonding (LAB), in which a laser shot is projected onto a bonding surface to melt a fusible material. When the laser shot is removed, the fusible material resolidifies and bonds the semiconductor device to the substrate. Laser shots are known to induce stress and possible warping in semiconductor devices due to the presence of heat over a large area, particularly for large and / or thin semiconductor wafers or dies. Compression LAB (cLAB) has been used to process devices with high sensitivity to warping. During the laser shot, compressive pressure is applied to the semiconductor wafer or die. However, cLAB introduces complex process control parameters such as flatness of the compression tool, flatness of the work block, contact speed, force control, and position control. Moreover, during cLAB, there is a high risk of misalignment of the bump pads. Temperature monitoring using an infrared (IR) camera is impractical. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1b illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2r The process of bonding an electrical component covered with PI tape to a substrate using LAB is illustrated;

[0006] Figure 3 illustrates an electrical component bonded to a substrate without warping; and

[0007] Figure 4 A printed circuit board (PCB) is illustrated with different types of packages mounted to a surface of the PCB. DETAILED DESCRIPTION

[0008] In the following description with reference to the accompanying drawings, the present invention is described in one or more embodiments, wherein like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purposes of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0009] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary to perform the circuit function.

[0010] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scored and broken along the non-functional areas of the wafer called saw streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads within the package. Electrical connections can be made with conductive layers, bumps, stud bumps, conductive glue, or wire bonding. Encapsulants or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0011] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0012] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, wherein the active surface 110 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers, which are formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a memory, or other signal processing circuit. The semiconductor die 104 may also include IPDs (such as inductors, capacitors, and resistors) and other circuits for RF signal processing. The surface 108 may be subjected to back grinding to planarize the semiconductor die 104.

[0013] Conductive layer 112 is formed on active surface 110 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0014] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesion layer. Bump 114 can also be crimped or thermo-compressed to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive glue, stud bumps, micro bumps or other electrical interconnects.

[0015] Figure 2a-2r Illustrated is the process of bonding an electrical component to a substrate using LAB. The backside of the electrical component is covered with PI tape to reduce stress and warping. Figure 2a The back grinding tape 120 is provided with Figure 1bThe semiconductor wafer 100 is brought into contact with the back grinding tape 120, wherein the bumps 114 are adhered to the adhesive surface 122, such as Figure 2b The back grinding tape 120 holds the semiconductor wafer 100 securely in place during the subsequent back grinding operation.

[0016] exist Figure 2c In the embodiment of the present invention, the back side 108 of the semiconductor wafer 100 is subjected to a grinding operation using a grinder 126 to reduce the semiconductor wafer 100 from an original thickness of 780 μm to a thickness of approximately 70-300 μm. The grinding operation also planarizes the back side 128 of the semiconductor wafer 100 . Figure 2d The semiconductor wafer 100 is shown with a reduced thickness and a planarized back side 128 .

[0017] exist Figure 2e , a support tape 130 is adhered to the back side 128 of the semiconductor wafer 100. In one embodiment, the support tape 130 is a polyimide (PI) tape having an adhesive coating totaling up to 250 μm in thickness. The adhesive coating may be a silicone or acrylic adhesive. The PI tape 130 is in direct physical contact with the back side 128 of the semiconductor wafer 100 and is secured with the adhesive coating. The PI tape 130 is used to provide structural support and reduce stress and warpage on the device during LAB. The PI tape 130 is heat resistant to 400 °C and has high transmittance in the near infrared (NIR) range, so there is little absorption of laser power. The PI tape 130 has a well-defined emissivity of 0.95, making it suitable for temperature monitoring using an infrared (IR) camera. Other materials may be used for the support tape, which has similar structural and insulating properties sufficient to provide structural support and reduce stress and warpage on the device during LAB.

[0018] Figure 2f Another embodiment with multiple layers of PI tape is illustrated. In this case, PI tape 130a is adhered to the back side 128 of the semiconductor wafer 100. PI tape 130b is adhered to PI tape 130a to increase the total thickness to greater than 250 μm and provide additional structural support and stress relief.

[0019] Back to Figure 2e In an embodiment, the cutting tape 132 is applied to the PI tape 130, such as Figure 2g As shown in FIG. 1 , the cutting tape 132 is in direct physical contact with the PI tape 130. Figure 2h In the process, the assembly is inverted and the back grinding tape 120 is removed.

[0020] exist Figure 2i 1 , the semiconductor wafer 100 is singulated into a plurality of semiconductor dies 104 using a saw blade or other cutting tool 138. In particular, the cutting tool 138 singulates the semiconductor wafer 100 and the PI tape 130 while leaving the dicing tape 132 substantially intact. The semiconductor wafer 100 is singulated into a plurality of individual semiconductor dies 104, each covered by the PI tape 130 on the back side 128 and still attached to the dicing tape 132. The individual semiconductor dies 104 are designated as electrical components 140. In another embodiment, the electrical component 140 can be a semiconductor die, a semiconductor package, a surface mount device, a discrete electrical device, a discrete transistor, a diode, an IPD, or other electrical device.

[0021] exist Figure 2j In the embodiment of the present invention, the ejection tool 142 is pushed against the surface 144 of the dicing tape 132 to release the electrical components 140 from the dicing tape. Each electrical component 140 having the PI tape 130 disposed on the back side 128 is separated from the dicing tape 132. The individual electrical components 140 can be inspected and electrically tested for identification of post-singulation KGD.

[0022] Figure 2k A perspective view of PI tape 130 is shown in a regular rectangular shape that completely covers the back side 128 of semiconductor wafer 100. PI tape 130 may have other geometric shapes and patterns to optimize structural support and stress relief, such as Figure 2l The parallel stripes and Figure 2m An island of insulating material in the

[0023] exist Figure 2n , use pick and place operations to move objects from Figure 2j The individual electrical components 140 are positioned on an interconnect substrate 150. The interconnect substrate or PCB 150 includes a conductive layer 152 and an insulating layer 154. The conductive layer 152 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 152 provides horizontal electrical interconnections across the substrate 150 and vertical electrical interconnections between the top surface 156 and the bottom surface 158 of the substrate 150. Depending on the design and function of the electrical component 140, portions of the conductive layer 152 may be electrically common or electrically isolated. The insulating layer 154 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polymer, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer 154 provides isolation between the conductive layers 152. Figure 2oThe electrical components 140 are shown disposed on the surface 156 of the interconnect substrate 150 , with the bumps 114 making contact with the conductive layer 152 .

[0024] exist Figure 2p In the embodiment of the present invention, an electrical component 140 having a PI layer 130 on a back side 128 is subjected to a LAB process when disposed on a surface 156 of an interconnect substrate 150, wherein a laser 164 projects a laser shot 166 to mechanically and electrically bond a bump 114 of the electrical component 140 to a conductive layer 152 of the interconnect substrate 150. The laser shot 166 heats the bump 114 to a reflow state to mechanically and electrically bond the bump to the conductive layer 152. Alternatively, the electrical component 140 can be bonded to the interconnect substrate 150 again using LAB, with flux, non-conductive glue, non-conductive film, anisotropic conductive glue, etc. In particular, the PI tape 130 on the back side 128 provides heat resistance and high transmittance with little absorption of laser power. The PI tape 130 provides structural support to the electrical component 140 and significantly reduces warpage during the laser shot 166. LAB using the PI tape 130 can be completed while taking temperature measurements using an IR camera with little impact on manufacturing throughput. The PI tape 130 disposed on the back side 128 of the electrical component 140 prior to LAB significantly reduces stress and warpage on the electrical component when subjected to laser shots 166 during LAB. As discussed in the background, LAB utilizing the PI tape 130 has a greater units processed per hour (UPH) through manufacturing than that of cLAB.

[0025] exist Figure 2q In the embodiment, the PI tape 130 is removed from the back side 128 by heat, mechanical stripping, chemical stripping or other tape removal procedures. Figure 2r In the process, interconnect substrate 150 is singulated with a saw blade or other cutting tool 170, leaving individual semiconductor packages 172 having electrical components 140 and a portion of interconnect substrate 150. Electrical components 140 do not experience warping due to the use of PI tape 130 as structural support on the back side of the electrical components during LAB.

[0026] Figure 3 A semiconductor package 172 is illustrated having an electrical component 140 mounted to an interconnect substrate 150, wherein bumps 114 are bonded to a conductive layer 152 using LAB. The electrical component 140 does not experience warpage due to the use of PI tape 130 during LAB. The PI tape 130 disposed on the back side 128 of the electrical component 140 prior to LAB significantly reduces stress and warpage on the electrical component when subjected to laser firing 166 during LAB.

[0027] Figure 4An electronic device 400 is illustrated having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages, including semiconductor package 172, mounted on a surface of PCB 402. Electronic device 400 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0028] Electronic device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 400 may be a subcomponent of a larger system. For example, electronic device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, electronic device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. Semiconductor packages may include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and lightweighting are essential for making products accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0029] exist Figure 4 4, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on the surface or within layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

[0030] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, the semiconductor device may have only a first level packaging, in which the die is mechanically and electrically mounted directly to the PCB. For illustrative purposes, several types of first level packages are shown on the PCB 402, including a wire bond package 406 and a flip chip 408. In addition, several types of second level packages are shown mounted on the PCB 402, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or SIP module 418, a quad flat package (QFN) 420, a quad flat package 422, an embedded wafer level ball grid array (eWLB) 424, and a wafer level chip scale package (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured in any combination of first and second level packaging styles and other electronic components can be connected to the PCB 402. In some embodiments, the electronic device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and simplified manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, resulting in lower costs for consumers.

[0031] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Supply of electrical components; removing a portion of a surface of the electrical component to reduce a thickness of the electrical component; providing a first support tape on the remaining surface of the electrical component to provide strain relief; and A laser shot is projected onto the electrical component while retaining the first support tape disposed on a remaining surface of the electrical component to reduce warping of the electrical component during the laser shot. The method of claim 1 , wherein the electrical component is contained within a semiconductor wafer.

3. The method according to claim 2, further comprising: The semiconductor wafer is singulated to provide the electrical component with a first support tape disposed on a surface of the electrical component.

4. The method according to claim 1, further comprising: providing a substrate; disposing the electrical component on the substrate; as well as The laser emission is directed onto the electrical component to bond the electrical component to the substrate.

5. A semiconductor device comprising: a semiconductor wafer including a semiconductor die, wherein the thickness of the semiconductor die is reduced by removing a portion of a back side of the semiconductor wafer prior to singulation; a support tape disposed on a remaining surface of the semiconductor die opposite an active surface of the semiconductor die, wherein the support tape comprises a polyimide tape to provide stress relief; as well as The laser light projected onto the semiconductor die while retaining the support tape disposed on a remaining surface of the semiconductor die to provide stress relief and reduce warping of the semiconductor die during the laser light projecting. 6 . The semiconductor device of claim 5 , wherein the semiconductor die is contained within a semiconductor wafer. 7 . The semiconductor device of claim 6 , wherein the semiconductor wafer is singulated to provide the semiconductor dies with a support tape disposed on a back side of the semiconductor dies. 8 . The semiconductor device of claim 5 , further comprising a substrate, wherein the semiconductor die is disposed on the substrate, and the laser emission is projected onto the semiconductor die to bond the semiconductor die to the substrate. 9 . The semiconductor device according to claim 5 , further comprising a dicing tape disposed on the supporting tape.

10. A semiconductor device comprising: An electrical component, wherein a portion of a surface of the electrical component is removed to reduce a thickness of the electrical component; a support tape disposed on a remaining surface of the electrical component, wherein the support tape comprises a polyimide tape to reduce warping of the electrical component; and The laser emission projected onto the electrical component while retaining the support tape disposed on a remaining surface of the electrical component reduces warping of the electrical component during the laser emission. The semiconductor device according to claim 10 , wherein the electrical component is contained within a semiconductor wafer. 12 . The semiconductor device according to claim 11 , wherein the semiconductor wafer is singulated to provide the electrical component with a support tape provided on a surface of the electrical component.

13. The semiconductor device of claim 10, further comprising a substrate, wherein the electrical component is disposed on the substrate, and the laser emission is projected onto the electrical component to bond the electrical component to the substrate. 14 . The semiconductor device according to claim 10 , further comprising a dicing tape disposed on the supporting tape.

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