Method for manufacturing optoelectronic hybrid packaging structure and protective structural member

Abstract

The application discloses a manufacturing method and a protective structure of an optoelectronic hybrid packaging structure. The method comprises the following steps: providing a carrier plate and an optical chip, the optical chip being provided with at least one optical interface on one side; providing at least one electronic chip, which is arranged on the upper surface of the optical chip; providing at least one protective structure, which is in a cover shape and is internally provided with a cavity, and the surface of the protective structure is further provided with at least one through hole; the protective structure is attached to the upper surface of the optical chip in correspondence with the optical interface, so that the optical interface is completely located in the cavity; a flowable adhesive is provided, the adhesive is filled in the through hole, and the pressure outside the cavity is reduced; when the pressure outside the cavity is reduced, the gas in the cavity is discharged along the gap between the un-solidified adhesive and the through hole until the gas pressure in the cavity is in a low-pressure environment; then the adhesive is solidified, so that the adhesive completely blocks the through hole; and a plastic encapsulation body is formed. The cavity forms a closed low-pressure space, so as to meet the reliability requirements in the injection molding process and subsequent process operations.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a manufacturing method of an optoelectronic hybrid packaging structure and a protection structure. BACKGROUND

[0002] Hybrid packaging of optoelectronic chips has gradually become the mainstream of future development. The main role of optoelectronic packaging is to convert optical signals and electrical signals into each other, or to use optical chips for operation. The biggest difference compared with traditional electrical chip packaging is that the optical chip has an optical port for light import. The quality of the optical port directly affects the quality of optical coupling, and plays an important role in the efficiency of optical-electrical conversion, and the speed and accuracy of optical operation. However, because of the existence of the optical port in the optical chip, the SIP packaging (System In Package) form commonly used in traditional packaging is difficult to implement. Because the injection molding process used in SIP packaging will directly cover the optical port together with the optical chip, effective optical coupling / optical transmission cannot be achieved. Once the optoelectronic packaging cannot use SIP packaging, it will be at a disadvantage in terms of packaging product reliability, versatility and iterativeness, affecting the development of optoelectronic packaging in the future.

[0003] In the commonly used technology, an optical port protection structure is usually provided before injection molding, which is attached to the upper surface of the optical chip and forms a closed cavity with the upper surface of the optical chip, that is, the optical port is protected in the closed cavity, and then the injection molding process is performed. However, in wafer-level injection molding process, the environmental pressure needs to be reduced to the minimum value (hundred pascal order), if the pressure in the optical port protection structure (i.e. the closed cavity) is atmospheric pressure (ten thousand pascal order), the large pressure difference is easy to cause cracking failure and other problems in injection molding and subsequent high-temperature process. SUMMARY

[0004] The purpose of the present application is to provide a manufacturing method of an optoelectronic hybrid packaging structure and a protection structure to meet the requirements of injection molding process and subsequent process workability and reliability.

[0005] To achieve the above-mentioned purpose of the application, the present application provides a manufacturing method of an optoelectronic hybrid packaging structure, comprising the steps of:

[0006] providing a carrier plate and an optical chip, the optical chip being provided with at least one optical interface on one side, and the side of the optical chip with the optical interface being arranged on the upper surface of the carrier plate away from the carrier plate;

[0007] providing at least one electrical chip, and arranging the electrical chip on the upper surface of the optical chip and realizing electrical connection with the optical chip;

[0008] The application provides at least one protective structural member, which is a cover-shaped structure, and a cavity is formed in the cover-shaped structure. A surface of the protective structural member is further provided with at least one through hole, which is connected with the inner and outer surfaces of the protective structural member. The protective structural member is attached to the upper surface of the optical chip corresponding to the optical interface, so that the optical interface is completely located in the cavity.

[0009] A colloid with fluidity is provided, the colloid is filled in the through hole, and the environment outside the cavity is depressurized. When the pressure outside the cavity is reduced, the gas in the cavity is discharged along the gap between the un-solidified colloid and the through hole until the gas pressure in the cavity is in a low-pressure environment. Then, the colloid is solidified, so that the colloid completely blocks the through hole.

[0010] A plastic sealing material is provided, which covers the outer side surface of the protective structural member, the surface of the electronic chip and the upper surface of the optical chip which is not shielded, so as to form a plastic sealing body.

[0011] Further, the protective structural member is a cover-shaped structure, and a cavity is formed in the cover-shaped structure. A surface of the protective structural member is further provided with at least one through hole, which is connected with the inner and outer surfaces of the protective structural member. Specifically, the protective structural member comprises the following steps:

[0012] A groove is further formed in the top wall of the protective structural member, and the depth of the groove is half of the thickness of the top wall of the protective structural member.

[0013] The through hole is connected with the inner surface of the protective structural member and the bottom surface of the groove.

[0014] Further, the colloid with fluidity is provided, and the colloid is filled in the through hole. Specifically, the method comprises the following steps:

[0015] The size of the through hole is matched, and the amount of the colloid is controlled, so as to avoid that the un-solidified colloid flows into the cavity along the through hole.

[0016] The colloid is a bottom filling colloid with fluidity, and air can pass through the un-solidified colloid in a low-pressure environment.

[0017] Further, the environment outside the cavity is depressurized. In the process of depressurization, the gas in the cavity is discharged along the gap between the un-solidified colloid and the through hole until the gas pressure in the cavity is in a low-pressure environment. Then, the colloid is solidified, so that the colloid completely blocks the through hole. Specifically, the method comprises the following steps:

[0018] A vacuum baking equipment is provided, and the packaged carrier plate, optical chip, electronic chip and protective structural member are placed in the vacuum baking equipment.

[0019] The cavity outer environment is depressurized until the cavity inner and outer pressures are in equilibrium, and the non-solidified colloid blocks the through hole by backfilling;

[0020] The non-solidified colloid is solidified by heating, so that the solidified colloid completely blocks the through hole, and the solidified colloid is completely located inside the groove.

[0021] Further, the at least one electric chip is provided on the upper surface of the optical chip and electrically connected with the optical chip, specifically comprising:

[0022] A plurality of through silicon vias are formed in the optical chip, the functional surface of the electric chip is arranged towards the upper surface of the optical chip, and the electrical connection between the electric chip and the optical chip is realized through the through silicon vias.

[0023] Further, the method further comprises the steps of:

[0024] The optical chip is debonded from the carrier plate;

[0025] A redistribution layer is formed on the side of the optical chip which is not attached with the electric chip, and the electrical connection between the optical chip and the redistribution layer is realized through the through silicon vias.

[0026] Further, the method further comprises the steps of:

[0027] The plastic package is thinned until the top wall of the protective structural member is exposed;

[0028] The top wall of the protective structural member is thinned until the optical interface is completely exposed.

[0029] The application also provides a protective structural member for the manufacturing method of the optoelectronic hybrid package structure according to any one of the above embodiments, which is a cover-shaped structure, a cavity is arranged inside the cover-shaped structure, at least one through hole is arranged on the surface of the protective structural member, and the through hole communicates the inner and outer surfaces of the protective structural member; when the protective structural member is attached to the upper surface of the optical chip corresponding to the optical interface, the optical interface is completely located inside the cavity.

[0030] Further, a groove is arranged on the upper surface of the top wall of the protective structural member, and the through hole communicates the bottom surface of the groove and the inner surface of the protective structural member.

[0031] Further, the groove is arranged as a cylindrical structure, and the depth is arranged as half of the thickness of the top wall of the protective structural member.

[0032] The beneficial effect of the present application is that by setting a protection structure at the optical interface, and setting a through hole on the protection structure for filling the colloid with fluidity, it is convenient to reduce the air pressure in the cavity where the optical interface is located to a lower value, and then heat to solidify the colloid at the through hole to form a closed low-pressure space in the cavity, so as to prevent the problems such as crack failure caused by the air pressure in the formed cavity being too high during injection molding and subsequent high-temperature processing, so as to meet the reliability requirements in the injection molding process and subsequent processing operation. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 The flow chart of the manufacturing method of the optoelectronic hybrid packaging structure in an embodiment of the present application is shown.

[0034] Figures 2-9 The process step diagram corresponding to the manufacturing method of the optoelectronic hybrid packaging structure in an embodiment of the present application is shown.

[0035] Figure 10 The side view structure diagram of the protection structure in an embodiment of the present application is shown.

[0036] Figure 11 The top view structure diagram of the protection structure in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely in combination with the specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0038] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0039] For the convenience of description, the terms indicating spatial relative positions, such as "upper", "lower", "rear", "front", etc., are used for description herein, which are used to describe the relationship of one unit or feature relative to another unit or feature shown in the drawings. The terms indicating spatial relative positions can include different positions of the device in use or operation other than the positions shown in the drawings. For example, if the device in the drawings is turned over, the unit described as being "below" or "above" the other unit or feature will be "below" or "above" the other unit or feature. Therefore, the exemplary term "below" can include both the lower and upper spatial positions.

[0040] As shown in Figure 1 The present application provides a manufacturing method of an optoelectronic hybrid packaging structure, comprising the steps of:

[0041] S1: providing a carrier plate and an optical chip, the optical chip is provided with at least one optical interface on one side surface, and the side surface of the optical chip with the optical interface is arranged on the upper surface of the carrier plate.

[0042] S2: providing at least one electronic chip, and arranging the electronic chip on the upper surface of the optical chip and realizing electrical connection with the optical chip.

[0043] S3: providing at least one protective structural member, the protective structural member is a cover-shaped structure, a cavity is formed in the cover-shaped structure, and at least one through hole is further formed on the surface of the protective structural member, the through hole communicates the inner and outer surfaces of the protective structural member, and the protective structural member is attached to the upper surface of the optical chip corresponding to the optical interface, so that the optical interface is completely located in the cavity.

[0044] S4: providing a colloid with fluidity, filling the colloid at the through hole, and performing pressure reduction treatment on the environment outside the cavity, when the pressure outside the cavity is reduced, the gas in the cavity is discharged along the gap between the un-solidified colloid and the through hole, until the gas pressure in the cavity is in a low-pressure environment, and then the colloid is solidified, so that the colloid completely blocks the through hole.

[0045] S5: providing plastic sealing material, covering the outer side surface of the protective structural member, the surface of the electronic chip, and the upper surface of the optical chip which is not shielded, to form a plastic sealing body.

[0046] Corresponding to step S1, as shown in Figure 2 A carrier plate 1 and an optical chip 2 are provided. The carrier plate 1 can be a substrate, or a glass plate, or other flat plates with certain supporting force and smooth surface. Exemplarily, the optical chip 2 is provided with an optical interface 21 for light introduction on one side surface, a plurality of through silicon vias 22 are formed in the optical chip 2, the through silicon vias 22 connect the upper and lower surfaces of the optical chip 2, and the through silicon vias 22 are filled with conductive material.

[0047] Specifically, a layer of bonding glue is first coated on the upper surface of the carrier plate 1, and then the side of the optical chip 2 having the optical interface 21 is fixed to the upper surface of the carrier plate 1 away from the carrier plate 1. The present application does not limit the selection of the bonding glue, and a temporary bonding glue can be selected to facilitate the subsequent debonding process.

[0048] In step S2, at least one electronic chip 3 is provided, and the electronic chip 3 is arranged on the upper surface of the optical chip 2 and electrically connected with the optical chip 2, specifically including:

[0049] As shown in Figure 3 , for example, an electronic chip 3 is provided, which includes a functional surface having an electrical pad and a non-functional surface opposite to the functional surface. The functional surface of the electronic chip 3 is arranged towards the upper surface of the optical chip 2. Specifically, the electrical pad on the functional surface of the electronic chip 3 is arranged opposite to the through silicon via 22, that is, the electrical connection between the electronic chip 3 and the optical chip 2 is realized through the through silicon via 22.

[0050] Of course, in other embodiments of the present application, two or more electronic chips 3 can be provided to meet different requirements of products, and the present application does not limit this, which can be adjusted according to actual design needs.

[0051] Further, before step S3, the manufacturing method in the embodiment further includes a step of: attaching at least one passive element 4 on the upper surface of the optical chip 2.

[0052] Continuing to refer to Figure 3 , for example, one passive element 4 is attached on the upper surface of the optical chip 2. The passive element 4 can be a resistor, a capacitor or an inductor, and the present application does not limit the type and number of the passive element attached on the upper surface of the optical chip 2, which can be adjusted according to actual needs.

[0053] In step S3, at least one protective structural member 5 is provided, which is in the form of a cover, and a cavity 51 is formed inside the cover. The surface of the protective structural member 5 is further formed with at least one through hole 52, which communicates the inner and outer surfaces of the protective structural member 5, specifically including:

[0054] Referring to Figure 10 and Figure 11 , they are a side view structural schematic diagram and a top view structural schematic diagram of the protective structural member 5 in the embodiment. Specifically, the cover-shaped structure is a five-surface structure, and the lower surface of the protective structural member 5 is inwardly recessed to form the cavity 51, that is, the protective structural member 5 has a top wall surface and four side surfaces connected perpendicularly to the circumferential side of the top wall surface.

[0055] Of course, in other embodiments of the present application, the cover-shaped structure can also be a polyhedral structure or an arc surface structure, that is, the surface of the protection structure 5 is an arc surface, as long as the cavity 51 is formed inside the protection structure 5, and the surface of the cavity 51 can completely cover the optical interface 21 and the side wall surface of the protection structure 5 does not contact the optical interface 21.

[0056] The present application does not limit the depth of the cavity 51, and the depth of the cavity 51 can be designed according to actual needs (i.e. the target thickness to be thinned in the subsequent thinning process).

[0057] Further, a groove 53 is formed on the top wall surface of the protection structure 5, and the groove 53 is used to accommodate the excess glue material filled in the through hole 52, so as to prevent the glue material from overflowing to the top wall surface of the protection structure 5 and affecting the subsequent injection mold pressing.

[0058] Specifically, the depth of the groove 53 is half of the thickness of the top wall of the protection structure 5, and the internal region of the groove 53 is specifically a cylindrical structure, which can make the glue material fill completely.

[0059] Of course, the depth of the groove 53 and the specific structure and size of the internal region thereof can be adjusted according to actual needs and process equipment.

[0060] More specifically, the through hole 52 communicates the inner surface of the protection structure 5 and the bottom surface of the groove 53, so as to ensure that the excess glue material filled in the through hole 52 can flow into the groove 53.

[0061] Of course, in other embodiments, the top wall of the protection structure 5 can be provided with a plurality of through holes 52, and each through hole 52 communicates the inner surface of the protection structure 5 and the bottom surface of the groove 53. The present application does not limit the number of through holes 52, and the number can be designed and adjusted according to actual needs.

[0062] The diameter of the through hole 52 can be determined according to the type of glue provided and the vacuum requirement in the subsequent process.

[0063] The material of the protection structure 5 can be silicon, glass, epoxy resin material or other high-temperature resistant materials, and the present application does not limit this.

[0064] Referring to Figure 4 , the protection structure 5 with the cavity 51 is provided, and the side of the protection structure 5 with the cavity 51 is directed towards the optical interface 21 and is fixedly attached to the upper surface of the optical chip 2 corresponding to the optical interface 21, so that the optical interface 21 is completely located in the cavity 51.

[0065] In step S4, a glue 6 with fluidity is provided, and the glue 6 is filled in the through hole 52, specifically including:

[0066] Referring to Figure 5 , the size of the through hole 52, the amount of the glue 6 is controlled, and the glue 6 is filled at the through hole 52 to avoid the un-solidified glue 6 from flowing into the cavity 51 along the through hole 52. At the same time, the amount of the glue 6 is controlled, so that the glue 6 can be completely backfilled to block the through hole 52 in the subsequent process, and the glue 6 will not exceed the upper surface of the groove 53 after the solidification process.

[0067] Specifically, the glue 6 is a flowable underfill glue, and air can pass through the glue 6 under low pressure.

[0068] Of course, in other embodiments of the present application, the glue 6 can also be selected as other glue materials with moderate viscosity, flowability and low solidification temperature.

[0069] At this time, Figure 5 The internal pressure of the cavity 51 in the through hole 52 is atmospheric pressure, and air can flow in the gap between the un-solidified glue 6 and the through hole 52 and in the glue 6.

[0070] In step S4, the environment outside the cavity 51 is depressurized, and in the process of depressurization, the gas in the cavity 51 is discharged along the gap between the un-solidified glue 6 and the through hole 52 until the gas pressure in the cavity 51 is in a low pressure environment, and then the glue 6 is solidified to completely block the through hole 52, which specifically includes:

[0071] A vacuum baking equipment is provided, and the packaged carrier 1, the optical chip 2, the electronic chip 3 and the protection structure 5 are placed in the vacuum baking equipment, that is, the packaging structure in the through hole 52 is placed in the vacuum baking equipment. Figure 5 The packaging structure in the through hole 52 is placed in the vacuum baking equipment.

[0072] The vacuum baking equipment is started, a target vacuum degree is set, the environment outside the cavity 51 is depressurized, and the internal and external pressures of the cavity 51 are balanced, that is, the internal and external pressures of the cavity 51 are reduced to the target vacuum degree, and the un-solidified glue 6 blocks the through hole 52 by backfilling. Specifically, as the pressure of the environment outside the cavity 51 decreases, the gas in the cavity 51 can be discharged along the gap between the un-solidified glue 6 and the through hole 52 and through the un-solidified glue 6; the internal and external pressures of the cavity 51 are reduced at the same time; the environment outside the cavity 51 is continuously depressurized until the internal and external pressures of the cavity 51 are balanced, that is, the pressure in the cavity 51 is reduced to the target vacuum degree, such as hundreds of pascals, and at this time the un-solidified glue 6 can block the through hole 52 by backfilling.

[0073] Further, the temperature in the vacuum baking equipment is increased to solidify the un-solidified glue 6, so that the solidified glue 6 completely blocks the through hole 52, the cavity 51 is a closed space, and the solidified glue 6 is completely located in the groove 53.

[0074] Further, the encapsulation structure after the colloid 6 is solidified is taken out from the vacuum baking equipment, the pressure outside the cavity 51 is increased to the atmospheric pressure, and the low-pressure space is formed inside the cavity 51. Referring to Figure 6 At this time, the cavity 51 is a closed low-pressure space.

[0075] The present application does not limit the specific pressure value of the low-pressure space formed by the cavity 51, and the process parameters can be adjusted according to the actual manufacturing process, so that the space pressure in the cavity 51 is kept at a low level, and the reliability of the subsequent formed plastic package is not affected.

[0076] Referring to Figure 7 The plastic encapsulation material is provided to cover the outer side surface of the protection structural part 5, the surface of the electric chip 3, and the upper surface of the optical chip 2 which is not shielded, to form a plastic package 7. The plastic package 7 takes epoxy resin as the base body, and adds additives such as curing agent and coupling agent, which plays a role of mechanical support and sealing protection for the encapsulation structure.

[0077] Further, the manufacturing method in the embodiment further includes the following steps:

[0078] S6: The optical chip 2 is unbonded from the carrier board 1.

[0079] S7: A redistribution layer 8 is formed on the side of the optical chip 2 which is not attached with the electric chip 3, and the electrical connection between the optical chip 2 and the redistribution layer 8 is realized through the through silicon via 22.

[0080] Referring to Figure 8 After the optical chip 2 is unbonded from the carrier board 1, the redistribution layer 8 is formed on the side of the optical chip 2 which is not attached with the electric chip 3, and the electrical connection between the optical chip 2 and the redistribution layer 8 is realized through the through silicon via 22.

[0081] Further, the metal solder ball 9 is also formed at the conductive solder pad at the bottom surface of the redistribution layer 8, which is used for welding with the external circuit board.

[0082] The manufacturing process of the optical chip 2 being unbonded from the carrier board 1, the redistribution layer 8, and the metal solder ball 9 is the prior art, and the present application will not be described in more detail.

[0083] S8: The plastic package 7 is thinned until the top wall of the protection structural part 5 is exposed.

[0084] S9: The top wall of the protection structural part 5 is thinned until the optical interface 21 is completely exposed.

[0085] Referring to Figure 9 The plastic package 7 can be thinned by using the grinding process or the laser process. After the top wall of the protection structural part 5 is exposed, the thinning process is continued on the plane until the optical interface 21 is completely exposed, which will not affect the quality of the optical port coupling at the optical interface 21.

[0086] The application also provides a protective structure 5 used in the manufacturing method of the optoelectronic hybrid packaging structure.

[0087] Referring to Figure 10 and Figure 11 , the protective structure 5 is a cover-shaped structure, and a cavity 51 is arranged in the cover-shaped structure. At least one through hole 52 is arranged on the surface of the protective structure 5, and the through hole 52 communicates the inner and outer surfaces of the protective structure 5. When the protective structure 5 is attached to the upper surface of the optical chip 2 corresponding to the optical interface 21, the optical interface 21 is completely located in the cavity 51.

[0088] Specifically, the cover-shaped structure is a five-faced structure, and the lower surface of the protective structure 5 is inwardly recessed to form the cavity 51, that is, the protective structure 5 has a top wall surface and four side surfaces connected to the circumferential side of the top wall surface.

[0089] Of course, in other embodiments of the application, the cover-shaped structure can also be a polyhedral structure or an arc surface structure, that is, the surface of the protective structure 5 is a circular arc surface, as long as the cavity 51 is formed in the protective structure 5, and the surface of the cavity 51 can completely cover the optical interface 21 and the side wall surface of the protective structure 5 does not contact the optical interface 21.

[0090] The application sets the depth of the cavity 51 to be at least higher than the thickness of the electrical chip 3 and the passive element 4. Specifically, the forming depth of the cavity 51 can be designed according to actual needs (that is, the target thickness to be thinned in the subsequent thinning process).

[0091] Further, a groove 53 is arranged on the top surface of the top wall of the protective structure 5, and the groove 53 is used to accommodate the excess glue material filled in the through hole 52, so as to prevent the glue material from overflowing to the top surface of the top wall of the protective structure 5 and affecting the subsequent injection mold pressing.

[0092] Specifically, the setting depth of the groove 53 is half of the thickness of the top wall of the protective structure 5, and the inner region of the groove 53 is specifically arranged as a cylindrical structure, which can make the glue material filled completely.

[0093] Of course, the setting depth of the groove 53 and the specific structure and size of the inner region thereof can be adjusted according to actual needs and process equipment.

[0094] More specifically, the through hole 52 communicates the inner surface of the protective structure 5 and the bottom surface of the groove 53, so as to ensure that the excess glue material filled in the through hole 52 can flow into the groove 53.

[0095] Of course, in other embodiments, the top wall of the protection structure 5 can be provided with a plurality of through holes 52, each of which is in communication with the inner surface of the protection structure 5 and the bottom surface of the groove 53, and the present application does not limit the number of through holes 52, which can be designed and adjusted according to actual needs.

[0096] The diameter of the through hole 52 can be determined according to the type of colloid provided and the vacuum requirement in the subsequent process.

[0097] The material of the protection structure 5 can be silicon, glass, epoxy resin material or other high-temperature resistant materials, and the present application does not limit this.

[0098] In summary, the present application provides a protection structure at the optical interface, and a through hole is provided on the protection structure for filling a colloid with fluidity. After the air pressure in the cavity where the optical interface is located is reduced to a lower value in the subsequent process, the colloid in the through hole is solidified by heating to form a sealed low-pressure space in the cavity, preventing the air pressure in the formed cavity from being too high to cause cracking failure in injection molding and subsequent high-temperature processes, and meeting the reliability requirements in injection molding processes and subsequent process operations.

[0099] It should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that can be understood by those skilled in the art.

[0100] The above series of detailed descriptions are only specific descriptions of the feasible embodiments of the present application, and are not intended to limit the protection scope of the present application. Any equivalent embodiments or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A method for fabricating a photoelectric hybrid packaging structure, characterized in that, Including the following steps: A carrier board and an optical chip are provided. The optical chip has at least one optical interface on one side. The side of the optical chip with the optical interface is disposed on the upper surface of the carrier board, facing away from the carrier board. At least one electrical chip is provided, which is disposed on the upper surface of the optical chip and electrically connected to the optical chip; At least one protective structural member is provided, the protective structural member is a cover-shaped structure, a cavity is formed inside the cover-shaped structure, at least one through hole is formed on the surface of the protective structural member, the through hole connects the inner and outer surfaces of the protective structural member, and a groove is formed on the upper surface of the top wall of the protective structural member, the through hole connects the inner surface of the protective structural member and the bottom surface of the groove; The protective structure is attached to the upper surface of the optical chip corresponding to the optical interface, so that the optical interface is completely located in the cavity; A flowable colloid is provided and filled into the through hole. The external environment of the cavity is depressurized. When the external pressure of the cavity decreases, the gas in the cavity is discharged through the gap between the unsolidified colloid and the through hole until the gas pressure in the cavity is in a low-pressure environment. Then, the colloid is solidified so that the colloid completely blocks the through hole and the solidified colloid is completely located inside the groove, and the solidified colloid does not exceed the upper surface of the groove. A molding compound is provided, and the molding compound is used to cover the outer side of the protective structure, the surface of the electrical chip, and the unshielded upper surface of the optical chip to form a molding compound; Thin the encapsulation until the top wall of the protective structure is exposed; Thin the top wall of the protective structure until the optical interface is fully exposed.

2. The method for fabricating the optoelectronic hybrid packaging structure according to claim 1, characterized in that, The provision includes at least one protective structural member, the protective structural member being a cover-like structure, the cover-like structure having an internal cavity, and the surface of the protective structural member further having at least one through hole connecting the inner and outer surfaces of the protective structural member, specifically including: The groove is formed to a depth equal to half the thickness of the top wall of the protective structure.

3. The method for fabricating the optoelectronic hybrid packaging structure according to claim 2, characterized in that, The provision of a flowable colloid, and the filling of the through-hole with the colloid, specifically includes: The amount of colloid used is controlled according to the size of the through hole to prevent the uncured colloid from flowing into the cavity along the through hole; The colloid is a fluid underfill colloid, and air can pass through the uncured colloid under low pressure.

4. The method for fabricating the optoelectronic hybrid packaging structure according to claim 3, characterized in that, The process of depressurizing the external environment of the cavity involves the gas inside the cavity escaping through the gap between the unsolidified colloid and the through-hole until the gas pressure inside the cavity reaches a low-pressure environment, at which point the colloid solidifies, completely blocking the through-hole. Specifically, this includes: A vacuum baking device is provided, in which the packaged carrier board, optical chip, electrical chip and protective structure are placed; The external environment of the cavity is depressurized until the internal and external pressures of the cavity are in equilibrium, and the unsolidified colloid is used to plug the through hole by backfilling. The temperature is increased to solidify the uncured colloid, so that the solidified colloid completely blocks the through hole and is completely located inside the groove.

5. The method for fabricating the optoelectronic hybrid packaging structure according to claim 4, characterized in that, The provision of at least one electrical chip, wherein the electrical chip is disposed on the upper surface of the optical chip and electrically connected to the optical chip, specifically includes: The optical chip has multiple through-silicon vias (TSVs) formed inside it, with the functional surface of the electrical chip facing the upper surface of the optical chip. The electrical connection between the electrical chip and the optical chip is achieved through the TSVs.

6. The method for fabricating the optoelectronic hybrid packaging structure according to claim 5, characterized in that, The method further includes the following steps: Debond the optical chip to the carrier board; A redistribution layer is formed on the side of the optical chip where the electrical chip is not attached, and an electrical connection between the optical chip and the redistribution layer is achieved through the through-silicon via.

7. The method for fabricating the optoelectronic hybrid packaging structure according to claim 1, characterized in that, The groove is configured as a cylindrical structure, and its depth is set to half the thickness of the top wall of the protective structure.

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