Floating rail circuit, half-bridge drive circuit and driving method

Abstract

This invention discloses a floating rail circuit, a half-bridge driving circuit, and a driving method. The floating rail circuit is used to power a gate driver and includes: a first MOSFET, the drain and source of which are connected to a first potential and a floating potential, respectively, and the gate connected to a clamping node; a third resistor R3, electrically connected between the floating potential and the second potential; and a current source, electrically connected between the first potential and the clamping node, wherein the voltage across the current source is a reference voltage V. REF The internal resistance is a first resistor R1; a second resistor R2 and a second MOS transistor are electrically connected between the clamping node and the second node; wherein, the first MOS transistor and the second MOS transistor are both PMOS transistors or NMOS transistors, and the floating rail voltage between the second potential and the floating potential is the power supply voltage of the gate driver. The floating rail circuit of the present invention can provide a constant floating rail voltage that does not change with variations in process, voltage, and temperature.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-voltage half-bridge driving circuits, and particularly relates to a floating rail circuit, a half-bridge driving circuit and a driving method. BACKGROUND

[0002] In the field of analog devices and power devices, for example, in the application of DCDC, motor driving, etc., the application of a half-bridge driving circuit is involved. The half-bridge driving circuit is divided into a high-voltage side and a low-voltage side. The high-voltage side and the low-voltage side generate V High_side and V Low_side respectively through a floating rail circuit, and supply power to a high-voltage side gate driver and a low-voltage side gate driver respectively. The high-voltage side gate driver and the low-voltage side gate driver drive a high-voltage side power tube and a low-voltage side power tube respectively.

[0003] Referring to Figure 1 This is a schematic diagram of a high-voltage side floating rail circuit in the prior art. In this scheme, a Zener diode D1 is used to clamp the floating rail voltage V High_side , and finally V High_side = V zener -V GS , wherein V zener is the anode voltage of the Zener diode D1, and V GS is the gate-source voltage of the PMOS tube HV_PMOS.

[0004] Referring to Figure 2 This is another schematic diagram of a high-voltage side floating rail circuit in the prior art. In this scheme, a current source I1 is used to clamp the floating rail voltage V High_side , and the voltage across the current source is a reference voltage V REF , and the internal resistance is a first resistor R1. Finally, V High_side = PVCC-V FLOAT = PVCC-(V CLAMP + V GS ) = PVCC-(PVCC-(V REF / R1)*R2+V GS ) = (R2 / R1)*V REF -V GS , wherein V GS is the gate-source voltage of the PMOS tube HV_PMOS.

[0005] Since V GS is a process-dependent voltage that changes with PVT (process, voltage, and temperature), the floating rail voltage V High_side in the above two schemes will change with PVT, and cannot provide a constant floating rail voltage for the gate driver.

[0006] Therefore, in order to solve the above technical problems, it is necessary to provide a floating rail circuit, a half-bridge driving circuit and a driving method. SUMMARY

[0007] Therefore, in order to solve the above technical problems, it is necessary to provide a floating rail circuit, a half-bridge driving circuit and a driving method.

[0008] In order to achieve the above-mentioned purpose, the technical scheme provided by an embodiment of the present application is as follows:

[0009] A floating rail circuit for powering a gate driver, the floating rail circuit comprising:

[0010] A first MOS transistor, a drain and a source of the first MOS transistor being connected to a first potential and a floating potential respectively, and a gate being connected to a clamping node;

[0011] A third resistor R3 being electrically connected between the floating potential and a second potential;

[0012] A current source being electrically connected between the first potential and the clamping node, a voltage across the current source being a reference voltage V REF , and an internal resistance being a first resistor R1;

[0013] A second resistor R2 and a second MOS transistor being electrically connected between the clamping node and a second node;

[0014] Wherein, the first MOS transistor and the second MOS transistor are both PMOS transistors or NMOS transistors, and a floating rail voltage between the second potential and the floating potential is a power supply voltage of the gate driver.

[0015] In an embodiment, a gate and a drain of the second MOS transistor are short-circuited, a source is connected to the second potential, and the second resistor R2 is electrically connected between the drain of the second MOS transistor and the clamping node; or,

[0016] The gate and the drain of the second MOS transistor are short-circuited and connected to the clamping node, and the second resistor R2 is electrically connected between the source of the second MOS transistor and the second potential.

[0017] In an embodiment, when the floating rail circuit is used to power a high-voltage side gate driver, the first potential is a ground potential, the second potential is a power supply voltage, and the first MOS transistor and the second MOS transistor are both PMOS transistors.

[0018] In an embodiment, a floating rail voltage V High_side between the power supply voltage and the floating potential is a power supply voltage of the high-voltage side gate driver, and V High_side = K*V REF , wherein K = R2 / R1.

[0019] In one embodiment, when the floating rail circuit supplies power for the low-voltage side gate driver, the first potential is a power supply voltage, the second potential is a ground potential, and the first MOS transistor and the second MOS transistor are both NMOS transistors.

[0020] In one embodiment, the floating rail voltage V Low_side is a power supply voltage for the low-voltage side gate driver, and V Low_side = K*V REF , where K = R2 / R1.

[0021] In one embodiment, the floating rail circuit further comprises a capacitor C electrically connected between the floating potential and the second potential.

[0022] Another embodiment of the present application provides the technical solution as follows:

[0023] A half-bridge driving circuit for driving power transistors, the half-bridge driving circuit comprising:

[0024] a first floating rail circuit for providing a first floating rail voltage V High_side for power supply of a high-voltage side gate driver, the high-voltage side gate driver being configured to drive high-voltage side power transistors;

[0025] a second floating rail circuit for providing a second floating rail voltage V Low_side for power supply of a low-voltage side gate driver, the low-voltage side gate driver being configured to drive low-voltage side power transistors;

[0026] The first floating rail circuit is the floating rail circuit described above, and / or the second floating rail circuit is the floating rail circuit described above.

[0027] In one embodiment, the first floating rail circuit further comprises a third MOS transistor, the third MOS transistor being an NMOS transistor, the source of the third MOS transistor being connected to the ground potential, the drain of the third MOS transistor being connected to the floating potential, and the third MOS transistor being turned on when the power supply voltage is less than a preset voltage threshold, so as to pull down the floating potential to the ground potential.

[0028] In one embodiment, the second floating rail circuit further comprises a fourth MOS transistor, the fourth MOS transistor being a PMOS transistor, the source of the fourth MOS transistor being connected to the power supply voltage, the drain of the fourth MOS transistor being connected to the floating potential, and the fourth MOS transistor being turned on when the power supply voltage is less than a preset voltage threshold, so as to pull up the floating potential to the power supply voltage.

[0029] Still another embodiment of the present application provides the technical solution as follows:

[0030] A driving method applied to the half-bridge driving circuit, the driving method comprising:

[0031] a first floating rail voltage V High_side Power supply for high-voltage side gate driver and drive high-voltage side power tube;

[0032] Compare the size of the power supply voltage and the preset voltage threshold, when the power supply voltage is less than the preset voltage threshold, drive the third MOS tube to turn on to pull down the floating potential to ground potential; when the power supply voltage is greater than or equal to the preset voltage threshold, the third MOS tube is cut off.

[0033] The technical scheme provided by another embodiment of the present application is as follows:

[0034] A driving method applied to the half-bridge driving circuit, the driving method comprises:

[0035] a second floating rail voltage V Low_side Power supply for low-voltage side gate driver and drive low-voltage side power tube;

[0036] Compare the size of the power supply voltage and the preset voltage threshold, when the power supply voltage is less than the preset voltage threshold, drive the fourth MOS tube to turn on to pull up the floating potential to the power supply voltage; when the power supply voltage is greater than or equal to the preset voltage threshold, the fourth MOS tube is cut off.

[0037] The present application has the following beneficial effects:

[0038] The floating rail circuit of the present application can provide a constant floating rail voltage, which does not change with process, voltage and temperature;

[0039] The high-voltage side and the low-voltage side of the half-bridge driving circuit are powered by floating rail circuits, which can ensure the voltage balance of the high-voltage side and the low-voltage side; at the same time, when the power supply voltage is low, the floating rail voltage can be switched to the maximum power supply voltage to ensure sufficient headroom. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.

[0041] Figure 1 is a schematic diagram of a high-voltage side floating rail circuit in the prior art;

[0042] Figure 2 is a schematic diagram of a high-voltage side floating rail circuit in another prior art;

[0043] Figure 3 Fig. 1 is a schematic diagram of a high-voltage side floating rail circuit in an embodiment of the present application;

[0044] Figure 4 Fig. 2 is a schematic diagram of a low-voltage side floating rail circuit in an embodiment of the present application;

[0045] Figure 5 Fig. 3 is a schematic diagram of a half-bridge driving circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the person skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should fall within the protection scope of the present application.

[0047] The present application discloses a floating rail circuit for powering a gate driver, which comprises:

[0048] a first MOS transistor, whose drain and source are connected to a first potential and a floating potential respectively, and whose gate is connected to a clamping node;

[0049] a third resistor R3, which is electrically connected between the floating potential and a second potential;

[0050] a current source, which is electrically connected between the first potential and the clamping node, and whose voltage is a reference voltage V REF , and whose internal resistance is a first resistor R1;

[0051] a second resistor R2 and a second MOS transistor, which are electrically connected between the clamping node and a second node;

[0052] wherein the first MOS transistor and the second MOS transistor are both PMOS transistors or NMOS transistors, and the floating rail voltage between the second potential and the floating potential is the power supply voltage of the gate driver.

[0053] The present application also discloses a half-bridge driving circuit for driving a power transistor, which comprises:

[0054] a first floating rail circuit and a high-voltage side gate driver, the first floating rail circuit being used to provide a first floating rail voltage V High_side for powering the high-voltage side gate driver, and the high-voltage side gate driver being used to drive a high-voltage side power transistor;

[0055] a second floating rail circuit and a low-voltage side gate driver, the second floating rail circuit being used to provide a second floating rail voltage VLow_side Power the low - voltage side gate driver, which is used to drive the low - voltage side power transistor;

[0056] The first floating rail circuit is the above - mentioned floating rail circuit, and / or the second floating rail circuit is the above - mentioned floating rail circuit.

[0057] The following further illustrates the present invention with specific embodiments.

[0058] Embodiment 1:

[0059] Refer Figure 3 As shown, the floating rail circuit in this embodiment is used to power the high - voltage side gate driver U1, and it includes:

[0060] The first MOS transistor HV_PMOS1, the drain and source of the first MOS transistor HV_PMOS1 are respectively connected to the ground potential and the floating potential V FLOAT and the gate is connected to the clamping node V CLAMP ;

[0061] The third resistor R3 is electrically connected between the floating potential V FLOAT and the power supply voltage PVCC;

[0062] The current source I2 is electrically connected between the ground potential and the clamping node V CLAMP , the voltage across the current source I2 is the reference voltage V REF , and the internal resistance is the first resistor R1;

[0063] The second resistor R2 and the second MOS transistor are electrically connected between the clamping node V CLAMP and the power supply voltage PVCC, and the second MOS transistor is the PMOS transistor HV_PMOS2.

[0064] Further, the floating rail circuit further includes a capacitor C, and the capacitor C is electrically connected between the floating potential V FLOAT and the power supply voltage PVCC.

[0065] Specifically, in this embodiment, the gate and drain of the second MOS transistor HV_PMOS2 are short - circuited, the source is connected to the power supply voltage PVCC, and the second resistor R2 is electrically connected between the drain of the PMOS transistor HV_PMOS2 and the clamping node V CLAMP ;

[0066] When applied to the high - voltage side, both the first MOS transistor and the second MOS transistor are PMOS transistors, and the gate - source voltage thresholds of the two PMOS transistors are the same.

[0067] In this embodiment, a second MOS transistor HV_PMOS2 is introduced between the second resistor R2 and the power supply voltage PVCC. By introducing this PMOS transistor, the floating rail voltage V can be eliminatedHigh_side Variation with respect to V caused by PVT parameters GS Variation

[0068] Wherein:

[0069] V CLAMP = PVCC - V GS - (R2 / R1) * V REF ;

[0070] V FLOAT = V CLAMP + V[[ID=二十三]] GS = PVCC - (R2 / R1) * V REF = PVCC - V GS - K * V REF ;

[0071] Therefore, V High_side = PVCC - V FLOAT = K * V REF , where K = R2 / R1

[0072] In this embodiment, K is the resistance ratio value of the second resistor R2 to the first resistor R1, and the reference voltage V REF is the voltage across the current source I2, and both of these values do not change with the change of PVT parameters

[0073] Exemplarily, since the breakdown voltage of the first MOS transistor HV_PMOS1 is typically around 5V, and the high-side gate driver usually requires a voltage of more than 5V for power supply. Without the floating rail circuit, it will cause the breakdown of HV_PMOS1 GS When the high-side gate driver operates at a voltage higher than the breakdown voltage of V

[0074] In this embodiment, by setting the value of K, a floating rail voltage V GS lower than 5V generated by the floating rail circuit can be obtained, so as to avoid the breakdown of the first MOS transistor High_side CLAMP

[0075] It should be understood that the position of the second MOS transistor HV_PMOS2 introduced in this embodiment is not limited to the position in Figure 3 . It can also be set at other positions. For example, after the gate and drain of the second MOS transistor HV_PMOS2 are short-circuited and connected to the clamping node V CLAMP , and the second resistor R2 is electrically connected between the source of the second MOS transistor HV_PMOS2 and the power supply voltage PVCC, the same technical effect can be achieved

[0076] Embodiment 2:

[0077] Refer Figure 4As shown, the floating rail circuit in the embodiment is used to supply power for the low-voltage side gate driver U2, which includes:

[0078] The first MOS tube HV_NMOS1 has its drain and source connected to the power supply voltage PVCC and the floating potential V FLOAT , respectively, and its gate connected to the clamping node V CLAMP .

[0079] The third resistor R3' is electrically connected between the floating potential V FLOAT and the ground potential.

[0080] The current source I3 is electrically connected between the power supply voltage PVCC and the clamping node V CLAMP , and has a voltage of the reference voltage V REF ' across its terminals and a resistance of the first resistor R1'.

[0081] The second resistor R2' and the second MOS tube are electrically connected between the clamping node V CLAMP and the ground potential, and the second MOS tube is an NMOS tube HV_NMOS2.

[0082] Further, the floating rail circuit further includes a capacitor C' electrically connected between the floating potential V FLOAT and the ground potential.

[0083] Specifically, the gate and the drain of the second MOS tube HV_NMOS2 in the embodiment are short-circuited, the source is connected to the ground potential, and the second resistor R2' is electrically connected between the drain of the NMOS tube HV_NMOS2 and the clamping node V CLAMP .

[0084] When applied to the low-voltage side, the first MOS tube and the second MOS tube are both NMOS tubes, and the gate-source voltage threshold values of the two NMOS tubes are the same.

[0085] In the embodiment, the second MOS tube HV_NMOS2 is introduced between the second resistor R2' and the ground potential, and the introduction of the NMOS tube can eliminate the V Low_side variation of the floating rail voltage V GS caused by PVT parameters.

[0086] Similarly to Embodiment 1, the floating rail voltage in the embodiment is:

[0087] V Low_side = PVCC - V FLOAT = K*V REF ', where K = R2' / R1'.

[0088] In this embodiment, K is the resistance ratio value of the second resistor R2' to the first resistor R1', and the reference voltage V REF ' is the voltage across the current source I3, and both of these values do not change with the variation of PVT parameters.

[0089] Exemplarily, since the breakdown voltage of the first MOS transistor HV_NMOS1 is typically around 5V, and the low-side gate driver usually requires a voltage of more than 5V for power supply. Without a floating rail circuit, it will cause the breakdown of HV_NMOS1. GS When the low-side gate driver operates at a voltage higher than the

[0090] breakdown voltage in this embodiment, by setting the value of K, a floating rail voltage V GS lower than 5V can be generated through the floating rail circuit, Low_side thus avoiding the breakdown of the first MOS transistor.

[0091] It should be understood that the position of the second MOS transistor HV_NMOS2 introduced in this embodiment is not limited to the Figure 4 position in CLAMP , and it can also be set at other positions. For example, after the gate and drain of the second MOS transistor HV_NMOS2 are short-circuited and connected to the clamping node V

[0092] Embodiment 3:

[0093] Refer Figure 5 as shown, a half-bridge drive circuit is disclosed in this embodiment. The half-bridge drive circuit includes:

[0094] A first floating rail circuit 11 and a high-side gate driver 12. The first floating rail circuit 11 is used to provide a first floating rail voltage V High_side to supply power to the high-side gate driver 12, and the high-side gate driver 12 is used to drive the high-side power transistor M1;

[0095] A second floating rail circuit 21 and a low-side gate driver 22. The second floating rail circuit 21 is used to provide a second floating rail voltage V Low_side to supply power to the low-side gate driver 22, and the low-side gate driver 22 is used to drive the low-side power transistor M2.

[0096] Among them, the first floating rail circuit 11 is substantially the same as the floating rail circuit in Embodiment 1. The difference is that the first floating rail circuit 11 in this embodiment further includes a third MOS transistor NM3. The third MOS transistor is an NMOS transistor, the source is connected to the ground potential, and the drain is connected to the floating potential V FLOATconnected, the third MOS tube is turned on when the power voltage is less than a preset voltage threshold, so as to pull the floating potential V FLOAT to ground potential.

[0097] Similarly, the second floating rail circuit 21 is substantially the same as the floating rail circuit in Embodiment 2, except that the second floating rail circuit 21 in the embodiment further comprises a fourth MOS tube PM4, which is a PMOS tube, the source is connected with the power voltage PVCC, the drain is connected with the floating potential V FLOAT , and the fourth MOS tube is turned on when the power voltage is less than a preset voltage threshold, so as to pull the floating potential V FLOAT to the power voltage PVCC.

[0098] In the prior art, the low-voltage side of the half-bridge driving circuit can be powered by an internal low-voltage LDO, which will cause the following problems:

[0099] 1. The internal LDO does not have enough driving capability due to the limited internal capacitor area;

[0100] 2. The internal LDO also powers the analog circuit, and if it also powers the driver, the backflush noise will have a significant impact on the analog circuit;

[0101] 3. If the low-voltage end is powered by an internal LDO, the matching between the power voltages of the low-voltage side and the high-voltage side is large and varies with PVT, so it will cause the imbalance between the propagation and dead time of the drivers on the high-voltage side and the low-voltage side, thereby affecting the efficiency.

[0102] To solve the above problems, in the embodiment, the above floating rail circuit is used for power supply on the high-voltage side and the low-voltage side, and through the setting of the resistance value, the floating rail voltage V High_side of the high-voltage side is the same as the floating rail voltage V Low_side of the low-voltage side, so that voltage balance can be achieved.

[0103] In addition, the floating rail voltage should be lower than the power voltage of the chip, but in the case where the power voltage of the chip is very low, the floating rail voltage will be lower, which will cause the propagation delay of the driver. In addition, due to the lack of headroom, the low-voltage side floating rail circuit cannot work normally.

[0104] To solve the above problems, the third MOS tube NM3 and the fourth MOS tube PM4 are added in the embodiment, which will switch the floating rail voltage to the maximum power voltage when the power voltage is lower than a preset voltage threshold.

[0105] Specifically, on the high-voltage side of the half-bridge driving circuit, the driving method of the high-voltage side gate driver is as follows:

[0106] The power voltage PVCC in the first floating rail circuit is connected with the floating potential VFLOAT a first floating rail voltage V High_side is used to power the high-voltage side gate driver and drive the high-voltage side power tube M1.

[0107] The power supply voltage PVCC is compared with a preset voltage threshold VCC_UVLO, when the power supply voltage PVCC is less than the preset voltage threshold VCC_UVLO, the third MOS tube NM3 is driven to be turned on to pull up the floating potential V FLOAT to the ground potential; when the power supply voltage PVCC is greater than or equal to the preset voltage threshold V FLOAT , the third MOS tube NM3 is turned off.

[0108] The driving method of the low-voltage side gate driver on the low-voltage side of the half-bridge driving circuit is specifically as follows:

[0109] The second floating rail voltage V FLOAT between the ground potential and the floating potential V Low_side is used to power the low-voltage side gate driver and drive the low-voltage side power tube M2.

[0110] The power supply voltage PVCC is compared with a preset voltage threshold VCC_UVLO, when the power supply voltage PVCC is less than the preset voltage threshold VCC_UVLO, the fourth MOS tube PM4 is driven to be turned on to pull down the floating potential V FLOAT to the power supply voltage PVCC; when the power supply voltage PVCC is greater than or equal to the preset voltage threshold V FLOAT , the fourth MOS tube PM4 is turned off.

[0111] It can be seen from the above technical solutions that the present application has the following advantages:

[0112] The floating rail circuit of the present application can provide a constant floating rail voltage, which does not change with process, voltage and temperature;

[0113] The high-voltage side and the low-voltage side of the half-bridge driving circuit are both powered by the floating rail circuit, which can ensure the voltage balance of the high-voltage side and the low-voltage side; at the same time, when the power supply voltage is low, the floating rail voltage can be switched to the maximum power supply voltage to ensure sufficient headroom.

[0114] It will be apparent to those skilled in the art that the application is not limited to the details of the above exemplary embodiments but can be implemented in other embodiments without departing from the spirit or essential characteristics of the application. Thus, the embodiments should be considered in all respects as illustrative and not restrictive, the scope of the application to be indicated by the appended claims rather than by the above description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No feature of the application is to be construed as limiting the application to the exact construction described herein unless required by the prior art.

[0115] Furthermore, it should be understood that although the specification is described in terms of embodiments, not every embodiment includes only one independent technical solution, and the specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A floating rail circuit for powering a gate driver, characterized by, The floating rail circuit comprises: a first MOS transistor, whose drain and source are connected to a first potential and a floating potential respectively, and whose gate is connected to a clamping node; a third resistor R3, which is electrically connected between the floating potential and a second potential; a current source electrically connected between the first potential and the clamping node, the voltage across the current source being a reference voltage V REF , and the internal resistance being a first resistance R1; a second resistor R2 and a second MOS transistor, which are electrically connected between the clamping node and the second potential; wherein the first MOS transistor and the second MOS transistor are both PMOS transistors or NMOS transistors, and the floating rail voltage between the second potential and the floating potential is the supply voltage of the gate driver.

2. The floating rail circuit of claim 1, wherein, The gate and the drain of the second MOS transistor are short-circuited, the source is connected to the second potential, and the second resistor R2 is electrically connected between the drain of the second MOS transistor and the clamping node; or, The gate and the drain of the second MOS transistor are short-circuited and connected to the clamping node, and the second resistor R2 is electrically connected between the source of the second MOS transistor and the second potential.

3. The floating rail circuit according to claim 1 or 2, characterized in that, When the floating rail circuit supplies power to a high-voltage side gate driver, the first potential is the ground potential, the second potential is the power supply voltage, and the first MOS transistor and the second MOS transistor are both PMOS transistors.

4. The floating rail circuit of claim 3, wherein, A floating rail voltage V between the power supply voltage and the floating potential High_side VDD is a supply voltage for a high-voltage side gate driver, and V High_side = K * V REF where K = R2 / R1.

5. The floating ground circuit according to claim 1 or 2, wherein When the floating rail circuit supplies power to a low-voltage side gate driver, the first potential is the power supply voltage, the second potential is the ground potential, and the first MOS transistor and the second MOS transistor are both NMOS transistors.

6. The floating rail circuit of claim 5, wherein, a floating voltage V between the second potential and the floating potential Low_side Vdd is a supply voltage for a low voltage side gate driver, and V Low_side = K*V REF where K = R2 / R1.

7. The floating rail circuit of claim 1, wherein, The floating rail circuit further comprises a capacitor C, which is electrically connected between the floating potential and the second potential.

8. A half-bridge drive circuit for driving a power transistor, characterized by The half-bridge driving circuit comprises: a first floating rail circuit for providing a first floating rail voltage V High_side to power a high voltage side gate driver for driving high voltage side power tubes; a second floating rail circuit for providing a second floating rail voltage V Low_side to power a low-side gate driver for driving a low-side power transistor; The first floating rail circuit is the floating rail circuit of any one of claims 1-4 and 7, and / or the second floating rail circuit is the floating rail circuit of any one of claims 1-2 and 5-7.

9. The half bridge drive circuit of claim 8, wherein, The first floating rail circuit further comprises a third MOS transistor, which is an NMOS transistor, whose source is connected to the ground potential and whose drain is connected to the floating potential. The third MOS transistor is turned on when the power supply voltage is less than a preset voltage threshold, so as to pull down the floating potential to the ground potential.

10. The half bridge drive circuit of claim 8, wherein, The second floating rail circuit further comprises a fourth MOS transistor, which is a PMOS transistor, whose source is connected to the power supply voltage and whose drain is connected to the floating potential. The fourth MOS transistor is turned on when the power supply voltage is less than a preset voltage threshold, so as to pull up the floating potential to the power supply voltage.

11. A driving method applied to the half-bridge driving circuit in claim 9, characterized in that, The driving method comprises: A first floating rail voltage V High_side Power supply for high-voltage side gate driver and driving high-voltage side power tube comparing the power supply voltage and the preset voltage threshold, and driving the third MOS transistor to be turned on when the power supply voltage is less than the preset voltage threshold, so as to pull down the floating potential to the ground potential, and driving the third MOS transistor to be turned off when the power supply voltage is greater than or equal to the preset voltage threshold.

12. A driving method applied to the half-bridge driving circuit in claim 10, characterized in that, The driving method comprises: A second floating rail voltage V Low_side Power supply for low-voltage side gate driver and drive low-voltage side power tube; comparing the power supply voltage and the preset voltage threshold, and driving the fourth MOS transistor to be turned on when the power supply voltage is less than the preset voltage threshold, so as to pull up the floating potential to the power supply voltage, and driving the fourth MOS transistor to be turned off when the power supply voltage is greater than or equal to the preset voltage threshold.

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