A GPON hardware system based on Zynq architecture

Abstract

A kind of GPON hardware system based on Zynq architecture, including Zynq framework SoC chip, optical line terminal optical module and optical network unit optical module, Zynq framework SoC chip includes processing system and programmable logic part, processing system and programmable logic part communicate by AXI-lite protocol.The GPON hardware system of flexible, scalable, easy maintenance network topology of P2P (point to point) or P2MP (point to multipoint) provided by the application is composed of Zynq architecture Soc chip and OLT (optical line terminal) optical module, ONU (optical network unit) optical module etc., the number of each node of system and topology can be flexibly set, and each node can be managed, configured and maintained remotely by SoC development platform based on Zynq architecture, and the hardware system built by it has the advantages of simple system, controllable cost, management configuration, simple upgrade and maintenance, high safety and reliability, no backdoor etc.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-speed digital optical communication, and particularly relates to a GPON hardware system based on a Zynq architecture. BACKGROUND

[0002] With the continuous development and popular application of a large number of high-speed digital communication and data acquisition and processing technologies such as 5G telecommunication networks, high-speed data services and 4K high-definition video transmission, FTTx gradually becomes a mainstream access network implementation mode for civilian and commercial use. As an alternative optimization scheme of Ethernet switching in the network, GPON cancels the use of passive optical devices for access and distribution of Ethernet switches, and replaces the traditional three-layer Ethernet design with a two-layer optical fiber network. The GPON (Gigabit-capable Passive Optical Network) access network system with the characteristics of high speed, high bandwidth, long distance, high reliability QoS, high security has become the most important optical communication system at present.

[0003] The GPON hardware system device of the prior art mainly adopts GPON OLT and GPON ONU special integrated chips of an imported manufacturer such as Microsemi to realize large-scale civilian and commercial low-cost access network applications in the telecommunication field. In addition, some industrial control fields use FPGA+CPU architecture with high cost and difficult configuration management and maintenance. The FPGA is used to realize high-speed data processing and transmission, and the CPU is used to realize data protocol conversion, service configuration management and the like, and two chips need to be configured and upgraded respectively. The traditional GPON system application environment is mostly in a normal temperature network room or office, and the network topology is complex, and the reliability and safety are not high. For example, the Chinese patent with the publication number CN112055270A discloses a GPON system, device access method and OLT supporting DPoG technology, a gigabit Ethernet passive optical network (GPON) system, device access method and optical line terminal supporting gigabit Ethernet passive optical network technology based on a cable data service interface specification protocol, which simply realizes the support for gigabit Ethernet passive optical network technology based on the GPON system, but uses a traditional data processing chip for processing, which cannot meet the current application requirements. In addition, special application fields such as military defense and aerospace have higher requirements for high speed, miniaturization, high reliability, nationalization, flexible networking, easy management and maintenance, miniaturization, reliability and safety. SUMMARY

[0004] To solve the above technical problems, the application provides a GPON hardware system based on a Zynq architecture, which is suitable for a high-speed digital optical communication GPON system with a P2P (point-to-point) or P2MP (point-to-multipoint) flexible configuration network topology composed of a domestic Zynq SoC (system on chip) chip and special harsh environment OLT (optical line terminal), ONU (optical network unit) optical module and the like.

[0005] The application is achieved by the following technical solutions.

[0006] The GPON hardware system based on the Zynq architecture comprises a Zynq architecture SoC chip, an optical line terminal optical module and an optical network unit optical module, the Zynq architecture SoC chip comprises a processing system and a programmable logic part, the processing system and the programmable logic part communicate through an AXI-lite protocol; the processing system comprises a memory module composed of a QSPI FLASH, an EMMC memory and a processing system DDR3 memory and a remote upgrade module; the programmable logic part comprises a high-speed GTX serial data transceiver and a low-speed HR parallel data transceiver, the high-speed GTX serial data transceiver is connected with a group of independent optical line terminal optical modules and optical network unit optical modules; another group of optical line terminal optical modules and optical network unit optical modules are connected to a serial-parallel conversion chip and then connected to the low-speed HR parallel data transceiver, the programmable logic part further comprises a programmable logic part DDR3 memory and a PCIE 2.0x4 high-speed interface.

[0007] Further, the remote upgrade module comprises a gigabit network port and an RS232 serial port.

[0008] Further, the Zynq architecture SoC chip is provided with a JTAG debugging port.

[0009] Further, the QSPI FLASH of the memory module is a 512Mbit QSPI Flash.

[0010] Further, the processing system DDR3 memory is composed of two pieces of 256Mx16bit DDR3 SDRAM memory.

[0011] Further, the programmable logic part DDR3 memory is composed of four pieces of 256Mx16bit DDR3 memory.

[0012] Further, the optical line terminal optical module is connected with an optical power divider, and the optical network unit optical module of other GPON systems can be connected through the optical power divider.

[0013] Further, an external remote upgrade, configuration management, log maintenance control platform is further included, and the remote upgrade module of the Zynq architecture SoC chip on the processing system is connected to the remote upgrade, configuration management, log maintenance control platform through a gigabit network port and an RS232 serial port.

[0014] Further, a host server is further included, and the programmable part of the Zynq architecture SoC chip is connected to the host server through a PCIE 2.0x4 high-speed interface.

[0015] Further, the optical power divider is one of a 1:16 optical power divider or a 1:32 optical power divider.

[0016] The application has the advantages that: through the implementation of the application, a GPON hardware system of a flexible, scalable, easy-to-maintain network topology of P2P (point-to-point) or P2MP (point-to-multipoint) based on a Zynq architecture Soc chip and OLT (optical line terminal) optical modules, ONU (optical network unit) optical modules and the like is provided, the number of nodes and the topology of the system can be flexibly set, and each node can be remotely managed, configured and maintained through a SoC development platform based on the Zynq architecture, and the hardware system built therefrom has the advantages of simple system, controllable cost, simple management configuration, upgrade and maintenance, high safety and reliability and no backdoor. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a system implementation block diagram of the application;

[0018] Figure 2 is a remote upgrade-gigabit Ethernet port principle diagram of the application;

[0019] Figure 3 is a remote upgrade-RS232 serial port principle diagram of the application;

[0020] Figure 4 is an OLT (optical line terminal) optical module and an ONU (optical network unit) optical module principle diagram of the application;

[0021] Figure 5 is a serial-parallel adapter JS2711 principle diagram of the application;

[0022] Figure 6 is a PCIe 2.0x4 Lanes principle diagram of the application;

[0023] Figure 7 is a SoC high-speed GTX Bank based on the Zynq architecture of the application;

[0024] Figure 8 is a PS and PL (programmable logic) part communication AXI-Lite bus block diagram of the application;

[0025] Figure 9 is a network topology composition block diagram of a GPON hardware system based on Zynq architecture of the present application. DETAILED DESCRIPTION

[0026] The technical solutions of the present application are further described below, but the scope of protection is not limited to the description.

[0027] As Figure 1As shown, a GPON hardware system based on Zynq architecture includes a Zynq architecture SoC chip, an optical line terminal optical module and an optical network unit optical module, and the Zynq architecture SoC chip is divided into a PS (processing system) part and a PL (programmable logic) part. The PS (processing system) part of the Zynq architecture SoC chip mainly includes a first start-up memory QSPI FLASH and a second start-up memory EMMC for loading a system start-up BOOT operating system image file, and further includes a DDR3 memory for caching user data, a gigabit Ethernet port for remote upgrading and system management, and an RS232 serial port for local debugging. The PL (programmable logic) part of the Zynq architecture SoC development system mainly includes 2.5Gbps special harsh environment applicable OLT transceiver optical modules and ONU (optical network unit) optical modules realized through high-speed GTX transceivers, and 2.5Gbps special harsh environment applicable OLT transceiver optical modules and ONU transceiver optical modules realized through 16-bit parallel interfaces of low-speed HR wide voltage range Banks to 2.5Gbps special harsh environment applicable OLT transceiver optical modules and ONU transceiver optical modules of high-speed SERDES serial-parallel conversion interface chips JS2711 serial interfaces. The 2.5Gbps special harsh environment applicable OLT transceiver optical modules and ONU transceiver optical modules form a flexible GPON communication system. P2P (point-to-point) communication at the current level or P2MP (multi-level point-to-multipoint) transmission end 2.5Gbps rate continuous mode and reception end 2.5Gbps rate burst mode communication can be realized. The I2C bus management interfaces provided by two OLT (optical line terminal) optical modules and two ONU (optical network unit) optical modules are connected to the I2C0 controller of the PS (processing system) part of the Zynq architecture SoC chip. Through system management and log functions, the transmission enable / disable, reception optical signal inspection, transmission end burst module use / disable and other fiber communication link management and detection functions of the two OLT and two ONU transceiver optical modules can be realized. The PL (programmable logic) part of the Zynq architecture SoC chip further includes a PCIe 2.0x4 Lanes high-speed interface realized through a high-speed GTX transceiver, and a PL (programmable logic) part DDR3 memory for realizing real-time data caching processing with high speed and high bandwidth of PCIe 5.0Gbpsx4 realized through an HP high-performance Bank. The PL (programmable logic) part of the Zynq architecture SoC chip realizes high-speed serial data transceiving, conversion processing and protocol forwarding of the fiber network GPON system, and the PS (processing system) part of the Zynq architecture SoC chip realizes user management, remote upgrading, system log recording and other work of the GPON system.The Zynq architecture SoC development system PS (processing system) part and PL (programmable logic) part, through the AXI-Lite high-speed communication bus between the processors in the Zynq SoC chip, the information interaction, protocol forwarding and data communication of the PS (processing system) part and the PL (programmable logic) part. Two groups of OLT and two ONU transceiver optical modules, respectively provide through GTX Bank high-speed serial data interface direct connection OLT (optical line terminal) optical module 1 and ONU (optical network unit) optical module 1; and through HRBank low-speed parallel data interface, after serial-parallel conversion chip, connect OLT (optical line terminal) optical module 2 and ONU (optical network unit) optical module 2, two kinds of photoelectric conversion interface. Can make no matter is the high-end series chip has the high-speed SERDES interface, or the low-end series chip only has HR low-speed interface, can be composed of flexible and diverse, easy to expand, easy to manage P2P (point to point), or P2MP (multi-level point to multi-point) single or multi-level GPON hardware system.

[0028] Reference Figure 1 A GPON hardware system based on Zynq architecture, mainly uses Zynq architecture SoC chip and two groups of OLT (optical line terminal) optical module 1 and 2, ONU (optical network unit) optical module 1 and 2 suitable for special harsh environment to form a domestic special GPON hardware system with system management, remote upgrade, data processing, protocol forwarding and support for various network topology expansion. Based on Zynq architecture SoC chip, FMQL series FMQL45T900 and other different models of Fudan Microelectronics can be selected. It contains two parts: PS (processing system) part and PL (programmable logic) part. The two parts can be used separately, or can be used together, and in fact the power supply circuit is also designed to independently power each part, so that the PS (processing system) part or the PL (programmable logic) part can be powered off when not used.

[0029] The PS (Processing System) part includes a four-core high-performance processor with a maximum working frequency of 1 GHz, a first-level cache including 32 KB instruction cache and 32 KB data cache, a second-level cache capacity of 256 KB, a storage memory capacity of 256 KB, an external DDR SDRAM memory interface of DDR3, DDR3L, and LPDDR2, an external SRAM static memory interface supporting 2 x QSPI, NAND, and NOR Flash, general-purpose peripherals including 2 x UART, 2 x CAN2.0, 2 x I2C, 2 x SPI, 2 x 64b GPIO, high-speed communication peripherals including 2 x USB, 2 x Tri-Mode Gigabit Ethernet, and 2 x SD / SDIO, and security protection measures including a dedicated security processor, a dedicated security algorithm hard core of RSA, AES, SHA-256, and SM4 for signature verification and decryption, and support for secure boot.

[0030] The PL (Programmable Logic) part includes 349760 logic cells (Logic Cells), 218600 lookup tables (LUTs), 437200 flip-flops (Flip-Flops), 545 block memories BRAM (36 kb Blocks), 900 DSP units, and 150 HPIO, 212 HRIO, x 16 Lanes GTX high-speed transceivers, and a maximum support of PCIe GEN2 x 8 hard core interface.

[0031] The memory module of the PS (Processing System) part sets up a 512Mbit QSPI Flash for the first boot configuration program loading memory of the Zynq architecture SoC development platform, and an EMMC memory is used as an optional first boot memory for a post-boot loading BOOT partition, which is used for loading a 4GB large-capacity memory of an operating system image file system; and the PS (Processing System) part DDR3 memory is designed with two pieces of external 256M x 16bit DDR3 SDRAM memory, which is used for PS (Processing System) part operating system read-write data cache and program loading. The QSPI Flash memory, the EMMC memory, and the PS (Processing System) part DDR3 memory constitute the memory module connected externally to the Zynq architecture SoC chip. The PS (Processing System) part is also designed with a Gigabit Ethernet port for GPON system remote upgrade, system management and configuration maintenance, and an RS232 serial port supporting or remote fast log query and system debugging. Figure 2 Remote upgrade - Gigabit Ethernet schematic diagram and Figure 3 Remote upgrade - RS232 serial port schematic diagram Figure 1 The remote upgrade is shown.

[0032] As Figure 1As shown, the PL (programmable logic) part includes 2.5Gbps special harsh environment applicable OLT1 optical module 1 and ONU (optical network unit) optical module 1 directly connected through high-speed GTX transceiver; and 2.5Gbps special harsh environment applicable OLT (optical line terminal) optical module 2 and ONU (optical network unit) optical module 2 through 16-bit parallel interface of low-speed HR wide voltage range Bank to high-speed SERDES serial-parallel conversion 1, 2 interface chip JS2711 serial interface.

[0033] The PL (programmable logic) part of the OLT1 optical module 1, 2 and ONU (optical network unit) optical module 1, 2, as Figure 4 As shown in the schematic diagram of the OLT (optical line terminal) optical module and the ONU (optical network unit) optical module, both are designed to support 2.5Gbps special harsh environment high-temperature resistance and anti-vibration requirements, and are made of domestic products. The OLT (optical line terminal) optical module is connected through a 1:16 or 1:32 optical power divider to form a GPON communication system with flexible and easily expandable network topology architecture. Figure 9 As shown, the P2P (point-to-point) communication at this level can be realized, or the transmitting end 2.5Gbps rate continuous mode and the receiving end 2.5Gbps rate burst mode gigabit PON network communication of P2MP (multi-level point-to-multipoint) can be realized. In addition, the OLT (optical line terminal) optical module and the ONU (optical network unit) optical module are completely consistent in size, structure, interface definition, only the internal circuit, receiving and transmitting wavelength range, software communication protocol and product model are different. By updating only the BOM (bill of materials) model, different combinations of hardware configuration and software definition reconfiguration such as four-way ONU (optical network unit) optical module, four-way OLT (optical line terminal) optical module, etc. can be realized, thereby expanding the diversified, simplified, low-cost, multi-functional, short development cycle GPON communication system with different network topology architecture.

[0034] The serial-parallel conversion 1 and serial-parallel conversion 2 high-speed interface chips of the PL (programmable logic) part, as shown in Figure 5 As shown in the schematic diagram of the serial-parallel conversion JS2711, it mainly focuses on the Zynq architecture SoC development platform GPON system without high-speed GTX transceiver interface under certain low-cost and reliable design requirements, which can still realize a simplified low-cost, multi-functional and easily expandable network system.

[0035] The I2C bus management interface provided by the two OLTs and two ONUs (Optical Line Transmitter Units) is connected to the general peripheral I2C0 controller of the PS (Processing System) part of the Zynq architecture SoC development platform. This enables fiber optic communication link management and detection functions such as enable / disable transmit, check received optical signals, and enable / disable burst module usage at the transmitter for the two OLTs and two ONUs through system management and logging.

[0036] The Zynq architecture SoC development platform's PL (Programmable Logic) section also includes a PCIe 2.0×4 Lanes high-speed interface implemented via a high-speed GTX transceiver, and a PL (Programmable Logic) section DDR3 memory implementing high-speed, high-bandwidth real-time data cache processing at PCIe 5.0GT / s×4 via HP high-performance banks. (Reference) Figure 6 The PCIe 2.0 × 4Lanes schematic shows a four-channel high-speed SEDERS serial data connection to the Zyqn SoC's high-speed GTX transceiver. (Refer to...) Figure 7 The high-speed GTX bank of the SoC based on the Zynq architecture is shown in the reference. Figure 9 The network topology block diagram of the GPON hardware system based on the Zynq architecture is shown. It enables bidirectional multi-channel data transmission from multiple topology GPON systems to the host server for analysis and processing, or synchronizes step-by-step control information or data packets from the host server to the Zynq SoC chips at each node of the GPON system for system configuration or data transmission at each node. The PL (Programmable Logic) section includes a DDR3 memory... Figure 1 As shown, the design uses four 256M×16bit DDR3 memory chips. With a clock frequency of 400MHz, the DDR data bandwidth is 400MHz×2×16bit×4=51200Mbit / 8=6400MB / s=6.4GB / s. The maximum data throughput of PCIe 2.0×4Lanes is 5GT / s×8 / 10bit×4=2GB / s. The maximum data bandwidth of the four OLT and ONU (Optical Network Unit) optical modules is 2.5Gbps×8 / 10×4=250MB / s×4=1GB / s. The system's maximum data throughput is 2GB / s + 1GB / s, totaling 3GB / s data bandwidth. Adding the estimated maximum 20% channel loss, the total is 3.75GB / s. The 6.4GB / s bandwidth of the four DDR3 memory chips in the PL (Programmable Logic) section meets the system's real-time data storage and processing bandwidth requirements without requiring additional data processing in the PL section.

[0037] The PS (processing system) part and the PL (programmable logic) part of the Zynq architecture SoC development platform communicate through the AXI-Lite high-speed communication bus between the processors inside the Zynq SoC chip, as shown in the following reference Figure 8 The AXI-Lite bus diagram for the communication between the PS and the PL (programmable logic) part is shown in the following figure, which uses 2*AXI 64-bit Master and Slave mode, and 4*AXI 64-bit Memory and 16 Interrupts, to perform the information interaction, protocol forwarding and data communication between the PS (processing system) part and the PL (programmable logic) part, and to realize the communication between the host server and the remote upgrade, configuration management, log maintenance control platform through the PCIe 2.0*4Lanes interface of the PL (programmable logic) part.

[0038] The above specific embodiments are used to help understand the present application, and are not used to limit the present application. For those skilled in the art to which the present application belongs, according to the idea of the present application, several simple deductions, deformations or substitutions can be made.

Claims

1. A GPON hardware system based on Zynq architecture, characterized in that: The application relates to a Zynq architecture SoC chip, an optical line terminal optical module and an optical network unit optical module, wherein the Zynq architecture SoC chip comprises a processing system and a programmable logic part, the processing system and the programmable logic part communicate through an AXI-lite protocol; the processing system comprises a memory module composed of a QSPI FLASH, an EMMC memory and a processing system DDR3 memory and a remote upgrade module; the programmable logic part comprises a high-speed GTX serial data transceiver and a low-speed HR parallel data transceiver, the high-speed GTX serial data transceiver is connected with a group of independent optical line terminal optical modules and optical network unit optical modules; another group of optical line terminal optical modules and optical network unit optical modules are connected to a serial-parallel conversion chip and then connected with the low-speed HR parallel data transceiver, the programmable logic part further comprises a programmable logic part DDR3 memory and a PCIE 2.0x4 high-speed interface; the remote upgrade module comprises a gigabit network port and an RS232 serial port; the optical line terminal optical module is connected with an optical power divider, and the optical line terminal optical module can be connected to optical network unit optical modules of other GPON systems through the optical power divider; the Zynq architecture SoC chip is further provided with an external remote upgrade, configuration management and log maintenance control platform, the remote upgrade module of the processing system of the Zynq architecture SoC chip is connected to the remote upgrade, configuration management and log maintenance control platform through the gigabit network port and the RS232 serial port; the Zynq architecture SoC chip further comprises a host server, and the programmable part of the Zynq architecture SoC chip is connected with the host server through the PCIE 2.0x4 high-speed interface; the Zynq architecture SoC chip is provided with a JTAG debugging port; the QSPI FLASH of the memory module is a 512Mbit QSPI Flash; the processing system DDR3 memory is composed of two 256Mx16bit DDR3 SDRAM memories; the programmable logic part DDR3 memory is composed of four 256Mx16bit DDR3 memories; the optical power divider is one of a 1:16 optical power divider and a 1:32 optical power divider. ​ ​ ​ ​ 2. The Zynq architecture based GPON hardware system as claimed in claim 1, wherein: ​ 3. The Zynq architecture based GPON hardware system as claimed in claim 1, wherein: ​ 4. The Zynq architecture based GPON hardware system as claimed in claim 1, wherein: ​ 5. The Zynq architecture based GPON hardware system as claimed in claim 1, wherein: ​ 6. The Zynq architecture based GPON hardware system as claimed in claim 2, wherein: ​

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