FPGA-based LVDS high-speed data switch

Abstract

The application discloses an FPGA-based LVDS high-speed data switch and belongs to the field of data switches.The FPGA-based LVDS high-speed data switch can be divided into a port configuration module, a routing configuration module, a data cache module, a data transceiving module, a clock generation module and a management interface module according to functions, can provide flexible high-speed data transmission channels for the interconnection between multiple chips on a board-level circuit, has a dynamic data routing function, can transmit data based on an LVDS bus, is suitable for the design of multiple masters and multiple slaves in parallel, provides a good solution for multipoint high-speed LVDS high-speed data transmission, can meet the requirement of flexible interconnection communication between multiple devices at high speed, reduces the complexity of the software and hardware design of the LVDS high-speed data switching between multiple chips on a board, has a market prospect and is suitable for popularization and application.

Description

Technical Field

[0001] This invention relates to the field of data switches, and more specifically, to an FPGA-based LVDS high-speed data switch. Background Technology

[0002] LVDS is widely used in high-speed board-level signal transmission due to its low power consumption, low bit error rate, and low crosstalk. However, LVDS bus signals can usually only be transmitted end-to-end and cannot be applied to mesh, star and other topologies.

[0003] Although the BLVDS and MLVDS standards can be used for communication between multiple LVDS devices, they sacrifice transmission rate due to time-sharing bus and have relatively stringent hardware design requirements, thus limiting their value in practical applications.

[0004] To address the shortcomings of existing signal technologies in achieving multi-master, multi-slave, dynamic routing configuration, and high-speed LVDS flexible interconnection and communication between multiple devices, the inventors have designed an FPGA-based LVDS high-speed data switch. Summary of the Invention

[0005] 1. Technical problems to be solved

[0006] To address the problems existing in the prior art, the purpose of this invention is to provide an FPGA-based LVDS high-speed data switch that can realize multi-master and multi-slave parallel communication functions, dynamically loaded data routing functions, flexible port combination configuration, adapt to different serial encoding formats and data rates of master and slave devices, and easily achieve multi-point communication in board-level high-speed LVDS communication.

[0007] 2. Technical Solution

[0008] To solve the above problems, the present invention adopts the following technical solution.

[0009] An FPGA-based LVDS high-speed data switch includes a port configuration module, a routing configuration module, a data buffer module, a data transceiver module, a clock generation module, and a management interface module. The port configuration module enables flexible configuration of LVDS data transmission and reception. It includes at least one set of input / output interfaces (IOBs) / input / output blocks (IOBs), each I / O interface / IOB being an external LVDS differential I / O pad. Each I / O interface / IOB includes a set of tri-state control signals T / R. Each set of I / O interfaces / IOBs is also connected in series with an IO Delay unit for providing specific input / output delay functions. The IO Delay unit is programmable and includes an output delay path O Delay and an input delay path I Delay, wherein the output delay path O... The input direction of the Delay is connected in sequence to the output parallel-to-serial converter (OSER) and the clock gating (CGA) unit. The output direction of the corresponding input delay path IDelay is connected in sequence to the clock distribution (CDA) unit and the deserializer (IDES). At the same time, depending on the encoding difference between the input and output signals, the output parallel-to-serial converter (OSER) and the deserializer (IDES) can be dynamically selected as either 8-bit or 10-bit.

[0010] An LVDS device interface consists of at least one data port and at most one on-path clock port. The maximum number of LVDS device interfaces depends on the amount of hardware resources of the FPGA used, including the phase-locked loop (PLL), low-voltage differential signal LVDS I / O, serializers (SERDES), and block random access memory (BRAM).

[0011] The routing configuration module is used to connect the data buses of each source end and destination end in the internal switching network. Each LVDS device interface consists of one or more data ports plus an optional clock port. The path from each source end to the destination end is determined by the two-dimensional routing table SW_Table. Each valid bit in the two-dimensional routing table SW_Table is used to control the input signal of the corresponding row to drive the output of the corresponding column.

[0012] The data caching module is used to buffer and forward data during master-slave data interaction. The cache FIFO in the data caching module is implemented by the block random access memory (BRAM) in the FPGA through IP core encapsulation, and each LANE port of each LVDS device interface is allocated a dedicated FIFO.

[0013] The data transceiver module is used to forward data between the source port and the destination port. The data transceiver module receives data and clock sent by the master device through the LVDS Rx interface. After buffering the data under the synchronous clock driven by the clock generation module, the data and the accompanying clock are transmitted to the LVDS Tx interface through the internal switching network.

[0014] The system high-speed master clock SYS_CLK of the clock generation module is output after being multiplied by the system phase-locked loop (PLL) from an externally input stable reference clock; the reference clock of each LVDS device interface is determined by its own clock configuration parameters.

[0015] The management interface module maps the I / O attributes of all ports, routing tables, clock trees of master and slave interfaces, and FIFO status data to a segment of address space in the form of registers. The registers are read and written through an external synchronous serial interface to realize parameter configuration and status reading.

[0016] Furthermore, the IO Delay unit is used to provide specific input / output delays to synchronize the phases between multiple LVDSLANEs and reduce the bit error rate;

[0017] When the switch is operating in direct forwarding mode, uplink and downlink data do not need to be buffered; when operating in buffered mode, the data sent by the host is first stored in the buffer FIFO, and the data is output after being converted by the output parallel-to-serial converter OSER. At the same time, according to the configured slave-side encoding mode 10b / 8b selection signal, the output parallel-to-serial converter OSER10 or the output parallel-to-serial converter OSER8 is selected.

[0018] The clock-gated CGA unit is used to generate special characters for control and indication, namely K codes.

[0019] Furthermore, in buffered receive mode, the serial data input from the LVDS port is first cyclically detected by the clock distribution CDA unit to identify special control and synchronization characters. After alignment, the valid serial data is sent to the deserializer IDES for serial-to-parallel conversion. The converted data is then written into the receive buffer FIFO on the slave side.

[0020] When the host-side encoding mode is 10-bit, its output data is decoded by a 10b / 8b decoder using a lookup table to obtain the target data.

[0021] Furthermore, the switch supports both 1:1 and 1:M transceiver port mapping relationships through the two-dimensional routing table SW_Table, and can also realize N:1 and N:M communication through time-division multiplexing by dynamically updating the routing table; the routing configuration module realizes the connection of the data bus between each source end and destination end in the internal switching network according to the two-dimensional routing table SW_Table.

[0022] Furthermore, the FIFO states include Full, Almost_Full, Empty, and Almost_Empty. The state information is read by the management interface module and simultaneously fed back directly to the external IO port of the corresponding LVDS device interface.

[0023] The FIFO data length thresholds corresponding to each state signal, namely Full_Len, Almost_Full_Len, Empty_Len, and Almost_Empty_Len, are configured through the management interface module.

[0024] Furthermore, the data read / write port width of the FIFO is set to 8 bits, and the maximum depth of the FIFO is 65536 bytes; the status signal of the FIFO is led out to the host for data flow control on the host side.

[0025] Furthermore, the LANE width of the transmitting end Tx and Rx in the LVDS device interface can be independently configured to any value among 1, 2, 4, and 8. When the LANE widths of the Tx and Rx ends are different, the Rx end can adjust the reading timing combination of its own FIFO to ensure that the Tx end outputs correct data through the data LANE.

[0026] Furthermore, when there is a difference in the total data bandwidth of the devices connected to the Tx and Rx ends, the clock generation module and the data buffer module work together, while the host monitors the status signal of the FIFO to prevent data overflow.

[0027] Furthermore, the accompanying reference clock of the LVDS device interface is a low-frequency clock, which is output by the clock generation module to the dedicated phase-locked loop (PLL) of the interface. The PLL multiplies the frequency to generate a reference clock that is 4 times or 5 times the frequency. The reference clock provides clock drive for the serializer SERDES, encoder, decoder, clock distribution unit (CDA), clock gating unit (CGA), and port data FIFO of the interface.

[0028] When there is a difference in the LANE width between the LVDS master and slave interfaces, the phase-locked loop (PLL) performs corresponding frequency division or multiplication on the reference clock according to the ratio of the LANE width difference, so as to match the data transmission and reception rates of the master and slave ends.

[0029] 3. Beneficial Effects

[0030] Compared with the prior art, the advantages of this invention are:

[0031] This invention, through its six-module setup—port configuration module, routing configuration module, data buffer module, data transceiver module, clock generation module, and management interface module—compared to traditional data transmission technologies such as LVDS, BLVDS, and MLVDS, provides a flexible, high-speed data transmission channel for interconnecting multiple chips on the board level. Its dynamic data routing function allows LVDS bus-based data transmission to move beyond fixed point-to-point directions and paths between chips, while also accommodating multi-master, multi-slave parallel designs. It avoids the bandwidth bottlenecks caused by time-division multiplexing in MLVDS and BLVDS, providing an excellent solution for high-speed, multi-point LVDS data transmission. This meets the requirements for flexible, high-speed LVDS interconnection and communication between multiple devices, reduces the hardware and software design complexity of high-speed LVDS data exchange between multiple chips on the board level, lowers design and manufacturing costs, and offers high operational efficiency. It has market potential and is suitable for widespread application. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the system framework of the port configuration module proposed in this invention;

[0033] Figure 2 This is a schematic diagram of the system framework of the routing configuration module proposed in this invention;

[0034] Figure 3 This is a schematic diagram of the system framework of the data caching module proposed in this invention;

[0035] Figure 4 This is a schematic diagram of the system framework of the data transceiver module proposed in this invention;

[0036] Figure 5 This is a schematic diagram of the system framework of the clock generation module proposed in this invention;

[0037] Figure 6 This is a schematic diagram of the system framework of the management interface module proposed in this invention. Detailed Implementation

[0038] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0039] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "top / bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "sleeved / connected," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0041] Example:

[0042] Please see Figure 1-6 An FPGA-based LVDS high-speed data switch includes a port configuration module, a routing configuration module, a data buffer module, a data transceiver module, a clock generation module, and a management interface module.

[0043] like Figure 1 As shown, the port configuration module is used to implement flexible configuration of LVDS data transmission and reception. The port configuration module includes at least one set of input / output interfaces (IO) / input / output blocks (IOB). The input / output interfaces (IO) / input / output blocks (IOB) are external LVDS differential IO pads. The input / output interfaces (IO) / input / output blocks (IOB) include a set of tri-state control signals (T / R). Each set of input / output interfaces (IO) / input / output blocks (IOB) is also connected in series with an IO Delay unit for providing specific input / output delay functions. The IO Delay unit is programmable and includes an output delay path (O Delay) and an input delay path (I Delay). The input direction of the output delay path (O Delay) is sequentially connected to an output parallel-to-serial converter (OSER) and a clock gating (CGA) unit. The output direction of the corresponding input delay path (I Delay) is sequentially connected to a clock distribution (CDA) unit and a deserializer (IDES). At the same time, according to the encoding difference between the input and output signals, an 8-bit or 10-bit output parallel-to-serial converter (OSER) and a deserializer (IDES) can be dynamically selected.

[0044] Figure 1In the direct forwarding mode, From Switch Fabric and To Switch Fabric are the uplink and downlink clock or data signals, respectively; From Tx Buf and To Rx Buf are the data signals read from the port's transmit buffer and the data signals written to the receive buffer, respectively, both with a bit width of 8 bits.

[0045] The IO Delay unit provides specific input / output delays to synchronize the phases of multiple LVDS LANEs and reduce the bit error rate. When the switch operates in direct forwarding mode, uplink and downlink data do not require buffering. In buffered mode, data sent by the host is first stored in a buffer FIFO, converted by the output parallel-to-serial converter (OSER), and then output. Simultaneously, based on the configured slave-side encoding mode 10b / 8b selection signal, either output parallel-to-serial converter (OSER10) or output parallel-to-serial converter (OSER8) is selected. The clock gating (CGA) unit generates special characters (K codes) for control and indication, enabling auxiliary functions such as bit synchronization and link alignment.

[0046] Accordingly, in buffered receive mode, the serial data input to the LVDS port is first cyclically detected by the clock distribution CDA unit to identify special control and synchronization characters. After data alignment, the valid serial data is sent to the deserializer IDES for serial-to-parallel conversion. The converted data is then written to the slave's receive buffer FIFO. When the master's encoding mode is 10-bit, the output data is decoded by a 10b / 8b decoder using a lookup table to obtain the target parallel data.

[0047] An LVDS device interface consists of at least one data port and at most one associated clock port. The maximum number of LVDS device interfaces depends on the amount of hardware resources used in the FPGA, such as the phase-locked loop (PLL), low-voltage differential signal LVDS I / O, serializers (SERDES), and block random access memory (BRAM).

[0048] As shown in Figure 2, the routing configuration module is used to connect the data buses of each source and destination end in the internal switching network. Each LVDS device interface consists of one or more data ports plus an optional accompanying clock port. The data path from each source end to the destination end is determined by the two-dimensional routing table SW_Table. Each valid bit in the two-dimensional routing table SW_Table is used to control the input signal of the corresponding row to drive the output of the corresponding column. The switch supports 1:1 and 1:M transceiver port mapping relationships through the two-dimensional routing table SW_Table, and can also realize N:1 and N:M communication in a time-division manner by dynamically updating the routing table. The routing configuration module completes the connection of the data buses of each source end and destination end in the internal switching network according to the two-dimensional routing table SW_Table.

[0049] like Figure 3 As shown, the data caching module is used for buffering and re-forwarding data during master-slave data interaction. The cache FIFO is implemented by encapsulating the FPGA's internal Block Random Access Memory (BRAM) through an IP core. Each LANE port of each LVDS interface is configured with a dedicated FIFO. The read and write clocks of each FIFO under the same interface are from the same source, while the clocks between different interfaces are usually asynchronous. When there is a difference in the LANE width or clock frequency of the master and slave interfaces, rate matching and data forwarding are achieved through the cache FIFO. The write clock of the FIFO comes from the clock of this interface after being multiplied by a PLL, and shares the clock domain with the port receiving module; the read clock is the driving clock of the destination interface, which is obtained by frequency division of the system's high-speed clock.

[0050] The FIFO's states include Full, Almost_Full, Empty, and Almost_Empty. This status information can be read by the management interface module or directly fed back to the external I / O port of the corresponding LVDS device interface. The FIFO data length thresholds corresponding to each status signal, including Full_Len, Almost_Full_Len, Empty_Len, and Almost_Empty_Len, are all configurable through the management interface module. The data read / write port width of the FIFO is set to 8 bits, and the maximum FIFO depth is 65536 bytes. The FIFO status signals are output to the host for host-side data flow control.

[0051] As shown in Figure 4, the data transceiver module is used to forward data between the source port and the destination port. The module receives data and clock signals from the master device via the LVDS Rx interface. After buffering the data under the synchronous clock output by the clock generation module, it transmits the data and accompanying clock signals to the LVDS Tx interface via the internal switching network. The LANE widths of the Tx and Rx ends of the LVDS device interface can be independently configured to any value among 1, 2, 4, and 8. When the LANE widths of the Tx and Rx ends are different, the correct data output from the Tx end is ensured by adjusting the reading timing combination of the Rx end FIFO. When there is a difference in the total data bandwidth of the devices connected to the Tx and Rx ends, the clock generation module and the data buffer module work together, while the host monitors the FIFO status signal to prevent data overflow.

[0052] like Figure 5As shown, the system high-speed master clock SYS_CLK of the clock generation module is output after being multiplied by the system phase-locked loop (PLL) from an externally input stable reference clock. The reference clock for each LVDS device interface is determined by the corresponding clock configuration parameters. The low-frequency accompanying reference clock of the LVDS device interface is output by the clock generation module to the dedicated PLL for that interface. After being multiplied by the PLL, a 4x or 5x working clock is generated to provide clock drive for the serializers SERDES, encoders, decoders, clock distribution units (CDA), clock gating units (CGA), and port data FIFOs of that interface. When there is a difference in the LANE width between the LVDS master and slave interfaces, the PLL divides or multiplies the reference clock according to the ratio of the LANE width difference to match the data transmission and reception rates of the master and slave ends. The system high-speed clock SYS_CLK is generated by multiplying the external reference clock by the FPGA's internal system PLL. The master device interface's accompanying clock is multiplied by a dedicated phase-locked loop PLL to generate the interface reference clock. The multiplication factor is determined by the SERDES encoding method of the master and slave devices' serializers and the data port width. In direct forwarding mode, this interface clock can also be used as the operating clock for the corresponding slave device port.

[0053] like Figure 6 As shown, the management interface module maps all port IO attributes, routing tables, master-slave interface clock trees, FIFO status and other information to an address space in the form of registers. The registers are read and written through an external synchronous serial interface to realize parameter configuration and status monitoring.

[0054] This invention achieves high-speed switching and flexible routing of LVDS signals through the coordinated operation of six modules: port configuration, routing configuration, data caching, data transmission and reception, clock generation, and management interface. It supports multi-master and multi-slave parallel communication, breaks through the limitations of traditional LVDS point-to-point transmission, and avoids the bandwidth bottleneck caused by BLVDS / MLVDS time-division multiplexing. It reduces the design difficulty and implementation cost of high-speed interconnection of multiple devices at the board level. The system has low latency and high reliability, and has good engineering application value.

[0055] The above are merely preferred embodiments of the present invention; however, the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and its improved concept, should be covered within the scope of protection of the present invention.

Claims

1. An FPGA-based LVDS high-speed data switch, comprising a port configuration module, a routing configuration module, a data buffer module, a data transceiver module, a clock generation module, and a management interface module, characterized in that: The port configuration module is used to implement flexible configuration of LVDS data transmission and reception. The port configuration module includes at least one set of input / output interfaces (IO) / input / output blocks (IOBs). Each IO / IOB is an external LVDS differential IO pad. Each IO / IOB includes a set of tri-state control signals (T / R). Each IO / IOB is also connected in series with an IO Delay unit for providing specific input / output delay functions. The IO Delay unit is programmable and includes an output delay path (O Delay) and an input delay path (IDelay). The input direction of the output delay path (O Delay) is sequentially connected to an output parallel-to-serial converter (OSER) and a clock gating (CGA) unit. The output direction of the corresponding input delay path (I Delay) is sequentially connected to a clock distribution (CDA) unit and a deserializer (IDES). Furthermore, based on the encoding differences between the input and output signals, an 8-bit or 10-bit output parallel-to-serial converter (OSER) and deserializer (IDES) can be dynamically selected. An LVDS device interface consists of at least one data port and at most one on-path clock port. The maximum number of LVDS device interfaces depends on the amount of hardware resources of the FPGA used, including the phase-locked loop (PLL), low-voltage differential signal LVDS I / O, serializers (SERDES), and block random access memory (BRAM). The routing configuration module is used to connect the data buses of each source end and destination end in the internal switching network. Each LVDS device interface consists of one or more data ports plus an optional clock port. The path from each source end to the destination end is determined by the two-dimensional routing table SW_Table. Each valid bit in the two-dimensional routing table SW_Table is used to control the input signal of the corresponding row to drive the output of the corresponding column. The data caching module is used to buffer and forward data during master-slave data interaction. The cache FIFO in the data caching module is implemented by the block random access memory (BRAM) in the FPGA through IP core encapsulation, and each LANE port of each LVDS device interface is allocated a dedicated FIFO. The data transceiver module is used to forward data between the source port and the destination port. The data transceiver module receives data and clock sent by the master device through the LVDSRx interface. After buffering the data under the synchronous clock driven by the clock generation module, the data and the accompanying clock are transmitted to the LVDS Tx interface through the internal switching network. The system high-speed master clock SYS_CLK of the clock generation module is output after being multiplied by the system phase-locked loop (PLL) from an externally input stable reference clock. The reference clock for each LVDS device interface is determined by its own clock configuration parameters; The management interface module maps the I / O attributes of all ports, routing tables, clock trees of master and slave interfaces, and FIFO status data to a segment of address space in the form of registers. The registers are read and written through an external synchronous serial interface to realize parameter configuration and status reading.

2. The FPGA-based LVDS high-speed data switch according to claim 1, characterized in that: The IODelay unit is used to provide specific input / output delays to synchronize the phases of multiple LVDS LANEs and reduce the bit error rate; When the switch is operating in direct forwarding mode, uplink and downlink data do not need to be buffered; when operating in buffered mode, the data sent by the host is first stored in the buffer FIFO, and the data is output after being converted by the output parallel-to-serial converter OSER. At the same time, according to the configured slave-side encoding mode 10b / 8b selection signal, the output parallel-to-serial converter OSER10 or the output parallel-to-serial converter OSER8 is selected. The clock-gated CGA unit is used to generate special characters for control and indication, namely K codes.

3. The FPGA-based LVDS high-speed data switch according to claim 2, characterized in that: In buffered receive mode, the serial data input from the LVDS port is first cyclically detected by the clock distribution CDA unit to identify special control and synchronization characters. After alignment, the valid serial data is sent to the deserializer IDES for serial-to-parallel conversion. The converted data is then written into the receive buffer FIFO at the slave end. When the host-side encoding mode is 10-bit, its output data is decoded by a 10b / 8b decoder using a lookup table to obtain the target data.

4. The FPGA-based LVDS high-speed data switch according to claim 1, characterized in that: The switch supports 1:1 and 1:M transceiver port mapping relationships through the two-dimensional routing table SW_Table, and can also realize N:1 and N:M communication through time-division multiplexing by dynamically updating the routing table; the routing configuration module realizes the connection of the data bus between each source end and destination end in the internal switching network according to the two-dimensional routing table SW_Table.

5. The FPGA-based LVDS high-speed data switch according to claim 1, characterized in that: The FIFO states include Full, Almost_Full, Empty, and Almost_Empty. The state information is read by the management interface module and simultaneously fed back directly to the external IO port of the corresponding LVDS device interface. The FIFO data length thresholds corresponding to each state signal, namely Full_Len, Almost_Full_Len, Empty_Len, and Almost_Empty_Len, are configured through the management interface module.

6. The FPGA-based LVDS high-speed data switch according to claim 5, characterized in that: The data read / write port width of the FIFO is set to 8 bits, and the maximum depth of the FIFO is 65536 bytes; the status signal of the FIFO is led out to the host for data flow control on the host side.

7. The LVDS high-speed data switch based on FPGA according to claim 1, characterized in that: The LANE width of the transmitting end Tx and Rx in the LVDS device interface can be independently configured to any value of 1, 2, 4, or 8. When the LANE widths of the Tx and Rx ends are different, the Rx end adjusts its own FIFO read timing combination to ensure that the Tx end outputs correct data in the LANE.

8. The FPGA-based LVDS high-speed data switch according to claim 7, characterized in that: When there is a difference in the total data bandwidth of the devices connected to the Tx and Rx ends, the clock generation module and the data buffer module work together, and the host monitors the status signal of the FIFO to prevent data overflow.

9. The FPGA-based LVDS high-speed data switch according to claim 1, characterized in that: The accompanying reference clock of the LVDS device interface is a low-frequency clock, which is output by the clock generation module to the dedicated phase-locked loop (PLL) of the interface. The PLL multiplies the frequency to generate a reference clock that is 4 times or 5 times the frequency. The reference clock provides clock drive for the serializer SERDES, encoder, decoder, clock distribution unit (CDA), clock gating unit (CGA), and port data FIFO of the interface. When there is a difference in the LANE width between the LVDS master and slave interfaces, the phase-locked loop (PLL) performs corresponding frequency division or multiplication on the reference clock according to the ratio of the LANE width difference, so as to match the data transmission and reception rates of the master and slave ends.

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