Storage circuit, in-memory computing circuit with BCAM addressing and logical operation function

Abstract

The application relates to the technical field of static random access memory, in particular to a storage circuit and an in-memory computing circuit with BCAM addressing and logic operation functions. The storage circuit comprises NMOS tubes N1-N5 and PMOS tubes P0-P1; wherein N1-N4 and P0-P1 form a 6T-SRAM unit, N5 is connected between two MOS tubes corresponding to any one storage node of the 6T-SRAM unit, and the gate of N5 is controlled by a control signal line EN. Compared with the conventional 6T-SRAM, the storage circuit designed by the application adds one transistor for isolating the read port from the storage node, thereby improving the read damage problem of the 6T structure. Meanwhile, compared with the conventional 8T-SRAM with separated read and write, one transistor is saved, and the storage circuit has a greater advantage in area.

Description

Technical Field

[0001] This invention relates to the field of static random access memory (SRAM) technology, and in particular to a memory circuit, an in-memory computing circuit based on the memory circuit with BCAM addressing and logic operation functions, and a memory chip based on the memory circuit. Background Technology

[0002] To overcome the computational limitations imposed by the traditional von Neumann architecture, the concept of Computing In Memory (CIM) was proposed. CIM eliminates the need for frequent data transfers from memory to the processor, integrating computation directly within the memory array. This reduces intermediate data transfers and lightens the processor's workload. Another significant advantage of CIM is its ability to perform multi-row reads. Through multi-row read technology, the discharge level of the bit lines is linearly related to the amount of data stored. Simple logical operations are performed using bit line voltage, reducing the number of memory accesses and thus minimizing energy consumption while increasing data throughput. SRAM, widely used in cache applications, is increasingly accounting for a larger proportion of chip area and power consumption, making research on SRAM-based CIM particularly important.

[0003] Traditional 6T-SRAM features a cross-coupled inverter and two access transistors for read and write operations. During a read operation, bit lines BL and BLB are pre-charged to VDD, and word line WL is set to VDD for reading. The read path of 6T-SRAM is through the memory node to ground (GND), which typically causes read interference. A key technology for in-memory computing is multi-row read technology, which opens multiple rows simultaneously instead of a single word line during a read operation; while traditional 6T-SRAM can only read one row of data in a single data read operation.

[0004] To address the read interference problem, an 8T-SRAM structure with read coupling was proposed. This structure has the advantage of read-write separation. There are also 9T-SRAM and even 10T-SRAM cells with read-write separation to achieve in-memory computing. Compared with the traditional 6T-SRAM, these structures can improve the read interference problem, but the area is also increased accordingly. Summary of the Invention

[0005] Therefore, it is necessary to address the problem of existing SRAM cells sacrificing area to improve read interference by providing a storage circuit, an in-memory computing circuit based on the storage circuit with BCAM addressing and logic operation functions, and a storage chip based on the storage circuit.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A memory circuit includes NMOS transistors N1-N5 and PMOS transistors P0-P1. N1-N4 and P0-P1 constitute a 6T-SRAM cell. N5 is connected between two MOS transistors corresponding to any memory node in the 6T-SRAM cell, and the gate of N5 is controlled by the control signal line EN. The specific connection method of the memory circuit is as follows:

[0008] The gate of N1 is electrically connected to the drain of N2, the drain of N4, and the gate of P1. The drain of N1 is electrically connected to the drain of N3 and the source of N5. The source of N1 and the source of N2 are connected to GND. The gate of P2 is electrically connected to the drain of P1, the gate of N2, and the drain of N5. The drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1. The source of P1 and the source of P2 are connected to VDD. The gate of N3 is connected to the right word line WLR, the gate of N4 is connected to the left word line WLL, and the gate of N5 is electrically connected to the external control signal line EN. The source of N3 is connected to the bit line BLB, and the source of N4 is connected to the bit line BL.

[0009] In this circuit, P2 and N2 form an inverter, and N3 and N4 form the transmission transistors of the memory circuit. Memory node Q is connected to bit line BL through N4, and memory node QB is connected to bit line BLB through N5 and N3.

[0010] Furthermore, the storage circuit implements SRAM mode including hold, write, and read operations. During a hold operation, the control signal line EN remains high, the left word line WLL and right word line WLR remain low, and the latch structure composed of P1, P2, N1, N2, and N5 latches the stored data in storage nodes Q and QB. During a write operation, the control signal line EN remains high, the left word line WLL and right word line WLR are pulled high, and the data to be written is loaded onto the write bit line. During a read operation, the bit line BLB is precharged high, the control signal line EN is low, the left word line WLL is pulled low, the right word line WLR remains high, and the result is read by the sensitive amplifier SA.

[0011] This invention also relates to an in-memory computing circuit with BCAM addressing and logic operation functions, which consists of an N×M array of multiple identical memory cells. Here, N is the number of rows of memory cells, and M is the number of columns of memory cells. Each row of memory cells shares the left word line WLL and the right word line WLR. Each column of memory cells shares the bit lines BL and BLB.

[0012] The storage unit adopts the circuit structure of the aforementioned storage circuit and implements the complete function of the circuit structure.

[0013] Furthermore, all bit lines BL and BLB are connected one-to-one with a sensitivity amplifier. In each column of memory cells, bit line BL or BLB serves as one input to a sensitivity amplifier, with the other input being a reference voltage. When the level of BL or BLB is higher than the reference voltage, the sensitivity amplifier outputs a high level; otherwise, it outputs a low level.

[0014] Furthermore, the bit lines BL and BLB of each column of memory cells are connected to an AND gate via single-ended sensitive amplifiers. The outputs of the two single-ended sensitive amplifiers serve as the two inputs of an AND gate. When the outputs of both sensitive amplifiers are high, the AND gate outputs a high level; otherwise, it outputs a low level.

[0015] Furthermore, when the in-memory computing circuit performs in-memory Boolean logic operations, the output of the sensitive amplifier connected to the bit line BLB serves as the output of the operation. When the in-memory computing circuit performs BCAM operations, the output of the AND gate serves as the output of the operation. When the in-memory computing circuit performs multiplication operations, the discharge amount of the bit line BLB is the result of the multiplication operation. Furthermore, the in-memory computing circuit implements in-memory Boolean logic operations as follows: the left word line WLL and control signal line EN of the same column of memory cells are kept low, the right word line WLR of the memory cell to be involved in the in-memory Boolean logic operation is set high, and the remaining word lines are set low. The voltage on the bit line BLB is compared with a reference voltage by the sensitive amplifier, and the corresponding in-memory Boolean logic operation result is output.

[0016] Furthermore, the in-memory computing circuit implements BCAM operations as follows: the control signal line EN of the same column of memory cells is kept low; the voltage signal corresponding to the search data and its opposite signal are input to the memory cell containing the data to be searched through the left word line WLL and the right word line WLR, respectively; the voltage signals of the bit lines BL and BLB, which represent the operation results, are output through two single-ended sensitive amplifiers and an AND gate; the output of the AND gate is high, indicating that the search data matches the data to be searched; the output of the AND gate is low, indicating that the search data does not match the data to be searched.

[0017] Furthermore, the in-memory computing circuit implements multiplication operations as follows:

[0018] Keep the control signal line EN and the left word line WLL of the same column of memory cells low, and input the voltage signal corresponding to the multiplier to the memory cell with the multiplier through the right word line WLR. The required multiplication result is obtained according to the discharge amount of the bit line BLB.

[0019] This invention also relates to a memory chip, which is packaged using the aforementioned memory circuit. The memory chip has the following pins:

[0020] The ground pin is connected to the source of PMOS transistors P1 and P2.

[0021] The power supply pin is connected to the source of NMOS transistors N1 and N2.

[0022] The first pin is connected to the source of the NMOS transistor N4.

[0023] The second pin is connected to the source of NMOS transistor N3.

[0024] The third pin is connected to the gate of NMOS transistor N4.

[0025] The fourth pin is connected to the gate of NMOS transistor N3.

[0026] The technical solution provided by this invention has the following beneficial effects:

[0027] 1. Compared with the traditional 6T-SRAM, the storage circuit designed in this invention adds one transistor to isolate the read port from the storage node, thereby improving the read corruption problem of the 6T structure. At the same time, compared with the traditional read-write separated 8T-SRAM, it has one less transistor, resulting in a greater area advantage.

[0028] 2. The array-distributed in-memory computing circuit designed in this invention can perform normal SRAM modes of holding, reading and writing, and can also perform simple Boolean logic operations, BCAM addressing operations and multiplication operations, thereby meeting a variety of computing needs. Attached Figure Description

[0029] Figure 1 This is a circuit diagram of the storage circuit according to Embodiment 1 of the present invention;

[0030] Figure 2 This is a circuit diagram illustrating the AND and NOT operations performed by two rows of storage cells in Embodiment 2 of the present invention.

[0031] Figure 3 For based on Figure 2 Simulation results of AND and NOT operations;

[0032] Figure 4 This is a circuit diagram illustrating the OR and OR NOT operations performed by two rows of memory cells in Embodiment 2 of the present invention.

[0033] Figure 5 For based on Figure 4 Simulation results of OR and NOR operations;

[0034] Figure 6 This is a schematic diagram of BCAM addressing in Embodiment 2 of the present invention, using a 4×4 memory cell as an example;

[0035] Figure 7 For based on Figure 6 Simulation results of BCAM addressing;

[0036] Figure 8 This is a circuit structure diagram of Embodiment 2 of the present invention for performing a 4-bit × 1-bit binary multiplication operation;

[0037] Figure 9 For based on Figure 8 The simulation results of performing a 4-bit × 1-bit binary multiplication operation are shown in the figure.

[0038] Figure 10 For based on Figure 8 Linearity variation graph of 4-bit × 1-bit binary multiplication results. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Example 1

[0041] Please see Figure 1 , Figure 1 This embodiment illustrates a memory circuit including NMOS transistors N1-N5 and PMOS transistors P0-P1. N1-N4 and P0-P1 constitute a 6T-SRAM cell. N5 is connected between the two MOS transistors corresponding to any memory node in the 6T-SRAM cell, and the gate of N5 is controlled by the control signal line EN. The specific connection method of the memory circuit is as follows:

[0042] The drain of N2 is electrically connected to the gate of N1, and the source of N2 is electrically connected to the source of N1. The gate of N3 is electrically connected to the right word line WLR, the drain of N3 is electrically connected to the drain of N1, and the source of N3 is electrically connected to the bit line BLB. The gate of N4 is electrically connected to the right word line WLL, the drain of N4 is electrically connected to the drain of N2 and the gate of N1, and the source of N4 is electrically connected to the bit line BL. The gate of N5 is electrically connected to the external control signal EN, the drain of N5 is electrically connected to the gate of N2, and the source of N5 is electrically connected to the drain of N1 and the drain of N3. The gate of P1 is electrically connected to the gate of N1, the drain of N2, and the drain of N4, and the drain of P1 is electrically connected to the gate of N2 and the drain of N5. The gate of P2 is electrically connected to the gate of N2 and the drain of N5. The drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1. The source of P1 is electrically connected to the source of P2.

[0043] An NMOS transistor N5 is added between the drains of P1 and N1 in the right half of the circuit. The gate of N5 is controlled by the external control signal line EN. P2 and N2 in the left half form an inverter. When N5 is turned on, the data stored in the storage nodes Q and QB are latched on both sides. The sources of transistors P1 and P2 are electrically connected to VDD, enabling the power supply path of storage nodes Q and QB. The sources of transistors N1 and N2 are electrically connected to GND, enabling the ground path of storage nodes Q and QB. When N5 is turned off, transistors P1 and N1 are disconnected. At this time, the gate of N1 is controlled by Q, and the drain of N1 is no longer directly affected by QB. Transistor N3 is controlled by the word line WLR, and transistors N1 and N3 are connected to the right bit line BLB. When both transistors N1 and N3 are turned on, the right bit line BLB can form a path to ground. By controlling the conduction level of transistors N1 and N3, the discharge amount of the right bit line BLB can be controlled. Different calculation modes can be realized using this principle.

[0044] Storage node Q is connected to bit line BL through transistor N4, and storage node QB is connected to bit line BLB through transistors N5 and N3. N4 and N3 are transmission transistors located on the left and right sides of the structure as two paths, which are controlled by the left word line WLL and the right word line WLR, respectively.

[0045] The circuit in this embodiment is a 7T-SRAM composed of 7 transistors. Compared to the traditional 6T-SRAM, the read port is isolated from the memory node, thus improving the read corruption problem of the 6T structure. Compared to the traditional read-write separated 8T-SRAM, it has one less transistor, giving it a greater advantage in area.

[0046] The specific operation of the storage circuit in SRAM mode according to this embodiment will be described below. In SRAM mode, operations include hold, write, and read operations, and the specific operation steps are as follows:

[0047] (1) Maintaining mode

[0048] During data retention, the external control signal line EN remains high, the left word line WLL and the right word line WLR remain low, NMOS transistors N3 and N4 are off, and N5 is on. The latch structure formed by PMOS transistors P1 and P2 and NMOS transistors N1, N2, and N5 latches the values ​​of memory nodes Q and QB. Changes in bit lines BL and BLB do not affect memory nodes Q and QB.

[0049] (2) Write operation

[0050] During the write operation, the external control signal line EN, the left word line WLL, and the right word line WLR remain at a high level, and the NMOS transistors N3, N4, and N5 are all turned on, loading the data to be written onto the write bit lines.

[0051] Assuming that before the write operation, memory node Q is high and QB is low, meaning the stored data is "1", when writing data "0", the data to be written, "0", is loaded onto the write bit line, i.e., BL is low and BLB is high. BL pulls down memory node Q through NMOS transistor N2, and BLB pulls up memory node QB through PMOS transistor P1. The feedback mechanism of the latch structure is broken, and the data "0" is written into the memory circuit.

[0052] Assuming that before the write operation, storage node Q is low and QB is high, meaning the stored data is "0", when writing data "1", the data to be written is loaded onto the write bit line, i.e., BL is high and BLB is low. BL pulls up storage node Q through P2, and BLB pulls down storage node QB through N1. The feedback mechanism of the latch structure is broken, and the data "1" is written into the storage circuit.

[0053] (3) Read operation

[0054] During the read operation, the external control signal line EN and the left word line WLL are at a low level, the right word line WLR is at a high level, NMOS transistors N4 and N5 are turned off, and NMOS transistor N3 is turned on, i.e., a single-sided read operation is performed.

[0055] Assuming that before the read operation, the storage node Q is at a high level and QB is at a low level, that is, the stored data is "1", at the start of the read operation, the bit line BLB is precharged to a high level, the storage node Q controls the gate of N1, when Q is at a high level N1 is turned on, the bit line BLB is discharged to a low level through NMOS transistors N3 and N1, and the operation of reading "1" is completed through the sensitive amplifier SA.

[0056] Assuming the storage node Q is low and QB is high, that is, when the stored data Q is "0", at the start of the read operation, the bit line BLB is also precharged to a high level. When the storage node Q is low, the NMOS transistor N1 is turned off, the bit line BLB cannot discharge and remains at a high level. The operation of reading "0" is completed through the sensitive amplifier SA.

[0057] Based on this, the truth table for implementing SRAM mode is shown in the table below, where L represents low level, H represents high level, Read represents read operation, Write represents write operation, and Hold represents hold state.

[0058] Table 1: SRAM Truth Table

[0059]

[0060] Therefore, the storage circuit in this embodiment not only improves read interference by spacing the read port and the storage node Q, but also reduces the area occupied while improving read interference compared to 8T-SRAM, 9T-SRAM, and 10T-SRAM. Thus, it offers a significant area advantage compared to existing structures designed to improve read interference.

[0061] Example 2

[0062] This embodiment introduces an in-memory computing circuit with BCAM addressing and logic operation functions, which consists of multiple identical memory cells forming an N×M array; where N is the number of rows of memory cells and M is the number of columns of memory cells; each row of memory cells shares the left word line WLL and the right word line WLR; each column of memory cells shares the bit lines BL and BLB; the memory cells adopt the circuit structure of the aforementioned memory circuit and implement the complete function of the circuit structure.

[0063] The number of sensitive amplifiers is the same as the number of bit lines. In each column of memory cells, bit line BL or BLB serves as one input to a sensitive amplifier, and the other input to the sensitive amplifier is a reference voltage. When the level of BL or BLB is higher than the reference voltage, the sensitive amplifier outputs a high level; otherwise, it outputs a low level. The number of AND gates is half the number of columns of memory cells. In each column of memory cells, the outputs of two sensitive amplifiers serve as the two inputs to an AND gate. When both outputs of the sensitive amplifiers are high, the AND gate outputs a high level; otherwise, it outputs a low level.

[0064] Based on the aforementioned circuit, this embodiment can not only implement SRAM mode functionality, but also, based on the interaction between different columns and rows, implement in-memory Boolean logic operations, BCAM addressing, and multiplication operations. The implementation methods for these operations are described in detail below.

[0065] I. In-store Boolean logic operations

[0066] When performing in-memory Boolean logic operations, the left word line WLL and control signal line EN of the same column of memory cells are kept at a low level, the right word line WLR of the memory cell to be involved in the in-memory Boolean logic operation is set to a high level, and the remaining word lines are set to a low level; the voltage on the bit line BLB is compared with a reference voltage by the sensitive amplifier SA, and the corresponding in-memory Boolean logic operation result is output.

[0067] like Figure 2 As shown, this paper uses the logical AND and NAND functions of two 1-bit stored data as an example to illustrate how to implement AND and NAND functions between two rows in the same column.

[0068] The left word lines WLL of two memory cells and the external control signal line EN are always at a low potential. Therefore, the NMOS transistors N4 and N5 are always in the off state. The memory cells of two rows are respectively marked as A and B. The word lines of row A are denoted as WLL0 and WLR0, and the word lines of row B are denoted as WLL1 and WLR1. A and B share the bit lines BL and BLB. Whether the right word line WLR is turned on determines whether the corresponding row participates in the operation, and a sense amplifier SA is configured for it. The other end of SA is connected to the reference voltage VREF1. The sense amplifier compares the voltage of the bit line BLB with the reference voltage VREF1, and then outputs the logical AND and NAND operation results of A and B.

[0069] The bit line BLB is precharged to a high level, and at the same time, the right word lines WLR0 and WLR1 of the two cells are turned on, that is, WLR0 and WLR1 are at a high level. When the data stored in the cell is "1", that is, Q is at a high level and QB is at a low level, a conduction path to the ground is formed between the bit line BLB and GND, and the charge on BLB flows to GND. At this time, the bit line BLB discharges. When the stored data in A or B is 1, the discharge speed of the bit line BLB is the same. When the stored data in both A and B is 1, the discharge speed of BLB is faster. By using the different discharge speeds of the bit lines when the stored data in both cells is "1" and only one cell stores data "1" within the same time, the reference voltage VREF1 of the sense amplifier SA is set, that is, the reference voltage VREF1 of the sense amplifier SA is located between the bit line voltages after the discharge of the two cells and the bit line voltage after the discharge of one cell within the same time. If VBLB > VREF1, at least one of A and B stores data "0" or both store "0". If VBLB < VREF1, the data stored in A and B are both "1".

[0070] Since the principle of the AND operation is that a high level is output only when both operands are at a high level, and the NAND operation is that a low level is output only when both operands are at a high level. Therefore, in this embodiment, a simulation experiment is carried out. Figure 3 It can be seen from the simulation results that when and only when both the upper and lower cells discharge, the output of the sense amplifier is "0", and in other cases, the output is "1", outputting the NAND operation result of A and B. The output at the other end of the sense amplifier SA is opposite to the output at this end, outputting the AND operation result of A and B. The principle of the AND and NAND operations between multiple rows is the same as that between two rows.

[0071] As Figure 4 shown, taking the logical OR and NOR of two 1-bit stored data as an example, the realization of the OR and NOR functions of the stored data between two rows in the same column is introduced.

[0072] The setting conditions for the AND-OR-NOT operation between A and B are the same as those for the AND and NAND operations. The difference is that when A and B perform the OR and OR-NOT operations, one end of SA is connected to the bit line BLB and the other end is connected to the reference voltage VREF2. SA compares the voltage of the bit line BLB with the reference voltage VREF2 and outputs the results of the logical OR and OR-NOT operations of A and B.

[0073] First, pre-charge the bit line BLB to a high level. At the same time, activate the right word lines WLR0 and WLR1 of the two cells. When any or all of the stored data in the cell is "1", that is, Q is 1 and QB is 0, a conduction path to the ground is formed between the bit line BLB and GND, and the charge on the bit line BLB flows towards GND, discharging the bit line BLB. The principle that the bit line BLB does not discharge when the stored data in both the A row and the B row is at a low level and the bit line BLB discharges when there is a high-level stored data in either A or B is used for judgment. The reference voltage VREF2 of SA is between the bit line voltage when it does not discharge and the bit line voltage after one cell discharges. If VBLB > VREF2, the stored data of both A and B is "0"; if VBLB < VREF2, at least one of the stored data in A or B is "1" or both are "1".

[0074] Since the principle of the OR operation is that only when both operands are at a low level will a low level be output, and the principle of the OR-NOT operation is that only when both operands are at a low level will a high level be output, therefore, in this embodiment, a simulation experiment is carried out. From Figure 5 the simulation results, it can be seen that only when the stored data in both cells is "0", that is, when the right bit line BLB in both cells does not discharge to the ground, BLB remains at a high level and the output result of SA is "1". When the stored data in any one cell is "1", that is, when the right bit line BLB in any one cell discharges to the ground, the output result of SA is "0". At this time, the reference voltage VREF2 of SA is between the bit line voltage when it does not discharge and the bit line voltage after one cell discharges. Then, one end of the sense amplifier SA outputs the OR-NOT operation result of A and B, and the other end outputs the opposite, outputting the OR operation result of A and B. The principles of the OR and OR-NOT operations between multiple rows are the same as those between two rows.

[0075] Based on this, the in-memory computing circuit of this embodiment can implement logical operations AND and NAND operations, OR and OR-NOT operations; it should be emphasized that the two output terminals of the sense amplifier output opposite results. The output terminal on the same side as the input terminal connected to the bit line BLB outputs the NAND or OR-NOT result, and the output terminal on the same side as the input terminal connected to the reference voltage outputs the AND or OR result.

[0076] The truth table for implementing logical AND and NAND, OR and NOR modes between two rows in the same column in Boolean logic operations is shown in the table below, where A represents the stored data in row A, B represents the stored data in row B, L represents low level, and H represents high level.

[0077] Table 2: Truth Table for In-Store Boolean Logic Operations

[0078]

[0079] II. BCAM Addressing Operations

[0080] The control signal line EN of the same column of memory cells is kept low; the voltage signal corresponding to the search data and its opposite signal are input to the memory cell containing the data to be searched through the left word line WLL and the right word line WLR, respectively; the matching result is represented by two single-ended sensitive amplifiers SA and an AND gate output. A high level output from the AND gate indicates a match; a low level output from the AND gate indicates a mismatch.

[0081] like Figure 6 As shown, in BCAM operation mode, the external control signal line EN is always low, that is, the NMOS transistor N5 is in the off state. The binary data to be searched is stored in the Q node inside the memory cell. The search line is the left word line WLL, which is the high or low level corresponding to the binary data of the search data. The right word line WLR is the high or low level corresponding to the inverse code of the binary data of the search data. When the data is "1", the corresponding word line is set to high level, and when the data is "0", the corresponding word line is set to low level. The lower ends of the left and right bit lines BL and BLB are each connected to a sensitive amplifier SA. The outputs of the two SA are connected to an AND gate. The output of the AND gate indicates whether there is a match. Before data lookup, the storage unit stores the binary data to be searched. The left and right bit lines BL and BLB are precharged to high level. The left and right word lines are set to high or low level respectively according to the search data. Then, the bit lines are controlled to discharge according to whether the data to be searched matches the search data. If they match, they do not discharge; otherwise, they discharge. Only when neither the left nor right bit lines of the column discharge, the output of the sensitive amplifier SA is high level. The output after passing through the AND gate is high level, indicating a match. Otherwise, the output of the AND gate is low level, indicating a mismatch.

[0082] The following analysis examines the data comparison process. When the search data is "0", the left word line WLL is low, NMOS transistor N4 is off, BL cannot discharge and remains high. At this time, the right word line WLR is high, NMOS transistor N3 is on. Assuming the memory node Q is "0", the gate of NMOS transistor N1 is turned off, the discharge path of BLB is cut off, and BLB does not discharge. This indicates that neither bit line BL nor BLB discharges, and the data in this cell is matched. Assuming the memory node Q is "1", the gate of NMOS transistor N1 is turned on, and BLB discharges. In this case, bit line BL does not discharge, but bit line BLB discharges, and the data in this cell is not matched. Similarly, when the search data is "1", the right word line WLR is low, NMOS transistor N3 is off, and BLB cannot discharge, remaining at a high level. At this time, the left word line WLL is high, and NMOS transistor N3 is on. Assuming that memory node Q is "0" and memory node QB is "1", the gate of N2 controls NMOS transistor N2 to turn on, and BL discharges. In this case, bit line BLB does not discharge, but bit line BL discharges, resulting in a data mismatch in this cell. Assuming that memory node Q is "1" and memory node QB is "0", the gate of N2 controls NMOS transistor N2 to turn off, and BL does not discharge. In this case, neither bit line BL nor BLB discharges, resulting in a data match in this cell.

[0083] Combination Figure 6 Taking BCAM operation with 4×4 memory cells as an example, the four pairs of word lines in the first to fourth rows are denoted as WLL0, WLR0; WLL1, WLR1; WLL2, WLR2; WLL3, WLR3, respectively. The four pairs of bit lines in the first to fourth columns are denoted as BL0, BLB0; BL1, BLB1; BL2, BLB2; BL3, BLB3, respectively. To more clearly demonstrate the technical solution provided by this invention and its resulting technical effects, a column search is taken as an example using four-bit binary data "0011", where the search data is "0011", "0" is low level, and "1" is high level. Therefore, the left word lines WLL0, WLL1, WLL2, and WLL3 are set to low level, low level, high level, and high level, respectively, and the right word lines WLR0, WLR1, WLR2, and WLR3 are set to high level, high level, low level, and low level, respectively. The array has four columns, and the data stored in each column from left to right are "0111", "0011", "1011", and "1101" respectively.

[0084] Based on the above analysis, the data stored in the first column is "0111". Although the data stored in the second row is "1", the left word line WLL1 is at a low level and is in the off state. Therefore, the left word line BL0 does not discharge, and SA outputs "1". However, the right word line WLR1 is in the opposite state to the left word line WLL1. Therefore, the right word line WLR1 is at a high level, and the transmission transistor N3 is turned on. At this time, BLB0 discharges, and SA outputs "0". The result of the two SAs is "0" after being ANDed by the gate. Therefore, the data stored in the first column does not match the search data.

[0085] The data stored in the second column is "0011". At this time, neither bit line BL1 nor BLB1 discharges, and both SA outputs are "1". After passing through an AND gate, the output is "1", so the second column matches the search data.

[0086] The data stored in the third column is "1011". Although the data "1" stored in the first row does not match the search data, the left word line WLL0 is at a low level and is in the off state. Therefore, the left bit line BL2 does not discharge, and SA outputs "1". However, the right word line WLR0 is in the opposite state to the left word line WLL0. At this time, WLR0 is at a high level, the transmission tube N3 is turned on, the right bit line BLB2 discharges, and SA outputs "0". The result of the two SAs is "0" after being ANDed by the gate. Therefore, the data stored in the third column does not match the search data.

[0087] The data stored in the fourth column is "1101". The data stored in the first, second, and third rows are different from the search data. However, since the left word lines WLL0 and WLL1 of the first and second rows are at a low level, the transmission transistor N4 is not turned on, which does not affect the left word line BL3. The left word line WLL2 of the third row is at a high level, the transmission transistor N4 is turned on, BL3 is discharged, and SA outputs "0". The right word lines WLR0, WLR1, and WLR2 are opposite to the left word lines WLL0, WLL1, and WLL2. The transmission transistor N4 of the first and second rows is turned on, the right word line BLB3 is discharged, and SA outputs "0". The result of the two SAs is "0" after being ANDed by an AND gate. Therefore, the data stored in the fourth column does not match the search data.

[0088] Ultimately, it was found that only the second column matched the search data. For example... Figure 7 Simulation results from BCAM show that when all four cells in a column match, neither the left nor right bit lines BL nor BLB discharges, thus maintaining a high level. BL and BLB then output a high level after passing through two sensitive amplifiers and an AND gate, indicating that the search data matches the data to be found. Conversely, when there are cells in a column with mismatched data, one of the left or right bit lines BL or BLB will discharge. BL and BLB then output a low level after passing through two sensitive amplifiers and an AND gate, indicating that the search data does not match the data to be found.

[0089] III. Multiplication Operations

[0090] The left word line WLL and the external control signal EN are kept low. The multiplicand is represented by different voltages operating on the right word line WLR. The multiplier is stored inside the memory cell, and its multiplication output is represented by the discharge amount on the right bit line BLB. Each memory cell performs a 2-bit × 1-bit multiplication in each calculation stage. The 2-bit multiplicand is applied to the right word line WLR, which is achieved by converting the multiplicand into a word line voltage. The multiplier operates inside the memory cell.

[0091] Please see Figure 8 To illustrate how this embodiment implements the function, we will take the implementation of 4-bit × 1-bit binary multiplication as an example. To implement 4-bit × 1-bit binary multiplication, only two units that implement 2-bit × 1-bit binary multiplication need to discharge through a single bit line.

[0092] First, we assume that a single storage unit can perform binary multiplication with a 2-bit multiplicand and a 1-bit multiplier. The 2-bit multiplicand is "00", "01", "10", and "11", which correspond to the voltages 0, 10, 11, and 11 of the four WLRs, respectively. WLR1 V WLR2 V WLR3 Different voltages on the right word line are applied to the gate of NMOS transistor N3. At the same time, different gate voltages control the NMOS transistor to conduct at different degrees, resulting in different current flows. This distinguishes the multiplicands with different weights. The binary multiplier is either "0" or "1" and is stored in node Q within the memory cell. First, the bit line BLB is pre-charged. When the binary multiplier is "0", the discharge on the bit line BLB is always zero, regardless of the gate voltage of transistor N3. When the binary multiplier is "1", NMOS transistor N1 is turned on. At this time, the discharge on the bit line BLB depends on the gate voltage of transistor N3, thus achieving the purpose of distinguishing the results of a 2-bit × 1-bit binary multiplication operation.

[0093] The truth table for implementing 2-bit × 1-bit binary multiplication is shown in the table below, where X represents any 2-bit data and its corresponding word line voltage.

[0094] Table 3: Truth Table of 2-bit × 1-bit Binary Multiplication Results

[0095]

[0096] Two units performing a 2-bit × 1-bit binary multiplication operation achieve a 4-bit × 1-bit binary multiplication operation by discharging through a single bit line. The distinction between the high 2 bits and the low 2 bits can be achieved using techniques such as transistor size weighting, capacitor array weighting, and pulse number / height / width weighting. In this explanation, pulse width modulation (PWM) is used as an example. Other techniques operate similarly to PWM, pre-charging the bit line (BLB) to a high level and obtaining different weighted currents based on different multiplicands and multipliers.

[0097] The truth table for implementing 4-bit × 1-bit binary multiplication is shown in the table below, where X represents any 4-bit data.

[0098] Table 4: Truth Table of 4-bit × 1-bit Binary Multiplication Results

[0099]

[0100] Figure 9 This diagram illustrates the result of a 4-bit × 1-bit binary multiplication operation. An external computing capacitor is connected to the bit line (BLB) to convert the weighted current into a weighted voltage. This voltage is then converted to an analog-to-digital converter (ADC) to obtain the binary number representing the result of the 4-bit × 1-bit binary multiplication operation. Therefore, the in-memory computing circuit in this embodiment can obtain 16 multiplication results for a 4-bit × 1-bit binary multiplication operation.

[0101] The present invention distinguishes the multiplication results by different discharge amounts on the bit line. The linearity between different discharge amounts on the bit line can be measured by the change in bit line voltage and the integral nonlinearity (INL). Figure 10 The measured INL value is obtained from... Figure 9 It can be seen that the linearity is worst when the multiplication result is 9, at which point the INL value is 0.62 LSB, but the INL value is still relatively small, indicating good linearity. Therefore, this embodiment can effectively implement 4-bit × 1-bit binary multiplication operations.

[0102] In summary, the in-memory computing circuit of this embodiment not only has the same effects as Embodiment 1, but also allows for full array operations within the array constructed based on Embodiment 1. Furthermore, it can perform simple Boolean logic operations, BCAM addressing operations, and 4-bit × 1-bit binary multiplication operations, satisfying various operational needs.

[0103] Example 3

[0104] This embodiment introduces a memory chip, packaged using the aforementioned memory circuit. The memory chip has the following pins: a ground pin connected to the sources of PMOS transistors P1 and P2; a power supply pin connected to the sources of NMOS transistors N1 and N2; a first pin connected to the source of NMOS transistor N4; a second pin connected to the source of NMOS transistor N3; a third pin connected to the gate of NMOS transistor N4; and a fourth pin connected to the gate of NMOS transistor N3.

[0105] Encapsulating storage circuits into chips makes them easier for those skilled in the art to use and facilitates the promotion and use of storage circuits.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A storage circuit, characterized in that, It includes NMOS transistors N1~N5 and PMOS transistors P1~P2; wherein, N1~N4 and P1~P2 constitute a 6T-SRAM cell, and N5 is connected between the two MOS transistors corresponding to any storage node of the 6T-SRAM cell, and the gate of N5 is controlled by the control signal line EN; the specific connection method of the storage circuit is as follows: The gate of N1 is electrically connected to the drain of N2, the drain of N4, and the gate of P1; the drain of N1 is electrically connected to the drain of N3 and the source of N5; the source of N1 and the source of N2 are connected to GND; the gate of P2 is electrically connected to the drain of P1, the gate of N2, and the drain of N5; the drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1; the source of P1 and the source of P2 are connected to VDD; the gate of N3 is connected to the right word line WLR, the gate of N4 is connected to the left word line WLL, the gate of N5 is electrically connected to the external control signal line EN; the source of N3 is connected to the bit line BLB, and the source of N4 is connected to the bit line BL; In this circuit, P2 and N2 form an inverter, and N3 and N4 form the transmission transistors of the storage circuit. Storage node Q is connected to bit line BL through N4, and storage node QB is connected to bit line BLB through N5 and N3. The storage circuit implements SRAM mode including hold, write, and read operations. During a hold operation, the control signal line EN remains high, the left word line WLL and right word line WLR remain low, and the latch structure composed of P1, P2, N1, N2, and N5 latches the data stored in storage nodes Q and QB. During a write operation, the control signal line EN remains high, the left word line WLL and right word line WLR are pulled high, and the data to be written is loaded onto the bit line. During a read operation, the bit line BLB is precharged high, the control signal line EN is low, the left word line WLL is pulled low, the right word line WLR remains high, and the result is read by the sensitive amplifier SA.

2. An in-memory computing circuit with BCAM addressing and logic operation functions, comprising an N×M array of multiple identical memory cells; wherein, N is the number of rows of storage units, and M is the number of columns of storage units; each row of storage units shares the left word line WLL and the right word line WLR; each column of storage units shares the bit lines BL and BLB; The characteristic feature is that the storage unit adopts the circuit structure of the storage circuit as described in claim 1, and realizes the complete function of the circuit structure.

3. The in-memory computing circuit with BCAM addressing and logic operation functions according to claim 2, characterized in that, All bit lines BL and BLB are connected to the sensitive amplifier in a one-to-one correspondence; in each column of memory cell, bit line BL or BLB serves as one input of a sensitive amplifier, and the other input of the sensitive amplifier is the reference voltage; when the level of BL or BLB is higher than the reference voltage, the sensitive amplifier outputs a high level, otherwise it outputs a low level.

4. The in-memory computing circuit with BCAM addressing and logic operation functions according to claim 2, characterized in that, The bit lines BL and BLB of each column of memory cells are connected to an AND gate through a single-ended sensitive amplifier; the outputs of the two single-ended sensitive amplifiers are respectively used as the two inputs of an AND gate; when the outputs of the two sensitive amplifiers are both high, the AND gate outputs a high level, otherwise it outputs a low level.

5. The in-memory computing circuit with BCAM addressing and logic operation functions according to claim 3 or 4, characterized in that, When the in-memory computing circuit performs in-memory Boolean logic operations, the output terminal of the sensitive amplifier connected to the bit line BLB is used as the output terminal of the operation; when the in-memory computing circuit performs BCAM operations, the output terminal of the AND gate is used as the output terminal of the operation; when the in-memory computing circuit performs multiplication operations, the discharge amount of the bit line BLB is the result of the multiplication operation.

6. The in-memory computing circuit with BCAM addressing and logic operation functions according to claim 5, characterized in that, The in-memory computing circuit implements in-memory Boolean logic operations in the following way: Keep the left word line WLL and control signal line EN of the same column of memory cells low, set the right word line WLR of the memory cell to be involved in the in-memory Boolean logic operation to high, and set the remaining word lines to low; after the sensitive amplifier compares the voltage on the bit line BLB with a reference voltage, the corresponding in-memory Boolean logic operation result is output.

7. The in-memory computing circuit with BCAM addressing and logic operation functions according to claim 5, characterized in that, The in-memory computing circuit implements BCAM operations in the following way: Keep the control signal line EN of the same column of memory cells low; input the voltage signal corresponding to the search data and its opposite signal to the memory cell containing the data to be searched through the left word line WLL and the right word line WLR, respectively; output the voltage signals of the bit lines BL and BLB representing the operation result through two single-ended sensitive amplifiers and an AND gate; output a high level at the output of the AND gate, indicating that the search data matches the data to be searched; output a low level at the output of the AND gate, indicating that the search data does not match the data to be searched.

8. The in-memory computing circuit with BCAM addressing and logic operation functions according to claim 5, characterized in that, The in-memory computing circuit implements multiplication operations in the following way: Keep the control signal line EN and the left word line WLL of the same column of memory cells low, and input the voltage signal corresponding to the multiplier to the memory cell with the multiplier through the right word line WLR. The required multiplication result is obtained according to the discharge amount of the bit line BLB.

9. A memory chip, characterized in that, It is packaged using the storage circuit as described in claim 1; the pins of the storage chip include: The power supply pin is connected to the source of PMOS transistors P1 and P2. The ground pin is connected to the source of NMOS transistors N1 and N2; The first pin is connected to the source of NMOS transistor N4; The second pin is connected to the source of NMOS transistor N3; The third pin is connected to the gate of NMOS transistor N4; The fourth pin is connected to the gate of NMOS transistor N3.

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