Circuit board and method of manufacturing the same

Abstract

A circuit board includes a first conductive layer on an outer side, the first conductive layer including a plurality of first connection pads. An insulating bump is protruded on each first connection pad, a surface of the bump is coated with a metal layer, and the metal layer is connected with the first connection pad. A manufacturing method of the circuit board is also provided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit board, in particular to a circuit board with conductive pillars and a manufacturing method thereof. BACKGROUND

[0002] The surface of a circuit board has a plurality of pads for soldering with various electronic components (such as chips). In the trend of high density, the pads are getting smaller and smaller. In order to improve the soldering yield and reliability, a method of using copper pillars instead of pads for soldering is proposed. The copper pillars protrude from the conductive layer on the surface of the circuit board and are formed by electroplating. However, in industrial production, the uniformity of electroplating is poor due to the limitations of electroplating equipment (such as traditional gantry or vertical continuous electroplating equipment) and chemicals. Moreover, due to the uneven distribution of nodes forming the copper pillars on the surface of the circuit board, the current density distribution during electroplating is uneven, resulting in a large difference in the height of the plurality of copper pillars formed by electroplating, which cannot meet the packaging requirements. SUMMARY

[0003] Therefore, the present application provides a manufacturing method of a circuit board and a circuit board manufactured by the method.

[0004] The first aspect of the present application provides a circuit board, comprising a first conductive layer on the outer side, wherein the first conductive layer comprises a plurality of first connection pads. An insulating bump is protruded on each first connection pad, and the surface of the bump is coated with a metal layer, wherein the metal layer is connected with the first connection pad.

[0005] The second aspect of the present application provides a manufacturing method of a circuit board, comprising the following steps:

[0006] providing a circuit substrate comprising a first metal layer on the outer side;

[0007] forming an insulating layer on the first metal layer;

[0008] removing part of the insulating layer to form a plurality of insulating bumps;

[0009] forming a metal layer on the surface of the bump, wherein the metal layer is connected with the first metal layer;

[0010] performing line manufacturing on the first metal layer to form a first conductive layer, wherein the first conductive layer comprises a plurality of first connection pads, and each first connection pad is connected with a corresponding metal layer.

[0011] The circuit board and the manufacturing method thereof provided by the present application, by removing part of the insulating layer to form a plurality of bumps, and by electroplating a metal layer on the surface of the bumps to obtain the conductive pillars, compared with the conductive pillars formed by the existing electroplating, the electroplating layer and time are shortened, the electroplating efficiency is improved, and the consistency of the height of the conductive pillars is improved. When the conductive pillars are connected with electronic components, the bumps can provide hard support. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1 to 10 It is a cross-sectional schematic diagram of the manufacturing process of the circuit board of an embodiment of the present application.

[0013] Explanation of main element symbols

[0014] Circuit board 100

[0015] Double-sided substrate 10

[0016] Blind hole 101

[0017] First metal layer 11

[0018] First insulating layer 12

[0019] Third metal layer 13

[0020] Conductive structure 102

[0021] Third conductive layer 130

[0022] Second insulating layer 21

[0023] Second metal layer 22

[0024] Circuit substrate 30

[0025] Insulating layer 40

[0026] Bump 41

[0027] Metal layer 42

[0028] First conductive layer 110

[0029] Second conductive layer 120

[0030] First connection pad 111

[0031] Second connection pad 121

[0032] First anti-soldering layer 61

[0033] Second anti-soldering layer 62

[0034] Anti-oxidation layer 70

[0035] The following detailed description will further explain the present application with reference to the above mentioned drawings. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing the specific embodiments only and is not intended to be limiting of the present application.

[0038] Some embodiments of the present application will be described in detail below with reference to the drawings. The following embodiments and features of the embodiments can be combined or replaced with each other or with other embodiments unless otherwise defined, without conflict.

[0039] Referring to Figures 1 to 10 The first embodiment of the present application provides a manufacturing method of a circuit board 100, which comprises the following steps:

[0040] Step S1, referring to Figure 1 A double-sided substrate 10 is provided, and a blind hole 101 is formed on the double-sided substrate 10.

[0041] The double-sided substrate 10 comprises a first metal layer 11, a first insulating layer 12 and a third metal layer 13 which are stacked. The blind hole 101 penetrates the third metal layer 13 and the first insulating layer 12, and part of the first metal layer 11 is exposed from the blind hole 101. The number of the blind holes 101 can be set according to actual needs, which is not limited by the present application.

[0042] The first insulating layer 12 is a dielectric material commonly used in the art, such as polyimide, epoxy resin, etc. The material of the first metal layer 11 and the third metal layer 13 can include but is not limited to copper, gold, silver, etc. In the present embodiment, the first metal layer 11 and the third metal layer 13 are copper foils.

[0043] Step S2, referring to Figure 2 A conductive structure 102 is formed in the blind hole 101 to electrically connect the first metal layer 11 and the third metal layer 13.

[0044] In this embodiment, the conductive structure 102 is a conductive hole. The conductive hole can be formed by the following method: first, a seed layer is formed on the inner wall of the blind hole 101 by a black hole / black shadow process, and then a copper plating layer is formed on the seed layer by electroplating to form the conductive hole. The seed layer can also be formed on the inner wall of the blind hole 101 by electroless copper plating. In other ways, the conductive structure 102 can be a conductive column, which can be formed by filling a conductive material in the blind hole 101.

[0045] Step S3, please refer to Figure 3 A circuit is made on the third metal layer to form a third conductive layer 130. The third conductive layer 130 is electrically connected to the first metal layer 11 through the conductive structure 102.

[0046] Step S4, please refer to Figure 4 And Figure 5 A second insulating layer 21 and a second metal layer 22 are provided, and the second insulating layer 21 and the second metal layer 22 are sequentially laminated on the third conductive layer 130 to obtain a circuit substrate 30.

[0047] The first metal layer 11 and the second metal layer 22 are located on the outer side of the circuit substrate 30 and are oppositely arranged. The second insulating layer 21 covers the third conductive layer 130 and is connected with the first insulating layer 12 to form an integral whole. In other embodiments, the third conductive layer 130 can be omitted, or the number of the third conductive layer 130 can be multiple, or the second metal layer 22 and the second insulating layer 21 can be omitted, which is not limited by the present application.

[0048] The second insulating layer 21 is a dielectric material commonly used in the art, such as polyimide, epoxy resin, etc. The material of the second metal layer 22 can include but is not limited to copper, gold, silver, etc. In this embodiment, the second metal layer 22 is a copper foil.

[0049] Step S5, please refer to Figure 5 An insulating layer 40 is formed on the side of the first metal layer 11 away from the first insulating layer 12. The insulating layer 40 covers the side of the first metal layer 11 away from the first insulating layer 12.

[0050] The material of the insulating layer 40 can be a photosensitive resin, such as photosensitive polyimide, or a non-photosensitive resin, such as ABF (Ajinomoto Build-up Film) material.

[0051] Step S6, please refer to Figure 6 Part of the insulating layer 40 is removed to form a plurality of insulating bumps 41.

[0052] The bumps 41 are formed by the remaining insulating layer 40. The plurality of bumps 41 are arranged on the first metal layer 11 at intervals. The bumps 41 are substantially columnar, and the diameter of the bumps 41 is 100-400 μm. In some embodiments, the diameter of the bumps 41 is 200-300 μm. The height a of the bumps 41 is 20-200 μm. In some embodiments, the height a of the bumps 41 is 30-50 μm. In the present embodiment, the cross-sectional shape of the bumps 41 along the thickness direction of the circuit board (i.e., along the height direction of the bumps 41) is an inverted trapezoid. In other embodiments, the cross-sectional shape of the bumps 41 can also be a trapezoid, a rectangle, etc., and the present application is not limited in this respect.

[0053] In the present embodiment, the material of the insulating layer 40 is a photosensitive resin. Step S6 specifically includes exposing and developing the insulating layer 40 to remove part of the insulating layer 40 and form the plurality of bumps 41. That is, part of the insulating layer 40 is removed by exposure and development. In other embodiments, part of the insulating layer 40 can also be removed by physical etching such as laser etching, plasma etching, or chemical etching, or other methods such as mechanical cutting, to form the plurality of bumps 41.

[0054] Step S7, please refer to Figure 7 A metal layer 42 is formed on the surface of the bumps 41 to obtain a conductive pillar 50.

[0055] The metal layer 42 covers all surfaces of the bumps 41 exposed to the circuit substrate 30 and is connected to the first metal layer 11. The bumps 41 and the metal layer 42 covering them together form the conductive pillar 50, which is electrically connected to the first metal layer 11.

[0056] In the present embodiment, the metal layer 42 is formed on the surface of the bumps 41 by electroplating. Specifically, a seed layer is first formed on the surface of the bumps 41 using a black shadow process, and then the metal layer 42 is formed on the seed layer by electroplating. In other embodiments, the metal layer 42 can also be formed on the surface of the bumps 41 by printing or other methods.

[0057] The thickness b of the metal layer 42 is 5-35 μm. In some embodiments, the thickness b of the metal layer 42 is 10-15 μm.

[0058] Step S8, please refer to Figure 8 Circuitry is made on the first metal layer and the second metal layer to form a first conductive layer 110 and a second conductive layer 120, respectively.

[0059] The first conductive layer 110 and the second conductive layer 120 are formed by an image transfer process and an etching process.

[0060] The first conductive layer 110 includes a plurality of first connection pads 111, each of which is electrically connected to the metal layer 42 of a corresponding conductive pillar 50. The second conductive layer 120 includes a plurality of second connection pads 121.

[0061] Step S9, please refer to Figure 9 A first anti-solder layer 61 is formed on the first conductive layer 110, and a second anti-solder layer 62 is formed on the second conductive layer 120, to obtain the circuit board 100.

[0062] The first anti-solder layer 61 covers the side of the first conductive layer 110 away from the first insulating layer 12, and the first connection pads 111 and the conductive pillars 50 are exposed outside the first anti-solder layer 61. The second anti-solder layer 62 covers the side of the second conductive layer 120 away from the second insulating layer 21, and the second connection pads 121 are exposed outside the second anti-solder layer 62.

[0063] In this embodiment, the first anti-solder layer 61 and the second anti-solder layer 62 are formed by printing, baking, UV exposure, and developing processes using a liquid photosensitive anti-solder ink.

[0064] The circuit board 100 further includes a conductive structure (not shown in the figure) that penetrates the second insulating layer 21 and electrically connects the second conductive layer 120 and the third conductive layer 130. The conductive structure can be a conductive hole or a conductive pillar.

[0065] Step S10, please refer to Figure 10 The first connection pads 111, the conductive pillars 50, and the second connection pads 121 are subjected to surface treatment to form a conductive anti-oxidation layer 70. The anti-oxidation layer 70 covers the surface of the first connection pads 111 away from the first insulating layer 12, the surface of the metal layer 42 away from the bump 41, and the surface of the second connection pads 121 away from the second insulating layer 21.

[0066] The anti-oxidation layer 70 is made of chemical deposition or electroplated nickel gold, nickel palladium gold, chemical tin, chemical tin silver, chemical tin silver copper, electroplated tin, electroplated tin silver, electroplated tin silver copper, or chemical silver.

[0067] Please refer to Figure 10The circuit board 100 includes a second conductive layer 120, a second insulating layer 21, a third conductive layer 130, a first insulating layer 12 and a first conductive layer 110 which are sequentially stacked, a plurality of conductive pillars 50 disposed on the first conductive layer 110, and a first anti-soldering layer 61 and a second anti-soldering layer 62 which are respectively disposed on the first conductive layer 110 and the second conductive layer 120. The second insulating layer 21 and the first insulating layer 12 are connected as a whole. The first conductive layer 110 includes a plurality of first connection pads 111, and the second conductive layer 120 includes a plurality of second connection pads 121. The plurality of conductive pillars 50 are disposed on the plurality of first connection pads 111. The conductive pillar 50 includes an insulating bump 41 disposed on the first connection pad 111 and a metal layer 42 covering a surface of the bump 41. The metal layer 42 is connected with the first connection pad 111. The first anti-soldering layer 61 covers a side of the first conductive layer 110 away from the first insulating layer 12, and the first connection pad 111 and the conductive pillar 50 are exposed outside the first anti-soldering layer 61. The second anti-soldering layer 62 covers a side of the second conductive layer 120 away from the second insulating layer 21, and the second connection pad 121 is exposed outside the second anti-soldering layer 62.

[0068] In the circuit board 100 and the manufacturing method thereof, the plurality of bumps 41 are formed by removing part of the insulating layer 40, and the conductive pillar 50 is obtained by electroplating a metal layer 42 on the surface of the bump 41. Compared with the existing electroplated conductive pillar, the electroplating layer and time are shortened, the electroplating efficiency is improved, and the consistency of the height of the conductive pillar 50 is improved. When the conductive pillar 50 is connected with an electronic component, the bump 41 can provide hard support.

[0069] The above merely describes the preferred embodiments of the present application, but is not intended to limit the present application in any form. Although the preferred embodiments of the present application are disclosed as above, the present application is not intended to be limited thereto, and any person skilled in the art can make some changes or modifications to the above disclosed technical contents to obtain equivalent embodiments with equivalent changes, as long as the changes or modifications do not depart from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application shall still fall within the scope of the technical solution of the present application.

Claims

1. A circuit board comprising a first conductive layer on an outer side, the first conductive layer comprising a plurality of first connection pads, the material of the first conductive layer being a copper foil, characterized in that, An insulating bump is protruded on each first connection pad, a surface of the bump is coated with a metal layer, the metal layer is connected with the first connection pad, the metal layer is a metal plating layer, the bump and the corresponding metal layer jointly form a conductive column, and the conductive column is used for connecting with an electronic component.

2. The circuit board of claim 1, wherein, The bump is made of a photosensitive resin.

3. The circuit board of claim 1, wherein, A first anti-soldering layer is coated on the first conductive layer, and the first connection pad and the metal layer are exposed from the first anti-soldering layer.

4. The circuit board of claim 1, wherein, A conductive anti-oxidation layer is coated on surfaces of the metal layer and the first connection pad.

5. A method of manufacturing a circuit board, characterized by, The method comprises the following steps: A circuit substrate is provided, comprising a first metal layer on an outer side, and the first metal layer is made of a copper foil; An insulating layer is formed on the first metal layer; Part of the insulating layer is removed to form a plurality of insulating bumps; A metal layer is formed on a surface of the bump by electroplating, wherein the metal layer is connected with the first metal layer, the bump and the corresponding metal layer jointly form a conductive column, and the conductive column is used for connecting with an electronic component; A first conductive layer is formed on the first metal layer by circuit manufacturing, wherein the first conductive layer comprises a plurality of first connection pads, and each first connection pad is connected with a corresponding metal layer.

6. The method of manufacturing a circuit board according to claim 5, wherein The insulating layer is made of a photosensitive resin, and part of the insulating layer is removed by exposure and development to form a plurality of insulating bumps.

7. The method of manufacturing a circuit board according to claim 5, wherein Part of the insulating layer is removed by laser etching or plasma etching to form a plurality of insulating bumps.

8. The method of manufacturing a circuit board according to claim 5, wherein The method further comprises the following steps: A first anti-soldering layer is formed on a surface of the first conductive layer, and the first connection pad and the metal layer are exposed from the first anti-soldering layer.

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