Method of manufacturing a flash memory device
By smoothing the interface between the sidewall and control gate through etching processes, the method addresses thickness non-uniformity and breakage issues, improving breakdown voltage and coupling ratio in flash memory devices.
Patent Information
- Application Number
- CN202211579332.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-06
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2042-12-06
AI Technical Summary
During the reduction of size of the existing flash memory devices, the side wall protrusions of the control gate layer cause uneven thickness or disconnection of the second side wall, which in turn causes a dielectric layer breakdown problem between the word line and the control gate.
The protrusions of the control gate layer are removed by the first etching process, and the interlayer dielectric layer is removed by anisotropic dry etching process to form a flat junction of the first side wall and the control gate layer, and then a covered second side wall is formed to ensure a flat contact between the word line and the control gate layer.
Reduce or avoid uneven thickness or disconnection of the second side wall, widen the process window, improve the breakdown voltage and coupling coefficient between the word line and the control gate, and improve the reliability of the device.
Smart Images
Figure CN115811883B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit manufacturing technology, and particularly to a method for manufacturing a flash memory device. Background Art
[0002] As a non-volatile memory, flash memory devices have the characteristics of convenience, high storage density, strong reliability, etc., and are widely used. The structures of existing flash memory devices usually include split-gate structures, stacked-gate structures or combinations thereof. Among them, split-gate flash memory devices have the characteristic of high programming efficiency.
[0003] With the continuous progress of integrated circuit manufacturing technology, the size of flash memory devices has also been continuously reduced. Referring to Figure 1 and Figure 2 , during the process of etching the control gate layer 20 exposed by the etching opening 10, side etching may occur, resulting in a protrusion A at the top corner of the control gate layer 20 near the opening 10; referring to Figure 3 , subsequent wet cleaning and other processes will etch back the first sidewall 30 above the control gate layer 20, thus exposing the protrusion A. However, referring to Figure 4 , as the size of the flash memory device is reduced, the thickness of each film layer in the flash memory device is thinned, and the related process window is reduced accordingly. Due to the presence of the protrusion A at the junction of the first sidewall 30 and the control gate layer 20, the second sidewall 31 formed on the surface of the first sidewall 30 and the sidewall of the control gate 21 is prone to uneven thickness. In severe cases, the part of the second sidewall 31 near the protrusion A will break, and the dielectric layer (i.e., the first sidewall 30, the second sidewall 31, and the third sidewall 33) between the control gate 21 and the word line 40 will be punctured.
[0004] In view of this, a method is needed to reduce or avoid the uneven thickness or disconnection of the second sidewall, so as to avoid the dielectric layer between the word line and the control gate from being punctured. Summary of the Invention
[0005] The purpose of the present invention is to provide a method for manufacturing a flash memory device, which reduces or avoids the uneven thickness or disconnection of the second sidewall, so as to avoid the dielectric layer between the word line and the control gate from being punctured.
[0006] To achieve the above purpose, the present invention provides a method for manufacturing a flash memory device, including:
[0007] Providing a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer, and a first sidewall is formed on the sidewall of the opening;
[0008] Perform a first etching process to remove the control gate layer exposed by the opening, so that the opening exposes the interlayer dielectric layer, and there is a protrusion at the top corner of the control gate layer close to the first sidewall;
[0009] Perform a second etching process to remove the protrusion and the interlayer dielectric layer exposed by the opening, so that the junction between the surface of the first sidewall and the sidewall of the control gate layer is straight;
[0010] Form a second sidewall that covers the surface of the first sidewall and the sidewall of the control gate layer;
[0011] Remove the floating gate layer exposed by the opening and form a word line in the opening; and,
[0012] Remove the hard mask layer and the control gate layer, interlayer dielectric layer, and floating gate layer under the hard mask layer to form a control gate and a floating gate.
[0013] Optionally, the second etching process is an anisotropic dry etching process.
[0014] Optionally, after performing the second etching process and before forming the second sidewall, further include:
[0015] Perform an ashing process and a wet cleaning process to remove the polymer generated in the second etching process.
[0016] Optionally, the interlayer dielectric layer is an ONO stacked structure formed by stacking silicon oxide layers, silicon nitride layers, and silicon oxide layers.
[0017] Optionally, the first sidewall is a silicon oxide layer.
[0018] Optionally, the second sidewall is a stacked structure formed by stacking a high-temperature oxide layer and a silicon nitride layer.
[0019] Optionally, after removing the floating gate layer exposed by the opening and before forming the word line, further include:
[0020] Form a third sidewall on the sidewall and bottom wall of the opening.
[0021] Optionally, the third sidewall is a silicon oxide layer.
[0022] Optionally, a gate oxide layer is further formed between the substrate and the floating gate layer.
[0023] Optionally, the manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device.
[0024] In summary, the present invention provides a method for manufacturing a flash memory device. Through a first etching process, the control gate layer exposed by the opening is removed. At this time, there are protrusions at the top corners of the control gate layer close to the first sidewall. Through a second etching process, the protrusions and the interlayer dielectric layer exposed by the opening are removed, so that the junction between the surface of the first sidewall and the sidewall of the control gate layer is flat. A second sidewall covering the surface of the first sidewall and the sidewall of the control gate layer is formed. The floating gate layer exposed by the opening is removed, and a word line is formed in the opening. In addition, the hard mask layer, the control gate layer, the interlayer dielectric layer, and the floating gate layer under the hard mask layer are removed to form a control gate and a floating gate. By removing the protrusions formed in the first etching process through the second etching process, the present invention makes the junction between the surface of the first sidewall and the sidewall of the control gate layer flat, reduces or avoids the situation of uneven thickness or disconnection of the second sidewall, broadens the process window of subsequent processes, and improves the breakdown voltage between the word line and the control gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figures 1 to 4 FIG. is a schematic structural diagram corresponding to some steps in a method for manufacturing a flash memory device;
[0026] Figure 5 FIG. is a flowchart of a method for manufacturing a flash memory device provided by an embodiment of the present invention;
[0027] Figures 6 to 11 FIG. is a schematic structural diagram corresponding to each step in a method for manufacturing a flash memory device provided by an embodiment of the present invention;
[0028] Among them, the reference numerals are as follows:
[0029] 10 - opening; 20 - control gate layer; 21 - control gate; 30 - first sidewall; 31 - second sidewall; 33 - third sidewall; 40 - word line;
[0030] 100 - substrate; 101 - gate oxide layer; 110 - floating gate layer; 111 - floating gate; 120 - interlayer dielectric layer; 130 - control gate layer; 131 - control gate; 140 - hard mask layer; 150 - opening; 151 - first sidewall; 152 - second sidewall; 153 - third sidewall; 160 - word line;
[0031] A, B - protrusions. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] The following will describe the specific embodiments of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.
[0033] Figure 5 A flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention. Refer to Figure 5 , the method for manufacturing the flash memory device described in this embodiment includes:
[0034] Step S01: Provide a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer, and a first sidewall is formed on the sidewall of the opening.
[0035] Step S02: Perform a first etching process to remove the control gate layer exposed by the opening, so that the opening exposes the interlayer dielectric layer, and there is a protrusion at the top corner of the control gate layer close to the first sidewall.
[0036] Step S03: Perform a second etching process to remove the protrusion and the interlayer dielectric layer exposed by the opening, so that the junction between the surface of the first sidewall and the sidewall of the control gate layer is straight.
[0037] Step S04: Form a second sidewall, which covers the surface of the first sidewall and the sidewall of the control gate layer.
[0038] Step S05: Remove the floating gate layer exposed by the opening and form a word line in the opening; and,
[0039] Step S06: Remove the hard mask layer and the control gate layer, interlayer dielectric layer, and floating gate layer below the hard mask layer to form a control gate and a floating gate.
[0040] Figures 6 to 11 Structural schematic diagrams corresponding to each step in the method for manufacturing the flash memory device provided in this embodiment. Below, in combination with Figures 6 to 11 Describe in detail the method for manufacturing the flash memory device described in this embodiment.
[0041] First, refer to Figure 6 , execute Step S01 to provide a substrate 100, on which a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130, and a hard mask layer 140 are sequentially formed. An opening 150 exposing the control gate layer 130 is formed on the hard mask layer 140, and a first sidewall 151 is formed on the sidewall of the opening 150.
[0042] Exemplarily, the process of forming the first sidewall 151 includes: sequentially depositing and forming a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130, and a hard mask layer 140 on the substrate 100; performing photolithography and etching processes on the hard mask layer 140 to pattern the hard mask layer 140, thereby forming the opening 150; depositing a first sidewall material layer (not shown in the figure) in the opening 150, and the first sidewall material layer extends to cover the surfaces of the hard mask layer 140 on both sides of the opening 150; etching the first sidewall material layer to form the first sidewall 151 on the sidewalls of the opening 150.
[0043] In this embodiment, the interlayer dielectric layer 120 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. Optionally, a gate oxide layer 101 is further formed between the substrate 100 and the floating gate layer 110. Optionally, the first sidewall 151 is a silicon oxide layer.
[0044] Next, refer to Figure 7 , perform step S02 to carry out a first etching process to remove the control gate layer 130 exposed in the opening 150, so that the opening 150 exposes the interlayer dielectric layer 120, and there is a protrusion B at the top corner of the control gate layer 130 close to the first sidewall 151. Specifically, the control gate layer 130 exposed in the opening 150 is etched using the hard mask layer 140 and the first sidewall 151 as masks, so that the opening 150 exposes the interlayer dielectric layer 120. It should be noted that during the etching process of the control gate layer 130, a side etching phenomenon may occur, causing the sidewall of the control gate layer 130 close to the opening 150 to present an inwardly concave bow-shaped profile, thereby resulting in the protrusion B at the top corner of the control gate layer 130 close to the first sidewall 151.
[0045] Optionally, after the first etching process and before performing step S03, a wet cleaning process can also be used to remove the polymer generated in the first etching process to ensure the smooth progress of subsequent etching and other processes. It should be noted that the wet etching process performed after the first etching process may etch back the first sidewall 151, exposing the protrusion B that was originally covered by the first sidewall 151.
[0046] Subsequently, refer to Figure 8 , perform step S03 to carry out a second etching process to remove the protrusion B and the interlayer dielectric layer 120 exposed in the opening 150, so that the junction between the surface of the first sidewall 151 and the sidewall of the control gate layer 130 is straight.
[0047] In this embodiment, the second etching process is an anisotropic dry etching process. It should be noted that, since the second etching process is an anisotropic dry etching process, and the first sidewall 151 is a silicon oxide layer, and the interlayer dielectric layer 120 is an ONO stacked structure, therefore, during the process of etching the interlayer dielectric layer 120 downward along the opening 150, the first sidewall 151 can protect the control gate layer 130 below it from etching damage. At the same time, since the protrusion B generated in step S02 is exposed outside the first sidewall 151, therefore, the protrusion B will be removed together in this etching process, making the junction between the surface of the first sidewall 151 and the sidewall of the control gate layer 130 flat, thereby increasing the process window of the subsequent process.
[0048] Optionally, after performing the second etching process and before performing step S04, an ashing process and a wet strip process may also be performed to remove the polymers generated in the second etching process.
[0049] Next, refer to Figure 9 , perform step S04 to form a second sidewall 152, and the second sidewall 152 covers the surface of the first sidewall 151 and the sidewall of the control gate layer 130. In this embodiment, the second sidewall 152 is a stacked structure formed by stacking a high temperature oxidation layer (HTO) and a silicon nitride layer.
[0050] Subsequently, refer to Figure 10 , perform step S05 to remove the floating gate layer 110 exposed by the opening 150 and form a word line 160 in the opening 150.
[0051] Exemplarily, the formation process of the word line 160 includes: etching the floating gate layer 110 exposed by the opening 150 and the gate oxide layer 101 below the opening 150 with the hard mask layer 140, the first sidewall 151, and the second sidewall 152 as masks, so that the opening 150 exposes the substrate 110; forming a third sidewall 153 on the sidewall and bottom of the opening 150 (the formation process of the third sidewall 153 is the same as that of the first sidewall 151 and will not be described in detail here); depositing and forming a word line material layer (not shown in the figure) on the hard mask layer 140 on both sides of the opening 150 and in the opening 150, and performing a planarization process and an etching process on the word line material layer to form a word line 160 in the opening 150. Optionally, a chemical mechanical polishing process is used for the planarization process. Optionally, the third sidewall 153 is a silicon oxide layer. The word line 160 is a polysilicon layer.
[0052] Next, refer to Figure 11, step S06 is executed to remove the hard mask layer 140, the control gate layer 130, the interlayer dielectric layer 120, and the floating gate layer 110 under the hard mask layer 140 to form a control gate 131 and a floating gate 111. Optionally, a dry etching process is used to remove the hard mask layer 140, the control gate layer 130, the interlayer dielectric layer 120, the floating gate layer 110, and the gate oxide layer 101 under the hard mask layer 140.
[0053] In this embodiment, the manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device. In other embodiments of the present invention, the manufacturing method of the flash memory device can also be used to manufacture other types of flash memory devices or other semiconductor devices with the same structure. The present invention does not limit this.
[0054] Comparison Figure 4 and Figure 11 It can be seen that in the existing flash memory device, there is a protrusion A directly on the surface of the sidewall of the control gate 21 close to the word line 40 and the first sidewall 30, so that the part of the second sidewall 31 close to the protrusion A is thinner and has a risk of breakage, increasing the breakdown risk between the control gate 21 and the word line 40; while in the flash memory device formed in this embodiment, the junction between the sidewall of the control gate 131 close to the word line 160 and the first sidewall 151 is flat, improving the breakdown voltage between the control gate 131 and the word line 160.
[0055] In summary, the present invention provides a manufacturing method of a flash memory device. Through the first etching process, the control gate layer exposed by the opening is removed. At this time, there is a protrusion at the top corner of the control gate layer close to the first sidewall; through the second etching process, the protrusion and the interlayer dielectric layer exposed by the opening are removed, so that the junction between the surface of the first sidewall and the sidewall of the control gate layer is flat; a second sidewall covering the surface of the first sidewall and the sidewall of the control gate layer is formed; the floating gate layer exposed by the opening is removed, and a word line is formed in the opening; and, the hard mask layer, the control gate layer, the interlayer dielectric layer, and the floating gate layer under the hard mask layer are removed to form a control gate and a floating gate. The present invention removes the protrusion formed in the first etching process through the second etching process, makes the junction between the surface of the first sidewall and the sidewall of the control gate layer flat, reduces or avoids the situation that the second sidewall has uneven thickness or breaks, broadens the process window of the subsequent process, and improves the breakdown voltage (Breakdown Voltage, BV) and coupling ratio (Coupling Ratio, CR) between the word line and the control gate.
[0056] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, without departing from the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content that does not depart from the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A manufacturing method of a flash memory device, characterized in that, Including: Providing a substrate, on which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer are sequentially formed. An opening exposing the control gate layer is formed on the hard mask layer, and a first sidewall is formed on the sidewall of the opening; Performing a first etching process to remove the control gate layer exposed by the opening, so that the opening exposes the interlayer dielectric layer, and there is a protrusion at the top corner of the control gate layer close to the first sidewall; Performing a second etching process to remove the protrusion and the interlayer dielectric layer exposed by the opening, so that the junction between the surface of the first sidewall and the sidewall of the control gate layer is straight; Forming a second sidewall, which covers the surface of the first sidewall and the sidewall of the control gate layer; Removing the floating gate layer exposed by the opening and forming a word line in the opening; And, Removing the hard mask layer and the control gate layer, interlayer dielectric layer, and floating gate layer under the hard mask layer to form a control gate and a floating gate.
2. The manufacturing method of the flash memory device according to claim 1, wherein, The second etching process is an anisotropic dry etching process.
3. The manufacturing method of the flash memory device according to claim 2, characterized in that, After performing the second etching process and before forming the second sidewall, it further includes: Performing an ashing process and a wet cleaning process to remove the polymer generated in the second etching process.
4. The manufacturing method of the flash memory device according to claim 1 or 2, characterized in that, The interlayer dielectric layer is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
5. The manufacturing method of the flash memory device as described in claim 4, characterized in that, The first sidewall is a silicon oxide layer.
6. The manufacturing method of the flash memory device according to claim 1, characterized in that, The second sidewall is a stacked structure formed by stacking a high-temperature oxide layer and a silicon nitride layer.
7. The manufacturing method of the flash memory device according to claim 1, characterized in that, After removing the floating gate layer exposed by the opening and before forming the word line, it further includes: Forming a third sidewall on the sidewall and bottom wall of the opening.
8. The method of manufacturing a flash memory device according to claim 7, wherein, The third sidewall is a silicon oxide layer.
9. The manufacturing method of the flash memory device according to claim 1, characterized in that, A gate oxide layer is further formed between the substrate and the floating gate layer.
10. The manufacturing method of the flash memory device according to claim 1, characterized in that, The manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device.