Controller and storage system

Abstract

Provided are a controller and a storage system capable of achieving miniaturization and high speed. The controller is provided with a first and a second PCIe MAC layer circuit connected to a physical layer interface circuit based on lane position flipping. The controller is provided with a signal processing circuit provided with a first terminal that receives a part of a signal of a first auxiliary signal line that transmits a sideband signal of a first port and a second terminal that receives a part of a signal of a second auxiliary signal line that transmits a sideband signal of a second port. The controller is capable of switching the wiring of the part of the signal of the first auxiliary signal line and the part of the signal of the second auxiliary signal line with respect to each of the first and second terminals of the signal processing circuit based on lane position flipping, and is capable of switching the wiring of the other part of the signal of the first auxiliary signal line and the other part of the signal of the second auxiliary signal line between the physical layer interface circuit and the first and second PCIe MAC layer circuits.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-152531 (filed on September 17, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to controllers and storage systems. Background Technology

[0003] In recent years, solid-state drives (SSDs) have been developed as storage systems incorporating non-volatile memory such as NAND flash memory. With the increasing data storage capacity of SSDs, the number of non-volatile memory modules incorporated into them has also increased. Consequently, there is a growing demand for smaller and faster storage systems. Summary of the Invention

[0004] The technical problem to be solved by this invention is to provide a controller and storage system that can achieve miniaturization and high speed.

[0005] The controller in this implementation includes: a physical layer interface circuit corresponding to a first port and a second port conforming to the PCIe standard, the first port including a first number of channels assigned a first order, and the second port including a second number of channels assigned a second order, the first number of channels and the second number of channels being connected to the physical layer interface circuit via wiring arranged in a sequence that has been swapped based on a lane reversal conforming to the PCIe standard, via a portion of the first order and a portion of the second order. The controller also includes: a first PCIe MAC (Media Access Control) layer circuit and a second PCIe MAC layer circuit, respectively provided corresponding to each of the first port and the second port, and connected to the physical layer interface circuit based on the lane reversal. The controller includes: a signal processing circuit having a first terminal and a second terminal, the first terminal receiving a portion of a signal from a first auxiliary signal line, the first auxiliary signal line being different from a first signal line corresponding to a first number of channels and transmitting a sideband signal of the first port; the second terminal receiving a portion of a signal from a second auxiliary signal line, the second auxiliary signal line being different from a second signal line corresponding to a second number of channels and transmitting a sideband signal of the second port. The controller also includes: a switching circuit that, based on channel position flipping, is capable of switching the routing of the portion of the signal from the first auxiliary signal line and the portion of the signal from the second auxiliary signal line relative to each terminal of the first and second terminals of the signal processing circuit; and is capable of switching the routing of other portions of the signal from the first auxiliary signal line and other portions of the signal from the second auxiliary signal line between the physical layer interface circuit and the first and second PCIe MAC layer circuits. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating one configuration example of a storage device according to an embodiment.

[0007] Figure 2 This is a perspective view showing an example of the appearance of a storage device.

[0008] Figure 3 This is a cross-sectional view showing an example of a storage device.

[0009] Figure 4 This diagram shows an example of channel numbering when the controller is mounted on the back of the substrate.

[0010] Figure 5This is a diagram illustrating an example of the internal structure of a controller for a storage device.

[0011] Figure 6 This is a diagram illustrating an example of using a Dual Port with channel position flipping.

[0012] Figure 7 This is a diagram illustrating an example of channel position flipping using a Single Port.

[0013] Figure 8 This is a diagram illustrating an example of the configuration of a controller for a storage device involved in a variation.

[0014] Label Explanation

[0015] 1. Storage System

[0016] 2 main units

[0017] 10 Controllers

[0018] 12 substrate

[0019] 14. Connector

[0020] 15 Physical Layer Interface Circuit

[0021] MAC layers 16A and 16B

[0022] 21A Host Port

[0023] 21B Host Port

[0024] 30 storage units

[0025] S1 switching circuit, circuit 1

[0026] S2 switching circuit, second circuit

[0027] S3 switching circuit, third circuit

[0028] S4 switching circuit Detailed Implementation

[0029] The embodiments will now be described with reference to the accompanying drawings.

[0030] Figure 1 This diagram illustrates a configuration example of the storage device 1 according to the embodiment. In this embodiment, the storage device 1, which is the storage system, is envisioned to be implemented as an SSD (Solid State Drive).

[0031] like Figure 1As shown, storage device 1 includes a controller 10, a buffer memory 20, and a storage device 30. Storage device 1 can be connected to host 2, for example, via an interface conforming to the PCI-Express™ (also known as PCIe™) standard.

[0032] Storage device 1 is an enterprise SSD. Storage device 1 has a memory 30 and a controller 10 mounted on a printed circuit board 12 (see reference). Figure 2 An example of a storage system configured as follows. The storage device 1 has a connection portion 14 (see reference 12) that uses wiring provided on the printed circuit board 12 as terminals. Figure 2 It can function as a removable SSD that can be installed inside the host 2 as a connector (also known as a card connector).

[0033] The host device 2 can be, for example, an information processing device such as a storage system, server, or personal computer; a mobile phone; a digital camera; an imaging device; a portable terminal such as a tablet computer or smartphone; a gaming device; or an in-vehicle terminal such as a vehicle navigation system.

[0034] The buffer memory 20 is, for example, DRAM (Dynamic Random Access Memory). The buffer memory 20 functions as the working memory of the controller 10. The buffer memory 20 can also be SRAM. The buffer memory 20 can also be built into the controller 10.

[0035] The memory 30 is, for example, a NAND flash memory. The memory 30 includes at least one semiconductor memory chip. The memory 30 can also be other semiconductor memories. In one example, it is MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), PRAM (Phase Change RAM), RRAM (Resistic RAM), etc.

[0036] The controller 10 is a chip component that integrates functional units such as the CPU (Central Processing Unit), which is the central hub of the computer, memory storing firmware that enables the CPU to operate, and I / O circuits. The controller 10 is configured, for example, as a SoC (System on a Chip).

[0037] Controller 10 receives commands from host 2 (in one example, a Write command and a Read command). Based on the received commands, controller 10 uses buffer memory 20 as a temporary storage area for data while performing write operations to write data transmitted from host 2 to memory 30 and read operations to read data requested by host 2 from memory 30. In other words, controller 10 controls memory 30 based on commands from host 2.

[0038] Figure 2 This is a perspective view showing an example of the appearance of storage device 1. Figure 3 This is a cross-sectional view showing an example of storage device 1. Furthermore, Figure 3 express Figure 2 A portion of section A-A. For example... Figure 2 and Figure 3 As shown, the storage device 1 has a box-shaped frame 11.

[0039] In addition, the storage device 1 includes a generally rectangular printed circuit board (hereinafter referred to as the board) 12. The board 12 may be a single-layer structure, or it may be a multi-layer structure formed by overlapping synthetic resins such as epoxy resin. Various wiring patterns of different shapes are formed on the surface of each layer. For example, layers may be formed for signal lines configured for transmitting and receiving signals, for example, layers configured as ground wiring for the reference potential of the controller 10 and the storage 30, for example, layers configured as wiring for the power supply potential of the controller 10 and the storage 30, etc.

[0040] A connecting portion 14 is provided at the end 12a of one short side of the substrate 12. The substrate 12 has a surface (an example of a first surface) 12b and a back surface (an example of a second surface) 12c that is the opposite side to the surface 12b. The connecting portion 14 has a plurality of terminals provided on the surface 12b of the substrate 12 and a plurality of terminals provided on the back surface 12c. A portion of a wiring pattern (not shown) formed on the substrate 12 is electrically connected to each terminal of the connecting portion 14. Each terminal of the connecting portion 14 is formed by wiring formed on the substrate 12. That is, the connecting portion 14 is formed as an edge connector. The connecting portion 14 is directly connected to a connector (not shown) on the circuit board of the host 2, or connected to a connector on the circuit board of the host 2 via a cable. Thus, the storage device 1 is electrically connected to the host 2.

[0041] like Figure 3 As shown, the substrate 12 and the controller 10 are disposed inside the frame 11. Although Figure 3 Although not shown in the diagram, buffer memory 20 and storage 30 are also located inside the frame 11.

[0042] like Figure 3As shown, the controller 10 is mounted on the back side 12c of the substrate 12, which is opposite to the plurality of terminals disposed on the surface 12b of the substrate 12.

[0043] By incorporating the substrate 12, controller 10, buffer memory 20, and storage 30 within the housing 11, these components and other circuit components mounted on the substrate 12 can be protected from structural damage, electrical short circuits, and static electricity.

[0044] Here, the reason for mounting the controller 10 on the back side 12c of the substrate 12 of the storage device 1 will be explained.

[0045] Previously, there was a U.2 standard that defined connection methods for applications such as SSDs using the PCIe standard. According to this U.2 standard, there is leeway in the height restrictions inside the storage device's enclosure, thus allowing the controller to be mounted on the surface (first side) of the printed circuit board.

[0046] In addition, in the U.2 standard, in order to achieve high-speed transmission at the GHz level of the PCIe interface, the terminals (pins) of the PCIe interface of the SoC, which integrates multiple components (systems) required for control, including the CPU, are arranged in a pattern (parallel pattern) that does not produce pattern intersection.

[0047] On the other hand, in recent years, EDSFF (Enterprise and Data Center SSD Form Factor) has been developed as a new standard. According to the EDSFF standard, in order to miniaturize storage devices, the internal height limit of the storage device enclosure has become stricter compared to the U.2 standard.

[0048] Therefore, in the storage device 1 of this embodiment, under the EDSFF standard, the height limitation problem is avoided by mounting the controller 10 or the like on the back side 12c of the substrate 12, which has a height limitation margin. Furthermore, by mounting the controller 10 or the like on the back side 12c of the substrate 12, heat dissipation efficiency can be expected to improve, thus also being advantageous for cooling.

[0049] Here, Figure 4 This is a diagram showing an example of channel numbering when the controller 10 is mounted on the back side 12c of the substrate 12. Figure 4 The diagram illustrates a comparison between an example assuming the controller 10 is configured on the back side 12c of substrate 12 in the EDSFF standard and an example assuming the controller 10 is configured on the surface 12b of substrate 12 in the U.2 standard. Figure 4In the standard PCIe interface, the number after L in channels L0 to L4 indicates the channel number. Each channel L0 to L4 includes multiple signal lines, but... Figure 4 The middle part is omitted. For example... Figure 4 As shown, when a controller 10 conforming to the PCIe interface U.2 standard is mounted on the back side 12c of the substrate 12 with terminals arranged in a parallel pattern (channel order in this case), the channel number of the signal line between the connector 14 and the controller 10 will be flipped.

[0050] On the other hand, the signal lines of the PCIe interface support lane reversal, which is a function that reverses the lane order according to the PCIe standard. Therefore, the routing of the PCIe interface signal lines can function as a lane reversal pattern when the controller 10 is mounted on the back side 12c of the substrate 12. Lane reversal improves the flexibility of substrate layout by allowing a logical reversal of the channel numbering order of the signal lines, reducing the number of signal lines that need to cross each other in the wiring of the printed circuit board.

[0051] Therefore, in this embodiment, the storage device 1 uses a channel position flipping method that conforms to the PCIe standard to connect the connection part 14 to the controller 10.

[0052] Here, Figure 5 This is a diagram illustrating an example of the internal configuration of the controller 10 of the storage device 1. (See diagram below.) Figure 5 As shown, storage device 1 is a device corresponding to the PCIe standard Dual Port (hereinafter referred to as a Dual Port device). That is, storage device 1 can be connected to host 2 via two ports. Storage device 1 can be accessed by host 2 via two ports, each with four channels. Figure 5 In this configuration, host 2 has host port 21A as port 1 and host port 21B as port 2. Here, PA-L0 to PA-L3 and PB-L0 to PB-L3 each represent one channel of the transmission path set on each port.

[0053] In addition, such as Figure 5 As shown, the connector 14 of the storage device 1 connects to the host ports 21A and 21B of the host 2 according to the PCIe standard channel positions, by swapping the order of some channels. Specifically, as... Figure 5 As shown, PA-L2 of host port 21A is connected to channel 4 of connection part 14, PA-L3 of host port 21A is connected to channel 5 of connection part 14, PB-L0 of host port 21B is connected to channel 2 of connection part 14, and PB-L1 of host port 21B is connected to channel 3 of connection part 14.

[0054] like Figure 5 As shown, the controller 10 includes a physical layer interface circuit 15 implemented as the standard physical layer (PHY) of the PCIe standard, a MAC 16A as the first PCIe MAC (Media Access Control) layer circuit corresponding to host port 21A, and a MAC 16B as the second PCIe MAC layer circuit corresponding to host port 21B. Furthermore, a huddle 17 is a CPU peripheral logic circuit disposed on the controller 10.

[0055] The physical layer interface circuit 15 uses a channel position flipping method conforming to the PCIe standard to connect the channels of the connection section 14 via multiple signal lines. These multiple signal lines transmit signals conforming to the PCIe standard. Each channel has its own set of differential pairs for bidirectional communication. In the PCIe standard, a transmit differential signal TX and a receive differential signal RX are assigned to any one of the multiple terminals of each channel. By using the transmit differential signal TX and the receive differential signal RX, bidirectional communication is possible.

[0056] MAC16A and MAC16B are configured according to host ports 21A and 21B respectively. MAC16A and MAC16B use channel position flipping conforming to the PCIe standard to connect to the physical layer interface circuit 15 and control access to the memory 30.

[0057] Additionally, the controller 10 has auxiliary signal lines for exchanging sideband signals, which are configured differently from the signal lines. More specifically, the controller 10 has signal processing circuitry comprising: a first terminal that receives a portion of the signal from the first auxiliary signal line (auxiliary signal line) transmitting the sideband signal of the host port 21A; and a second terminal that receives a portion of the signal from the second auxiliary signal line (auxiliary signal line) transmitting the sideband signal of the host port 21B. The sideband signal of the host port 21A is different from the first signal line (signal line) corresponding to the first number of channels allocated in a first order in the host port 21A. The sideband signal of the host port 21B is different from the second signal line (signal line) corresponding to the second number of channels allocated in a second order in the host port 21B.

[0058] Furthermore, the controller 10 includes a switching circuit that flips the auxiliary signal line corresponding to the channel position between the physical layer interface circuit 15 and MAC 16A and MAC 16B. The switching circuit will be described below.

[0059] When using a Dual Port device with channel position flipping in a Dual Port configuration, the following problem occurs. Figure 6 This is a diagram illustrating an example of using a Dual Port with channel position flipping. (Example:) Figure 6 As shown, when using DualPort with channel position inversion, host ports 21A and 21B are connected to MAC16A and MAC16B of controller 10 in reverse order. This results in the problems described below.

[0060] (1) The signal PERST#, which is the Sideband signal, is switched between host port 21A and host port 21B for connection.

[0061] (2) The Refclk (reference clock) signal, which serves as the Sideband signal, is switched between host port 21A and host port 21B for connection.

[0062] (3) The PIPE (PHY Interface for the PCI Express Architecture) clock switch circuit 18, which detects the disappearance of the signal Refclk, receives the signal Refclk from the opposite port.

[0063] Additionally, using Figure 7 This example illustrates the use of channel position flipping with a Single Port. For example... Figure 7 As shown, when using channel position inversion as a Single Port, channel position inversion is performed using a PCIe MAC (Media Access Control) layer. Additionally, one PERST# signal and one Refclk signal are used as the Sideband signal. Therefore, even with channel position inversion, the host port 21A and controller 10, as a Single Port, can be connected without problems.

[0064] Therefore, as Figure 5 As shown, the storage device 1 according to this embodiment, which is a Dual Port device, includes a switching circuit, which includes switching circuits S1 to S3 for switching the Sideband signal between host port 21A and host port 21B. Thus, the storage device 1 can switch between Dual Port usage channel positions. A detailed description follows.

[0065] The switching circuit can switch the routing of a portion of the first auxiliary signal line and a portion of the second auxiliary signal line relative to each terminal of the first and second terminals of the signal processing circuit based on channel position inversion. Furthermore, the switching circuit can switch the routing of other portions of the first auxiliary signal line and other portions of the second auxiliary signal line between the physical layer interface circuit 15 and MAC16A and MAC16B.

[0066] like Figure 5 As shown, the PERST# signal, which is the PCIe Sideband signal, is a negative logic reset signal sent from host 2. The PERST# signal can be used by host 2 to reset the bus, which is the bus used in communication corresponding to the PCIe standard. The PERST# signal can be used when an error occurs, such as when host 2 reinitializes storage device 1.

[0067] like Figure 5 As shown, the Refclk signal, which is the PCIe Sideband signal, is a reference differential clock signal sent from host 2. The reference differential clock signal is composed of two differential signals forming a differential clock. By receiving the differential clock from the connected host 2, storage device 1 can easily synchronize the signals transmitted with the connected host 2.

[0068] The switching circuit S1 included in the switching circuit functions as a first circuit that switches the detection of interruption of the signal PERST#, which is a Sideband signal, between the host port 21A and the host port 21B. The switching circuit S1 includes a multiplexer 51, a multiplexer 52, and a signal PERST# switching unit 53.

[0069] The multiplexer 51 includes an input terminal for one of the input signals PERST#A, an input terminal for the other of the input signals PERST#B, a control terminal connected to the signal PERST# switching unit 53 of the hub 17, and an output terminal connected to the terminal of the input signal PERST#A of the hub 17. The multiplexer 51 outputs either the input signal PERST#A or the input signal PERST#B based on the signal input to the control terminal from the signal PERST# switching unit 53.

[0070] The multiplexer 52 includes an input terminal for one of the input signals PERST#B, an input terminal for the other of the input signal PERST#A, a control terminal connected to the signal PERST# switching unit 53 of the hub 17, and an output terminal connected to the terminal of the signal PERST#B input to the hub 17. The multiplexer 52 outputs either the input signal PERST#A or the signal PERST#B based on the signal input to the control terminal from the signal PERST# switching unit 53.

[0071] The PERST# switching unit 53 is one of the modules installed in the huddle 17. Under the control of the CPU, which operates according to the firmware, the PERST# switching unit 53 determines which reset signal (PERST#A or PERST#B) to select. Furthermore, the PERST# switching unit 53 outputs a signal indicating the decision result to the multiplexer 51 and multiplexer 52.

[0072] That is, the switching circuit S1 switches the output signals from the multiplexer 51 and the multiplexer 52 according to the switching signal from the signal PERST# switching unit 53. As a result, the interruption detection of the signal PERST# is correctly switched between the host port 21A and the host port 21B.

[0073] The switching circuit S2 included in the switching circuit functions as a second circuit in the physical layer interface circuit 15, switching between signals RefclkA and RefclkB. Furthermore, the switching circuit S2 in the physical layer interface circuit 15 is controlled by a CPU that operates according to the firmware.

[0074] The physical layer interface circuit 15 has physical layers (PHY0 to PHY7) corresponding to multiple channels PA-L0 to PA-L3 of host port 21A and multiple channels PB-L0 to PB-L3 of host port 21B.

[0075] The physical layer interface circuit 15 receives signal RefclkA from host port 21A via connection part 14, and receives signal RefclkB from host port 21B via connection part 14. Under the control of the CPU, which operates according to the firmware, the switching circuit S2 switches between signal RefclkA and signal RefclkB in the physical layer interface circuit 15.

[0076] More specifically, the physical layer interface circuit 15 turns on the switch configured in physical layer PHY2, one of the switches configured in physical layer PHY2, physical layer PHY3, physical layer PHY6, and physical layer PHY7 constituting the switching circuit S2. As a result, physical layer PHY2 outputs a signal PCLK2 corresponding to signal RefclkA from the PIPE clock switch circuit 18-2. Furthermore, the physical layer interface circuit 15 turns on the switch configured in physical layer PHY0, physical layer PHY1, physical layer PHY4, and physical layer PHY5 constituting the switching circuit S2. As a result, physical layer PHY0 outputs a signal PCLK0 corresponding to signal RefclkB from the PIPE clock switch circuit 18-1.

[0077] The two switching circuits S3 included in the switching circuit function as a third circuit that switches the Refclk disappearance detection signals output from the corresponding Refclk Loss det (Refclk disappearance detector) 19 between the host port 21A and the host port 21B. The switching circuit S3 includes a multiplexer 61, a multiplexer 62, and a detection signal switching unit 63.

[0078] The Refclk Loss det19 function monitors the clock period of signals RefclkA and RefclkB. When Refclk Loss det19 detects that signals RefclkA or RefclkB have deviated from a certain frequency range, it outputs a Refclk disappearance detection signal.

[0079] The multiplexer 61 includes an input terminal for one of the Refclk disappearance detection signals of the input signal RefclkB, an input terminal for the other of the Refclk disappearance detection signals of the input signal RefclkA, a control terminal connected to the detection signal switching unit 63, and an output terminal connected to the control terminal of the PIPE clock switching circuit 18. The multiplexer 61 outputs either the Refclk disappearance detection signal of the input signal RefclkB or the Refclk disappearance detection signal of the input signal RefclkA, based on the signal input to the control terminal from the detection signal switching unit 63.

[0080] The multiplexer 62 includes an input terminal for one of the Refclk disappearance detection signals of the input signal RefclkA, an input terminal for the other of the Refclk disappearance detection signals of the input signal RefclkB, a control terminal connected to the detection signal switching unit 63, and an output terminal connected to the control terminal of the PIPE clock switching circuit 18. The multiplexer 62 outputs either the Refclk disappearance detection signal of the input signal RefclkB or the Refclk disappearance detection signal of the input signal RefclkA, based on the signal from the detection signal switching unit 63 input to the control terminal.

[0081] Under the control of the CPU, which operates according to the firmware, the detection signal switching unit 63 determines whether to select the Refclk disappearance detection signal of signal RefclkB or the Refclk disappearance detection signal of signal RefclkA. Furthermore, the detection signal switching unit 63 selects the signal from the same side as that switched by the signal PERST# switching unit 53 by outputting a signal specifying the determined disappearance detection signal to the multiplexer 61 and multiplexer 62.

[0082] The PIPE clock switching circuit 18-1 has an input terminal for one side of the input signal OSC, an input terminal (second terminal) for the other side of the input signal PCLK0 from the physical layer interface circuit 15, a control terminal connected to the multiplexer 61, and an output terminal connected to the MAC 16B. The signal OSC is a synchronization signal output from the signal transmitting circuit (oscillator).

[0083] The PIPE clock switching circuit 18-1 outputs a signal to MAC16B that has been input to either one of the input terminals of one side or the other side, based on the disappearance detection signal input from the multiplexer 61 to the control terminal.

[0084] The PIPE clock switching circuit 18-2 has an input terminal for one side of the input signal OSC, an input terminal (first terminal) for the other side of the input signal PCLK2 from the physical layer interface circuit 15, a control terminal connected to the multiplexer 62, and an output terminal connected to the MAC 16A. The signal OSC is a synchronization signal output from the signal transmitting circuit (oscillator).

[0085] The PIPE clock switching circuit 18-2 outputs a signal to MAC16A based on the disappearance detection signal input from the multiplexer 62 to the control terminal, which is either input to one of the input terminals or the other input terminal.

[0086] That is, the switching circuit S3 switches the output signals from the multiplexer 61 and the multiplexer 62 using the switching signal from the detection signal switching unit 63. As a result, the Refclk disappearance detection signal is correctly switched between the host port 21A and the host port 21B.

[0087] Thus, according to this embodiment, by using a channel position flipping method that conforms to the PCIe standard, the storage device 1, which is a Dual Port device, can have the controller 10 mounted on at least the back side of the substrate 12. With this configuration, according to this embodiment, height restrictions can be relaxed and heat dissipation efficiency can be improved without sacrificing the transmission characteristics on the substrate 12.

[0088] (Modified Example)

[0089] Figure 8 This is a diagram illustrating an example of the configuration of the controller 10 of the storage device 1 involved in the modified example. For example... Figure 8 As shown, the storage device 1 can also be configured to include a Bifurcation switch circuit S4 that switches the path from the physical layer interface circuit 15 to MAC 16A and MAC 16B. The Bifurcation switch circuit S4 is a line-corresponding circuit that constitutes the switching circuit.

[0090] The Bifurcation switching circuit S4 employs numerous switches utilizing multiplexers to correctly branch the channels connected to the physical layer interface circuit 15 to MAC16A / MAC16B. Under the control of the CPU, which operates according to the firmware, the multiple multiplexers switch paths from the physical layer interface circuit 15 to MAC16A and MAC16B based on channel position inversions. Specifically, the Bifurcation switching circuit S4 operates based on channel position inversions as follows.

[0091] The bridging switch circuit S4 branches the channel PB-L3 of host port 21B, which is connected to physical layer PHY0 of physical layer interface circuit 15, to PB-L3 of MAC 16B. The bridging switch circuit S4 also branches the channel PB-L2 of host port 21B, which is connected to physical layer PHY1 of physical layer interface circuit 15, to PB-L2 of MAC 16B. The bridging switch circuit S4 further branches the channel PA-L3 of host port 21A, which is connected to physical layer PHY2 of physical layer interface circuit 15, to PA-L3 of MAC 16A. Finally, the bridging switch circuit S4 branches the channel PA-L2 of host port 21A, which is connected to physical layer PHY3 of physical layer interface circuit 15, to PA-L2 of MAC 16A.

[0092] Additionally, the Bifurcation switch circuit S4 branches the channel PB-L1 of host port 21B, which is connected to physical layer PHY4 of physical layer interface circuit 15, to PB-L1 of MAC 16B. The Bifurcation switch circuit S4 also branches the channel PB-L0 of host port 21B, which is connected to physical layer PHY5 of physical layer interface circuit 15, to PB-L0 of MAC 16B. Furthermore, the Bifurcation switch circuit S4 branches the channel PA-L1 of host port 21A, which is connected to physical layer PHY6 of physical layer interface circuit 15, to PA-L1 of host port 21A of MAC 16A. Finally, the Bifurcation switch circuit S4 branches the channel PA-L0 of host port 21A, which is connected to physical layer PHY7 of physical layer interface circuit 15, to PA-L0 of MAC 16A.

[0093] As described above, by using the Bifurcation switch circuit S4, each channel connected to the physical layer interface circuit 15 is correctly branched to MAC16A / MAC16B, and even when the controller 10 is mounted on the back side 12c of the substrate 12, the channel number of the signal line between the connection part 14 and the controller 10 will not be reversed.

[0094] However, such variations require a large number of switches, which can complicate the wiring within the SoC. However, by considering timing convergence on the mounting surface during wiring design, the timing of each signal can be properly synchronized.

[0095] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A controller, comprising: A physical layer interface circuit corresponding to a dual-port system with a first port and a second port conforming to the PCIe standard, the first port including a first number of channels assigned a first order, and the second port including a second number of channels assigned a second order, the first number of channels and the second number of channels being connected to the physical layer interface circuit via wiring arranged in the following order: the order is a combination of the first order and the second order, which are swapped based on channel position flipping conforming to the PCIe standard. The first PCIe MAC layer circuit, i.e. the first PCIe media access control layer circuit, and the second PCIe MAC layer circuit, i.e. the second PCIe media access control layer circuit, are configured corresponding to each of the first ports and the second ports, and are connected to the physical layer interface circuit based on the channel position flip. A signal processing circuit includes a first terminal and a second terminal. The first terminal receives a portion of a signal from a first auxiliary signal line, which is different from the first signal line corresponding to a first number of channels, and transmits the sideband signal of the first port. The second terminal receives a portion of a signal from a second auxiliary signal line, which is different from the second signal line corresponding to a second number of channels, and transmits the sideband signal of the second port. as well as The switching circuit, based on the channel position flip, is capable of switching the routing of a portion of the signals of the first auxiliary signal line and the routing of a portion of the signals of the second auxiliary signal line relative to each terminal of the first terminal and the second terminal of the signal processing circuit. Furthermore, it is capable of switching the routing of other portions of the signals of the first auxiliary signal line and the routing of other portions of the signals of the second auxiliary signal line between the physical layer interface circuit and the first PCIe MAC layer circuit and the second PCIe MAC layer circuit.

2. The controller according to claim 1, The switching circuit includes a first circuit that switches between the first port and the second port the interrupt detection of the reset signal, which is used by the host to reset the bus used in communication corresponding to the PCIe standard, as a sideband signal.

3. The controller according to claim 1 or 2, The switching circuit includes: A second circuit switches between the first port and the second port the reference differential clock signal, which is the sideband signal, sent from the host in the physical layer interface circuit; and The third circuit switches the disappearance detection signal of the reference differential clock signal between the first port and the second port.

4. A controller, comprising: A physical layer interface circuit corresponding to a dual-port system with a first port and a second port conforming to the PCIe standard, the first port including a first number of channels assigned a first order, and the second port including a second number of channels assigned a second order, the first number of channels and the second number of channels being connected to the physical layer interface circuit via wiring arranged in the following order: the order is a combination of the first order and the second order, which are swapped based on channel position flipping conforming to the PCIe standard. The first PCIe MAC layer circuit, i.e. the first PCIe media access control layer circuit, and the second PCIe MAC layer circuit, i.e. the second PCIe media access control layer circuit, are configured corresponding to each of the first ports and the second ports, and are connected to the physical layer interface circuit based on the channel position flip. A signal processing circuit includes a first terminal and a second terminal. The first terminal receives a portion of a signal from a first auxiliary signal line, which is different from the first signal line corresponding to a first number of channels, and transmits the sideband signal of the first port. The second terminal receives a portion of a signal from a second auxiliary signal line, which is different from the second signal line corresponding to a second number of channels, and transmits the sideband signal of the second port. as well as A switching circuit, based on the channel position flip, performs a path switching to the first PCIe MAC layer circuit and the second PCIe MAC layer circuit for the first number of channels and the second number of channels connected to the physical layer interface circuit.

5. A storage system comprising: substrate; A connecting portion is disposed on the substrate and corresponds to the dual ports of the first port and the second port; Semiconductor memory chips, which are mounted on the substrate; and The controller according to any one of claims 1 to 4 is mounted on the second surface of the substrate, which is opposite to the connection portion, and controls the operation of the semiconductor memory chip.

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