Display panel

Abstract

The embodiment of the present application provides a display panel. The display panel comprises a driving substrate and a light emitting device which is bound on the driving substrate. The driving substrate comprises a driving circuit and a first power line, and the first power line comprises a conductive pad. The light emitting device comprises a first pad and a second pad. The first pad is overlapped with and bound on the conductive pad, and the second pad is electrically connected with the driving circuit. The embodiment of the present application overlaps and binds the opaque first pad with the first power line, specifically, overlaps and binds the first pad with the conductive pad. Thus, the overlapping area of the first pad and the first power line is increased, the opaque area in the display panel is reduced, the layout space in the display panel is saved, and the aperture ratio and the transparency of the display panel are increased.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel. Background Technology

[0002] Currently, transparent LED display panel technology is becoming a trend in the display industry. In transparent LED display panels, the aperture ratio of the display area affects the degree of transparency. Improving the aperture ratio is a crucial optimization direction for achieving true transparency. Transparent display panels contain opaque components and opaque metal traces. How to strategically arrange these components and traces to maximize the aperture ratio is a pressing research topic in the industry.

[0003] Therefore, for transparent display panels, it is urgent to optimize the layout of opaque components and opaque metal traces within the display panel in order to improve the aperture ratio of the transparent display panel. Summary of the Invention

[0004] The purpose of this application is to provide a display panel that improves the aperture ratio of the display panel by optimizing the layout of opaque devices and opaque metal traces within the display panel.

[0005] To address the above technical problems, this application provides a display panel, including...

[0006] A driving substrate, the driving substrate including a driving circuit and a first power line, the first power line including a conductive pad.

[0007] A light-emitting device is bonded to the driving substrate. The light-emitting device includes a first pad and a second pad, the first pad overlapping and bonded to the conductive pad, and the second pad being electrically connected to the driving circuit.

[0008] In some embodiments, the first power line is a cathode power line, and the driving substrate further includes a second power line, which is an anode power line.

[0009] The driving circuit includes scan lines, data lines, a first thin-film transistor, and a second thin-film transistor.

[0010] The gate of the first thin-film transistor is electrically connected to the scan line, the source of the first thin-film transistor is electrically connected to the data line, and the drain of the first thin-film transistor is electrically connected to the gate of the second thin-film transistor. The source of the second thin-film transistor is electrically connected to the second power line, and the drain of the second thin-film transistor is electrically connected to the second pad of the light-emitting device.

[0011] In some embodiments, the first power line is an anode power line, and the driving substrate further includes a second power line, which is a cathode power line.

[0012] The driving circuit includes scan lines, data lines, a first thin-film transistor, and a second thin-film transistor.

[0013] The gate of the first thin-film transistor is electrically connected to the scan line, the source of the first thin-film transistor is electrically connected to the data line, and the drain of the first thin-film transistor is electrically connected to the gate of the second thin-film transistor. The drain of the second thin-film transistor is electrically connected to the second power line, and the source of the second thin-film transistor is electrically connected to the second pad of the light-emitting device.

[0014] In some embodiments, the first power line and the second power line are arranged to cross each other. The first power line and the second power line are insulated from each other.

[0015] The first power line includes a first conductive layer and a second conductive layer disposed on a different layer from the first conductive layer, and the first conductive layer and the second conductive layer are connected together. The second power line includes a third conductive layer, which is disposed on the same layer as the second conductive layer but spaced apart.

[0016] In some embodiments, the second power line includes a fourth conductive layer, which is separate from and connected to the third conductive layer.

[0017] The fourth conductive layer is on the same layer as the first conductive layer and is spaced apart.

[0018] Alternatively, the fourth conductive layer may be located on the side of the third conductive layer that is away from the first conductive layer.

[0019] In some embodiments, the first power line includes a first segment and a second segment connected together, the first segment extending along a first direction and the second segment extending along a second direction intersecting the first direction.

[0020] The second power line includes a third segment and a fourth segment connected together, wherein the third segment extends along the first direction and the fourth segment extends along the second direction.

[0021] The first pad overlaps with and is bound to the first line segment.

[0022] In some embodiments, the width of the first line segment is greater than the width of the second line segment.

[0023] In some embodiments, the first line segment and the second line segment are arranged on the same layer.

[0024] In some embodiments, the display panel further includes a first driving module and a second driving module. The first driving module and the second driving module are disposed on the same side of the display panel. The first driving module is connected to the data line, and the second driving module is connected to the scan line.

[0025] In some embodiments, the scan line includes a fifth line segment and a sixth line segment connected together, the fifth line segment extending along a first direction and the sixth line segment extending along a second direction intersecting the first direction.

[0026] The data line extends along the second direction. The second drive module is connected to the sixth line segment.

[0027] This application provides a display panel. The display panel includes a driving substrate and light-emitting devices bonded to the driving substrate. The driving substrate includes a driving circuit and a first power line, the first power line including a conductive pad. The light-emitting device includes a first pad and a second pad. The first pad overlaps with and is bonded to the conductive pad, and the second pad is electrically connected to the driving circuit.

[0028] This application embodiment overlaps and bonds the opaque first pad with the first power line, specifically by overlapping and bonding the first pad with a conductive pad. This increases the overlap area of ​​the first pad and the first power line, reduces the opaque area within the display panel, thereby saving layout space within the display panel and increasing the aperture ratio and transparency of the display panel. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of the display panel provided in the first embodiment of this application;

[0031] Figure 2 yes Figure 1 An enlarged view of a portion A of the central display panel;

[0032] Figure 3 yes Figure 1 An enlarged schematic diagram of the intersection point B between the first and second power lines of the display panel;

[0033] Figure 4 yes Figure 1 A cross-sectional view of the intersection point B of the first and second power lines of the display panel along the second direction.

[0034] Figure 5 yes Figure 1 A schematic diagram showing the connection between the data line of the central display panel and the first driving module, and the connection between the scan line and the second driving module;

[0035] Figure 6 This is a schematic cross-sectional view of the intersection B of the first power line and the second power line of the display panel provided in the second embodiment of this application along the second direction.

[0036] Figure 7 This is a schematic diagram of the structure of the display panel provided in the third embodiment of this application.

[0037] Reference numerals: 100 - Display panel; 10 - Driving substrate; T - Driving circuit; T1 - First thin-film transistor; T2 - Second thin-film transistor; L - Light-emitting device; L1 - First pad; L2 - Second pad; V1 - First power line; V11 - First conductive layer; V12 - Second conductive layer; D - Conductive pad; V2 - Second power line; V21 - Third conductive layer; V22 - Fourth conductive layer; I - Insulating layer; I1 - First insulating layer; I2 - Second insulating layer; K - Via; gate - Scan line; data - Data line; COF1 - First driving module; COF2 - Second driving module; x - First direction; y - Second direction; XD1 - First line segment; XD2 - Second line segment; XD3 - Third line segment; XD4 - Fourth line segment; XD5 - Fifth line segment; XD6 - Sixth line segment; A - Local area; B - Intersection of the first power line and the second power line. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] It should be noted that, in the description of this application, the orientations or positional relationships indicated by terms such as "upper," "lower," "front," "back," "left," "right," "inner," and "outer" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0040] Please refer to Figure 1 and Figure 2This application provides a display panel 100 according to a first embodiment. In this first embodiment, the display panel 100 includes a driving substrate 10 and a light-emitting device L bonded to the driving substrate 10. The driving substrate 10 includes a driving circuit T and a first power line V1. The first power line V1 includes a conductive pad D. The light-emitting device L includes a first pad L1 and a second pad L2. The first pad L1 overlaps with and is bonded to the conductive pad D. The second pad L2 is electrically connected to the driving circuit T.

[0041] In this embodiment, the opaque first pad L1 is overlapped and bonded to the first power line V1, specifically by overlapping and bonding the first pad L1 to the conductive pad D. This increases the overlap area of ​​the first pad L1 and the first power line V1, reduces the opaque area within the display panel 100, thereby saving layout space within the display panel 100, improving the panel's transmittance, and increasing the aperture ratio and transparency of the display panel 100.

[0042] Optionally, the light-emitting device L in this application may be a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini-LED), or a micrometer light-emitting diode (Micro-LED), but this application is not limited to these.

[0043] Optionally, the conductive pad D can be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), silver (Ag), titanium (Ti), and iron (Fe), an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. In this embodiment, the conductive pad D is a copper (Cu) sheet. Copper has good conductivity and is easy to melt and bond. When attaching the LED chip, solder is applied to the conductive pad D to melt it, and then the LED chip is attached to the molten area. The molten area cools to form the first bonding pad L1.

[0044] In this first embodiment, the first power line V1 is a cathode power line. The driving substrate 10 also includes a second power line V2, which is an anode power line.

[0045] The driving circuit T includes a scan line gate, a data line data, a first thin-film transistor T1, and a second thin-film transistor T2.

[0046] The gate of the first thin-film transistor T1 is electrically connected to the scan line. The source of the first thin-film transistor T1 is electrically connected to the data line. The drain of the first thin-film transistor T1 is electrically connected to the gate of the second thin-film transistor T2. The source of the second thin-film transistor T2 is electrically connected to the second power line V2. The drain of the second thin-film transistor T2 is electrically connected to the second pad L2 of the light-emitting device L.

[0047] Understandably, the first power line V1 is the cathode power line. Therefore, the first pad L1 overlaps with the cathode power line, increasing the overlap area between them. This reduces the opaque area within the display panel 100, increasing the aperture ratio and transparency of the display panel 100. Furthermore, the layout space saved by the overlapping of the first pad L1 with the cathode power line allows for the placement of more light-emitting devices L, thereby increasing pixel density.

[0048] It should be noted that the gate of the first thin-film transistor T1 is electrically connected to the scan line gate. When a high-level signal is applied to the scan line gate, the first thin-film transistor T1 is turned on. The signal of the data line data connected to the source of the first thin-film transistor T1 is transmitted to the drain. Since the drain of the first thin-film transistor T1 is electrically connected to the gate of the second thin-film transistor T2, when the first thin-film transistor T1 is turned on and the signal of the data line data is a high-level signal, the second thin-film transistor T2 is turned on. The turning on of the second thin-film transistor T2 connects the second pad L2 of the light-emitting device L to the anode power line and the first pad L1 to the cathode power line, thereby causing the light-emitting device L to emit light.

[0049] Optionally, the metal layer containing the data line and the metal layer containing the scan line gate can be insulated from different layers, or they can be in the same layer with an insulating gap.

[0050] Please refer to Figure 3 and Figure 4 In this first embodiment, the first power line V1 and the second power line V2 are arranged in a cross configuration. The first power line V1 and the second power line V2 are insulated from each other.

[0051] The first power line V1 includes a first conductive layer V11 and a second conductive layer V12 disposed on a different layer from the first conductive layer V11. The first conductive layer V11 and the second conductive layer V12 are connected together. The second power line V2 includes a third conductive layer V21, which is disposed on the same layer as the second conductive layer V12 but spaced apart.

[0052] It should be noted that, in order for the light-emitting device L to be arranged within the display panel 100, the first power line V1 and the second power line V2 need to be arranged crosswise. The crosswise arrangement of the second power line V2 and the first power line V1 allows the light-emitting device L, which overlaps with and is bound to the first power line V1, to be connected to the second power line V2.

[0053] Understandably, reducing the resistance of the first power line V1 within the display panel 100 can improve its transmission efficiency, thereby enhancing the luminous efficiency of the display panel 100. The first power line V1 includes a first conductive layer V11 and a second conductive layer V12 that are connected and overlapped. This reduces the resistance of the first power line V1 while avoiding widening its trace width. Avoiding an increase in the trace width of the first power line V1 reduces the obstruction of the first power trace to the transparency of the display panel 100, increasing the aperture ratio. Since the first power line V1 and the second power line V2 are insulated, the third conductive layer V21 and the second conductive layer V12 are co-layered and insulated from each other, with a gap between them. This arrangement results in a smaller thickness at the overlap between the second power line V2 and the first power line V1, which helps reduce the film thickness.

[0054] Optionally, an insulating layer I is further provided between the first conductive layer V11 and the second conductive layer V12. A through-hole K is formed in the insulating layer I, and the first conductive layer V11 and the second conductive layer V12 are connected through the through-hole K.

[0055] In this first embodiment, the second power line V2 may further include a fourth conductive layer V22, which is disposed on a different layer than the third conductive layer V21 but connected thereto. The fourth conductive layer V22 is disposed on the same layer as the first conductive layer V11 but spaced apart from it.

[0056] Understandably, the second power line V2 includes a third conductive layer V21 and a fourth conductive layer V22 that are connected and overlapped in different layers. This reduces the resistance of the second power line V2 while avoiding increasing its width. Avoiding an increase in the width of the second power line V2 reduces the obstruction of the second power line to the transparency of the display panel 100, thus improving the aperture ratio. Since the first power line V1 and the second power line V2 are insulated, the fourth conductive layer V22 and the first conductive layer V11 are on the same layer and insulated, but spaced apart. This arrangement results in a smaller thickness at the overlap between the second power line V2 and the first power line V1, which helps reduce the film thickness.

[0057] In this first embodiment, an insulating layer I is further provided between the fourth conductive layer V22 and the third conductive layer V21. A via K is formed in the insulating layer I, and the fourth conductive layer V22 and the third conductive layer V21 are connected through the via K.

[0058] Understandably, since the fourth conductive layer V22 and the first conductive layer V11 are disposed in the same layer, and the third conductive layer V21 and the second conductive layer V12 are disposed in the same layer, the insulating layer I between the fourth conductive layer V22 and the third conductive layer V21 can be the same layer as the insulating layer I between the first conductive layer V11 and the second conductive layer V12. This saves film layers and reduces film thickness. This insulating layer I prevents the first conductive layer V11 and the third conductive layer V21 from contacting at the intersection of the first power line V1 and the second power line V2, thereby avoiding short circuits caused by the connection of the first power line V1 and the second power line V2.

[0059] This application embodiment uses a multi-layer conductive layer stacking design for the first power line V1 or the second power line V2 to reduce the resistance of the first power line V1 or the second power line V2, thereby avoiding widening the trace width and increasing the aperture ratio. In this first embodiment, both the first power line V1 and the second power line V2 include two conductive layers. Optionally, the first power line V1 may include two conductive layers, and the second power line V2 may include one conductive layer. Alternatively, the first power line V1 may include one conductive layer, and the second power line V2 may include two conductive layers. Furthermore, the first power line V1 may include three conductive layers, and the second power line V2 may include one conductive layer. This application does not impose any limitations on these aspects.

[0060] Please refer to this again. Figure 1 In this first embodiment, the first power line V1 includes a first segment XD1 and a second segment XD2 connected together. The first segment XD1 extends along a first direction x. The second segment XD2 extends along a second direction y that intersects the first direction x.

[0061] The second power line V2 includes a connected third segment XD3 and a fourth segment XD4. The third segment XD3 extends along a first direction x, and the fourth segment XD4 extends along a second direction y.

[0062] The first pad L1 overlaps with the first line segment XD1 and is bound together.

[0063] Understandably, the first segment XD1 of the first power line V1 is used to overlap and bond with the first pad L1 of the light-emitting device L, so that the light-emitting device L is arranged along the first direction x. The second segment XD2 of the first power line V1 is used to transmit power signals. The third segment XD3 of the second power line V2 extends along the first direction x to facilitate electrical connection with the light-emitting device L arranged along the first direction x.

[0064] The fourth segment XD4 of the second power line V2 is used to transmit power signals.

[0065] In this first embodiment, the width of the first line segment XD1 is greater than the width of the second line segment XD2.

[0066] Understandably, the first pad L1 overlaps with and is bound to the first line segment XD1. The width of the first line segment XD1 is greater than the width of the second line segment XD2 to facilitate the binding of the first pad L1 with the first line segment XD1.

[0067] In this first embodiment, the first line segment XD1 and the second line segment XD2 are arranged on the same layer.

[0068] Understandably, connecting the first line segment XD1 and the second line segment XD2 and setting them in the same layer can reduce the film thickness and save on processes, as the first line segment XD1 and the second line segment XD2 can be set in one patterning process.

[0069] Please refer to Figure 5 In this first embodiment, the display panel 100 further includes a first driving module COF1 and a second driving module COF2. The first driving module COF1 and the second driving module COF2 are disposed on the same side of the display panel 100. The first driving module COF1 is connected to the data line, and the second driving module COF2 is connected to the scan line gate.

[0070] Understandably, the first driving module COF1 is used to emit data signals, and the second driving module COF2 is used to emit scan signals. Placing the first driving module COF1 and the second driving module COF2 on the same side of the display panel 100 allows for the other sides of the display panel 100 to be left unused for splicing. Using the sides without the first driving module COF1 and the second driving module COF2 for splicing allows for seamless splicing of the display panels 100.

[0071] In this first embodiment, the scan line gate includes a fifth line segment XD5 and a sixth line segment XD6 connected together. The fifth line segment XD5 extends along a first direction x, and the sixth line segment XD6 extends along a second direction y that intersects with the first direction x.

[0072] The data line extends along the second direction y. The second driver module COF2 is connected to the sixth segment XD6.

[0073] Understandably, the data line extends along the second direction y, and the sixth segment XD6 of the scan line gate also extends along the second direction y. Since the first driving module COF1 and the second driving module COF2 are located on the same side of the display panel 100, the data line and the sixth segment XD6 extend out of the display panel 100 in the same direction, facilitating connection with the first driving module COF1 and the second driving module COF2 located on the same side of the display panel 100.

[0074] Please refer to Figure 6 , Figure 6 This is a cross-sectional view of the intersection B of the first power line V1 and the second power line V2 along the second direction y of the display panel 100 provided in the second embodiment of this application. The second embodiment of this application provides a display panel 100. The difference between this second embodiment and the first embodiment is that in this second embodiment, the second power line V2 includes a fourth conductive layer V22. The fourth conductive layer V22 and the third conductive layer V21 are separate layers but connected. The fourth conductive layer V22 is located on the side of the third conductive layer V21 away from the first conductive layer V11.

[0075] Specifically, since the third conductive layer V21 and the second conductive layer V12 are on the same layer and spaced apart, a first insulating layer I1 is also included between the first conductive layer V11 and the third conductive layer V21 to prevent the first conductive layer V11 from contacting the third conductive layer V21 and causing the first power line V1 and the second power line V2 to connect. A fourth conductive layer V22 is disposed on the side of the third conductive layer V21 away from the first conductive layer V11, and is configured to connect the fourth conductive layer V22 to the third conductive layer V21. Optionally, a second insulating layer I2 is provided between the second conductive layer V12 and the fourth conductive layer V22, and a through-hole K is formed in the second insulating layer I2, through which the first conductive layer V11 and the second conductive layer V12 are connected.

[0076] Understandably, the second power line V2 includes a third conductive layer V21 and a fourth conductive layer V22 that are connected and overlapped in different layers. This reduces the resistance of the second power line V2 while avoiding increasing its trace width. Avoiding an increase in the trace width of the second power line V2 reduces the obstruction of the second power line trace to the transparency of the display panel 100, thus improving the aperture ratio.

[0077] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of the display panel 100 provided in the third embodiment of this application. The third embodiment of this application also provides a display panel 100. The difference between this third embodiment and the first or second embodiment is that in this third embodiment, the first power line V1 is an anode power line. The driving substrate 10 also includes a second power line V2. The second power line V2 is a cathode power line.

[0078] The driving circuit T includes a scan line gate, a data line data, a first thin-film transistor T1, and a second thin-film transistor T2.

[0079] The gate of the first thin-film transistor T1 is electrically connected to the scan line. The source of the first thin-film transistor T1 is electrically connected to the data line. The drain of the first thin-film transistor T1 is electrically connected to the gate of the second thin-film transistor T2. The drain of the second thin-film transistor T2 is electrically connected to the second power supply line V2. The source of the second thin-film transistor T2 is electrically connected to the second pad L2 of the light-emitting device L.

[0080] Understandably, the first power line V1 is the anode power line. Therefore, the first pad L1 overlaps with the anode power line, increasing the overlap area between them. This reduces the opaque area within the display panel 100, increasing the aperture ratio and transparency of the display panel 100. Furthermore, the layout space saved by the overlapping of the first pad L1 with the anode power line allows for the placement of more light-emitting devices L, thereby increasing pixel density.

[0081] It should be noted that the gate of the first thin-film transistor T1 is electrically connected to the scan line gate. When a high-level signal is applied to the scan line gate, the first thin-film transistor T1 is turned on. The signal of the data line data connected to the source of the first thin-film transistor T1 is transmitted to the drain. Since the drain of the first thin-film transistor T1 is electrically connected to the gate of the second thin-film transistor T2, when the first thin-film transistor T1 is turned on and the signal of the data line data is a high-level signal, the second thin-film transistor T2 is turned on. The turning on of the second thin-film transistor T2 connects the second pad L2 of the light-emitting device L to the cathode power line and the first pad L1 to the anode power line, thereby causing the light-emitting device L to emit light.

[0082] The above provides a detailed description of a display panel provided in this application.

[0083] This application provides a display panel. The display panel includes a driving substrate and light-emitting devices bonded to the driving substrate. The driving substrate includes a driving circuit and a first power line, the first power line including a conductive pad. The light-emitting device includes a first pad and a second pad. The first pad overlaps with and is bonded to the conductive pad, and the second pad is electrically connected to the driving circuit.

[0084] This application embodiment overlaps and bonds the opaque first pad with the first power line, specifically by overlapping and bonding the first pad with a conductive pad. This increases the overlap area of ​​the first pad and the first power line, reduces the opaque area within the display panel, thereby saving layout space within the display panel and increasing the aperture ratio and transparency of the display panel.

[0085] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A display panel, characterized in that, include: A driving substrate, the driving substrate including a driving circuit and a first power line, the first power line including a conductive pad; and A light-emitting device is bonded to the driving substrate; the light-emitting device includes a first pad and a second pad, the first pad overlaps with and is bonded to the conductive pad, and the second pad is electrically connected to the driving circuit. The first power line includes a first segment and a second segment connected together. The first segment extends along a first direction, and the second segment extends along a second direction intersecting the first direction. The second power line includes a third segment and a fourth segment connected together, wherein the third segment extends along the first direction and the fourth segment extends along the second direction; The first pad overlaps with and is bound to the first line segment. The width of the first line segment is greater than the width of the second line segment. The first line segment and the second line segment are set on the same layer.

2. The display panel according to claim 1, characterized in that, The first power line is a cathode power line, and the driving substrate further includes a second power line, which is an anode power line. The driving circuit includes scan lines, data lines, a first thin-film transistor, and a second thin-film transistor. The gate of the first thin-film transistor is electrically connected to the scan line, the source of the first thin-film transistor is electrically connected to the data line, and the drain of the first thin-film transistor is electrically connected to the gate of the second thin-film transistor; the source of the second thin-film transistor is electrically connected to the second power line, and the drain of the second thin-film transistor is electrically connected to the second pad of the light-emitting device.

3. The display panel according to claim 1, characterized in that, The first power line is an anode power line, and the driving substrate further includes a second power line, which is a cathode power line. The driving circuit includes scan lines, data lines, a first thin-film transistor, and a second thin-film transistor. The gate of the first thin-film transistor is electrically connected to the scan line, the source of the first thin-film transistor is electrically connected to the data line, and the drain of the first thin-film transistor is electrically connected to the gate of the second thin-film transistor; the drain of the second thin-film transistor is electrically connected to the second power line, and the source of the second thin-film transistor is electrically connected to the second pad of the light-emitting device.

4. The display panel according to claim 1, characterized in that, The first power line and the second power line are arranged to cross each other, and the first power line and the second power line are insulated from each other. The first power line includes a first conductive layer and a second conductive layer disposed on a different layer from the first conductive layer, and the first conductive layer and the second conductive layer are connected together; the second power line includes a third conductive layer, and the third conductive layer is disposed on the same layer as the second conductive layer but spaced apart.

5. The display panel according to claim 4, characterized in that, The second power line includes a fourth conductive layer, which is separate from and connected to the third conductive layer; The fourth conductive layer is disposed on the same layer as the first conductive layer and spaced apart; or... The fourth conductive layer is located on the side of the third conductive layer away from the first conductive layer.

6. The display panel according to claim 2 or 3, characterized in that, The display panel further includes a first driving module and a second driving module, which are disposed on the same side of the display panel. The first driving module is connected to the data line, and the second driving module is connected to the scan line.

7. The display panel according to claim 6, characterized in that, The scan line includes a fifth line segment and a sixth line segment connected together. The fifth line segment extends along a first direction, and the sixth line segment extends along a second direction intersecting the first direction. The data line extends along the second direction; the second drive module is connected to the sixth line segment.

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