A trench silicon carbide MOSFET device

Abstract

The present invention discloses a trench-type silicon carbide MOSFET device. The device includes a heavily doped second-conductivity-type heterogeneous material region at the bottom of the trench region, and a heavily doped second-conductivity-type semiconductor shielding layer and a lightly doped first-conductivity-type semiconductor region between the trench region and the first-conductivity-type semiconductor drift region. The heavily doped second-conductivity-type heterogeneous material region is located at the bottom of the trench region and contacts the heavily doped second-conductivity-type semiconductor shielding layer and the lightly doped first-conductivity-type semiconductor region. The sidewalls of the lightly doped first-conductivity-type semiconductor region contact the heavily doped second-conductivity-type semiconductor shielding layer. The above solution can achieve low-voltage conduction of the device, reduce conduction losses, increase breakdown voltage, and reduce reverse leakage. It can also optimize the avalanche path, improve the avalanche withstand capability of the device, and enhance device reliability. It also improves the device's third-quadrant conduction performance and reliability.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of power semiconductor technology, and in particular to a trench silicon carbide MOSFET device. Background Art

[0002] The performance of traditional silicon-based semiconductor devices has gradually approached the physical limits of the material. Devices made of third-generation semiconductor materials represented by silicon carbide (SiC) have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance. They can achieve higher power density and higher efficiency, and have broad application prospects in the field of high-power, high-temperature and high-frequency power electronics.

[0003] As a representative of silicon carbide switching devices, silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) has the advantages of low switching loss, high operating frequency, easy driving, and suitability for parallel use. It has gradually been promoted and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible direct current transmission. However, due to the large bandgap width of silicon carbide materials, the body diode of silicon carbide MOSFET has a high forward turn-on voltage drop (V ON >2.7V), increasing device conduction losses. Simultaneously, when the body diode is conducting, the injected non-equilibrium minority carriers are stored, and when the diode is turned off, the reverse recovery process also increases device losses. Furthermore, due to the low stacking fault energy on the basal plane of silicon carbide, basal plane dislocations can split into Shockley partial dislocations under external forces, generating stacking faults that cause bipolar degradation and reliability issues. Therefore, when using silicon carbide MOSFETs, an external silicon carbide Schottky diode is generally connected in reverse parallel, but this introduces additional parasitic parameters and increases system manufacturing costs. In addition, due to the wide bandgap and low intrinsic carrier concentration of SiC MOSFETs, the parasitic bipolar junction transistor (BJT) in SiC MOSFETs is unlikely to be activated during typical unclamped inductive switching (UIS) events, but instead has gate oxide reliability issues. The BJT may fail due to the injection of hot holes, which significantly reduces the threshold voltage, increases leakage current, and causes electron current to enter the source terminal. Therefore, special attention needs to be paid to the gate oxide electric field and reliability issues of SiC MOSFETs during avalanche. Summary of the Invention

[0004] In view of this, the present invention provides a trench silicon carbide MOSFET device to improve the body diode degradation phenomenon, reduce the reverse leakage of the device, optimize the avalanche path, improve the avalanche tolerance, and thus improve the reliability of the device.

[0005] In a first aspect, an embodiment of the present invention provides a trench silicon carbide MOSFET device, comprising:

[0006] A metallized drain, a heavily doped first conductivity type semiconductor substrate, a lightly doped first conductivity type semiconductor drift region, and a metallized source are stacked from bottom to top; a first conductivity type semiconductor current extension region, a second conductivity type semiconductor body region, a heavily doped second conductivity type semiconductor contact region, and a heavily doped first conductivity type semiconductor source region are further included between the lightly doped first conductivity type semiconductor drift region and the metallized source; the first conductivity type semiconductor current extension region is in contact with the lightly doped first conductivity type semiconductor drift region, and the heavily doped second conductivity type semiconductor contact region and the heavily doped first conductivity type semiconductor source region are both in ohmic contact with the metallized source;

[0007] The trench silicon carbide MOSFET device further includes a trench region, the trench region extending downward from a surface of the heavily doped first conductive type semiconductor source region toward the metallized source electrode to the first conductive type semiconductor current extension region; a gate dielectric layer is provided on a portion of the sidewalls of the trench region, the gate dielectric layer being in contact with the heavily doped first conductive type semiconductor source region, the second conductive type semiconductor body region, and a portion of the first conductive type semiconductor current extension region;

[0008] A heavily doped second conductive type semiconductor shielding layer and a lightly doped first conductive type semiconductor region are further provided between the trench region and the first conductive type semiconductor drift region; a heavily doped second conductive type heterogeneous material region and a heavily doped first conductive type polysilicon gate electrode region, which are insulated from each other, are provided inside the trench region; the heavily doped second conductive type heterogeneous material region is electrically connected to the metallized source, the heavily doped second conductive type heterogeneous material region is located at the bottom of the trench region and is in contact with the heavily doped second conductive type semiconductor shielding layer and the lightly doped first conductive type semiconductor region; the sidewalls of the lightly doped first conductive type semiconductor region are in contact with the heavily doped second conductive type semiconductor shielding layer; wherein the band gap width of the heterogeneous material forming the heavily doped second conductive type heterogeneous material region is smaller than the band gap width of silicon carbide.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows:

[0010] Optionally, an insulating dielectric layer is further provided in the trench region; the insulating dielectric layer covers the heavily doped second conductivity type heterogeneous material region;

[0011] The heavily doped first conductivity type polysilicon gate electrode region is located on a surface of the insulating dielectric layer on a side away from the heavily doped second conductivity type heterogeneous material region.

[0012] Optionally, the insulating dielectric layer fills the bottom corner of the trench region; and the heavily doped second conductivity type semiconductor shielding layer covers the insulating dielectric layer at the bottom corner.

[0013] Optionally, the trench silicon carbide MOSFET device may further include an inter-electrode dielectric layer, which is located on the surface of the side of the heavily doped first conductive type polysilicon gate electrode region away from the insulating dielectric layer; the inter-electrode dielectric layer is used to separate the heavily doped first conductive type polysilicon gate electrode region and the metallized source.

[0014] Optionally, the trench silicon carbide MOSFET device may also include a heavily doped first conductivity type polysilicon shielding gate electrode region, wherein the heavily doped first conductivity type polysilicon shielding gate electrode region is located between the heavily doped second conductivity type heterogeneous material region and the heavily doped first conductivity type polysilicon gate electrode region; the heavily doped first conductivity type polysilicon shielding gate electrode region has the same potential as the metallized source.

[0015] Optionally, the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region includes at least one of silicon, polysilicon, germanium, germanium silicon and gallium arsenide.

[0016] Optionally, the insulating dielectric layer includes oxide or low-k dielectric.

[0017] Optionally, the thickness of the insulating dielectric layer along a first direction is greater than the thickness of the gate dielectric layer along a second direction; the first direction is parallel to the extension direction of the trench region, and the second direction is perpendicular to the first direction.

[0018] Optionally, the doping concentration of the heavily doped region is above 1E19 cm-3, and the doping concentration of the lightly doped region is above 5E16 cm-3. -3 the following.

[0019] Optionally, the doping concentration of the first conductive type semiconductor current extension region is 1.1 to 1000 times the doping concentration of the lightly doped first conductive type semiconductor drift region.

[0020] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

[0021] Optionally, the metallized source and the metallized drain both include any one or more of titanium, titanium nitride, tungsten titanium, silver, aluminum, nickel, platinum, copper, silicon or gold.

[0022] In the embodiment of the present invention, a heavily doped second conductivity type semiconductor shielding layer and a lightly doped first conductivity type semiconductor region are provided between the trench region and the first conductivity type semiconductor drift region; a heavily doped second conductivity type heterogeneous material region and a heavily doped first conductivity type polysilicon gate electrode region are provided in the trench region (which are insulated from each other); the heavily doped second conductivity type heterogeneous material region is electrically connected to the metallized source, the heavily doped second conductivity type heterogeneous material region is located at the bottom of the trench region and is in contact with the heavily doped second conductivity type semiconductor shielding layer and the lightly doped first conductivity type semiconductor region; the sidewalls of the lightly doped first conductivity type semiconductor region are electrically connected to the metallized source. The heavily doped second conductivity type semiconductor shielding layer contacts the heavily doped second conductivity type heterogeneous material region, wherein the bandgap width of the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region is smaller than the bandgap width of silicon carbide. The above technical solution improves the device's reverse freewheeling capability and reliability, improves the device's reverse leakage, and reduces system power consumption and manufacturing costs without sacrificing device area or original performance. It also adds an additional avalanche current path, improving the device's avalanche withstand capability. When the device operates in the third quadrant, it can achieve low-voltage conduction, effectively reducing conduction losses and improving the device's third-quadrant conduction performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic structural diagram of a trench silicon carbide MOSFET device provided in an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of an equivalent circuit structure of a trench silicon carbide MOSFET device provided in an embodiment of the present invention;

[0025] Figure 3 A schematic structural diagram of another trench silicon carbide MOSFET device provided in an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of current distribution during breakdown of a heterojunction diode provided by an embodiment of the present invention;

[0027] Figure 5 A breakdown characteristic curve of a heterojunction diode provided by an embodiment of the present invention;

[0028] Figure 6 An energy band diagram of a heterojunction diode provided by an embodiment of the present invention;

[0029] Figure 7 A current distribution diagram of a trench silicon carbide MOSFET device during avalanche provided by an embodiment of the present invention;

[0030] Figure 8A current distribution diagram of a silicon carbide MOSFET device during avalanche in a related technology provided by an embodiment of the present invention.

[0031] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0032] 1 is a heavily doped first conductivity type semiconductor substrate, 2 is a metallized drain, 3 is a lightly doped first conductivity type semiconductor drift region, 4 is a metallized source, 5 is a first conductivity type semiconductor current extension region, 6 is a second conductivity type semiconductor body region, 7 is a heavily doped second conductivity type semiconductor contact region, 8 is a heavily doped first conductivity type semiconductor source region, 9 is a trench region, 10 is a gate dielectric layer, 11 is a heavily doped second conductivity type semiconductor shield layer, 12 is a lightly doped first conductivity type semiconductor region, 13 is a heavily doped second conductivity type heterogeneous material region, 14 is a heavily doped first conductivity type polysilicon gate electrode region, 15 is an insulating dielectric layer, 16 is an inter-electrode dielectric layer, and 17 is a heavily doped first conductivity type polysilicon shield gate electrode region. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0034] Based on the above-mentioned defects of the prior art, the present application provides a trench silicon carbide MOSFET device. Figure 1 A schematic structural diagram of a trench silicon carbide MOSFET device provided in an embodiment of the present invention is provided. Figure 2 Schematic diagram of the equivalent circuit structure of a trench silicon carbide MOSFET device provided by an embodiment of the present invention. Figure 1 and Figure 2 The trench silicon carbide MOSFET device includes: a metallized drain 2, a heavily doped first conductivity type semiconductor substrate 1, a lightly doped first conductivity type semiconductor drift region 3, and a metallized source 4 stacked from bottom to top; a first conductivity type semiconductor current extension region 5, a second conductivity type semiconductor body region 6, a heavily doped second conductivity type semiconductor contact region 7, and a heavily doped first conductivity type semiconductor source region 8 are further included between the lightly doped first conductivity type semiconductor drift region 3 and the metallized source 4; the first conductivity type semiconductor current extension region 5 is in contact with the lightly doped first conductivity type semiconductor drift region 3, and the heavily doped second conductivity type semiconductor contact region 7 and the heavily doped first conductivity type semiconductor source region 8 are both in ohmic contact with the metallized source 4;

[0035] The trench-type silicon carbide MOSFET device further includes a trench region 9, which extends downward from the heavily doped first conductive type semiconductor source region 8 toward the metallized source electrode 4 to the first conductive type semiconductor current extension region 5; a gate dielectric layer 10 is provided on part of the sidewall of the trench region 9, and the gate dielectric layer 10 is in contact with the heavily doped first conductive type semiconductor source region 8, the second conductive type semiconductor body region 6 and part of the first conductive type semiconductor current extension region 5 respectively; a heavily doped second conductive type semiconductor shielding layer 11 and a lightly doped first conductive type semiconductor region 12 are further provided between the trench region 9 and the first conductive type semiconductor drift region 3; within the trench region 9 A heavily doped second conductivity type heterogeneous material region 13 and a heavily doped first conductivity type polysilicon gate electrode region 14 are provided insulated from each other; the heavily doped second conductivity type heterogeneous material region 13 is electrically connected to the metallized source 4, and the heavily doped second conductivity type heterogeneous material region 13 is located at the bottom of the trench region 9 and is in contact with the heavily doped second conductivity type semiconductor shielding layer 11 and the lightly doped first conductivity type semiconductor region 12; the sidewalls of the lightly doped first conductivity type semiconductor region 12 are in contact with the heavily doped second conductivity type semiconductor shielding layer 11; wherein, the bandgap width of the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region 13 is smaller than the bandgap width of silicon carbide.

[0036] Specifically, if Figure 1 and Figure 2 As shown, the trench silicon carbide MOSFET device provided by an embodiment of the present invention, hereinafter referred to as the "device," comprises a heavily doped first conductivity type semiconductor substrate 1, a metallized drain 2 located on one side surface of the heavily doped first conductivity type semiconductor substrate 1, and the metallized drain 2 can be defined as being located on the lower surface or back surface of the heavily doped first conductivity type semiconductor substrate 1, with the metallized drain 2 pointing from bottom to top toward the heavily doped first conductivity type semiconductor substrate 1. A lightly doped first conductivity type semiconductor drift region 3 is disposed on the upper surface or front surface of the heavily doped first conductivity type semiconductor substrate 1. A first conductivity type semiconductor current extension region 5 and a second conductivity type semiconductor body region 6 are disposed on the upper surface of the lightly doped first conductivity type semiconductor drift region 3, stacked in sequence. A heavily doped first conductivity type semiconductor source region 8 and a heavily doped second conductivity type semiconductor contact region 7 are disposed on the upper surface of the second conductivity type semiconductor body region 6. The sidewalls of the heavily doped first conductivity type semiconductor source region 8 and the heavily doped second conductivity type semiconductor contact region 7 are in contact with each other. The trench silicon carbide MOSFET device also includes a metallized source 4. The upper surfaces of the heavily doped first conductivity type semiconductor source region 8 and the heavily doped second conductivity type semiconductor contact region 7 are both in direct contact with the metallized source 4 through ohmic contacts. The second conductivity type semiconductor body region 6, the heavily doped first conductivity type semiconductor source region 8, and the heavily doped second conductivity type semiconductor contact region 7 form the body diode of the trench silicon carbide MOSFET device.

[0037] For further reference, Figure 1 and Figure 2 The trench silicon carbide MOSFET device is further provided with a trench region 9, which extends downward from the surface of the heavily doped first conductivity type semiconductor source region 8 to a portion of the depth of the first conductivity type semiconductor current extension region 5. That is, the bottom surface of the trench region 9 exceeds the lower surface of the second conductivity type semiconductor body region 6 and is located within the first conductivity type semiconductor current extension region 5. The sidewalls of the trench region 9 are in contact with the sidewalls of the heavily doped first conductivity type semiconductor source region 8, the second conductivity type semiconductor body region 6, and a portion of the first conductivity type semiconductor current extension region 5.

[0038] The trench region 9 is internally provided with a mutually insulated heavily doped second conductivity type heterogeneous material region 13 and a heavily doped first conductivity type polysilicon gate electrode region 14. The heavily doped first conductivity type polysilicon gate electrode region 14 is provided above the trench region 9. The upper surface of the heavily doped first conductivity type polysilicon gate electrode region 14 may be parallel to and in contact with the upper surfaces of the heavily doped first conductivity type semiconductor source region 8 and the heavily doped second conductivity type semiconductor contact region 7. The lower surface of the heavily doped first conductivity type polysilicon gate electrode region 14 may be located below the lower surface of the second conductivity type semiconductor body region 6. Portions of the sidewalls of the trench region 9 are also covered with a gate dielectric layer 10, which is used to isolate the heavily doped first conductivity type semiconductor source region 8, the second conductivity type semiconductor body region 6, and a portion of the first conductivity type semiconductor current extension region 5 from the heavily doped first conductivity type polysilicon gate electrode region 14. The heavily doped second conductivity type heterogeneous material region 13 is located at the bottom of the trench region 9.

[0039] In addition, in the present application, a heavily doped second conductive type semiconductor shielding layer 11 and a lightly doped first conductive type semiconductor region 12 are also arranged between the trench region 9 and the first conductive type semiconductor drift region 3. The heavily doped second conductive type semiconductor shielding layer 11 and the lightly doped first conductive type semiconductor region 12 are both located outside the bottom of the trench region 9 and are both in direct contact with the heavily doped second conductive type heterogeneous material region 13.

[0040] In this configuration, the heavily doped second conductive type heterogeneous material region 13 and the lightly doped first conductive type semiconductor region 12 can form a heterojunction diode HJD. Figure 2As shown, the heterojunction diode HJD is connected in parallel with the device's body diode D1 between the source S and drain D. Because the bandgap of the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region 13 is smaller than that of silicon carbide, the integrated heterojunction diode HJD has a lower barrier height than the body diode D1 of the silicon carbide MOSFET device itself. During forward conduction, the heterojunction diode HJD turns on in advance of the body diode D1 in the device, suppressing the conduction of the body diode D1 and avoiding the problem of device reliability degradation caused by degradation of the body diode D1. Figure 2 In the description, the first conductivity type is N-type and the second conductivity type is P-type, that is, the device is an N-type semiconductor device, but the invention is not limited thereto. Figure 2 In the figure, R1 and R2 represent the resistance of different film regions.

[0041] In addition, in the present application, the heavily doped second conductivity type heterogeneous material region 13 is electrically connected to the metallized source 4 using a through-hole through layout design (the electrical connection is not shown in the figure). The heavily doped second conductivity type heterogeneous material region 13 and the metallized source 4 have the same potential. When the device operates in the third quadrant, a current path is formed from the source, heterojunction, drift region, substrate to drain, achieving low-voltage conduction of the device.

[0042] In addition, reference Figure 1 The direction parallel to the extension direction of the trench region 9 can be defined as a first direction X, and the direction perpendicular to the extension direction of the trench region 9 can be defined as a second direction Y. The first direction X is the direction in which the lightly doped first conductivity type semiconductor region 12 and the heavily doped second conductivity type heterogeneous material region 13 are stacked. In this embodiment, along the second direction Y, the lightly doped first conductivity type semiconductor region 12 can be positioned between the heavily doped second conductivity type semiconductor shield layer 11, and the length of the lightly doped first conductivity type semiconductor region 12 along the second direction Y is less than the length of the heavily doped second conductivity type heterogeneous material region 13 along the second direction Y. In this way, the heavily doped second conductivity type semiconductor shield layer 11 is in direct contact with both sides of the bottom of the heavily doped second conductivity type heterogeneous material region 13. When avalanche breakdown occurs in the device, the avalanche current can be promptly discharged through the drift region, shield layer, heterojunction, and source, preventing device burnout. Furthermore, the avalanche current discharge path is further away from the heavily doped first conductivity type polysilicon gate electrode region 14, which also improves the device's avalanche resistance. At the same time, since the side walls of the lightly doped first conductive type semiconductor region 12 are covered by the heavily doped second conductive type semiconductor shielding layer 11, when the device is subjected to reverse withstand voltage, the lightly doped first conductive type semiconductor region 12 can be completely depleted by the heavily doped second conductive type semiconductor shielding layer 11, thereby reducing the reverse leakage of the heterojunction diode and further improving the reliability of the device.

[0043] It will be understood by those skilled in the art that the barrier height of the heterojunction diode formed by the heavily doped second conductivity type heterogeneous material region 13 and the lightly doped first conductivity type semiconductor region 12 is related to the selected heterogeneous material, the doping concentration of the heterogeneous material, etc. The embodiments of the present invention do not limit the specific type and doping concentration of the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region 13. Those skilled in the art can select the heterogeneous material according to actual needs, as long as the band gap of the heterogeneous material is smaller than the band gap of the silicon carbide material.

[0044] In an embodiment of the present invention, a heavily doped second conductivity type semiconductor shielding layer 11 and a lightly doped first conductivity type semiconductor region 12 are arranged between the trench region 9 and the first conductivity type semiconductor drift region 3; a heavily doped second conductivity type heterogeneous material region 13 and a heavily doped first conductivity type polysilicon gate electrode region 14 that are insulated from each other are arranged inside the trench region 9; the heavily doped second conductivity type heterogeneous material region 13 is electrically connected to the metallized source 4, and the heavily doped second conductivity type heterogeneous material region 13 is located at the bottom of the trench region 9 and is in contact with the heavily doped second conductivity type semiconductor shielding layer 11 and the lightly doped first conductivity type semiconductor region 12; the sidewalls of the lightly doped first conductivity type semiconductor region 12 are in contact with the heavily doped second conductivity type semiconductor shielding layer 11; wherein, the band gap width of the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region 13 is smaller than the band gap width of silicon carbide. By adopting the above technical solution, the reverse freewheeling capability and reliability of the device are improved without sacrificing the device area and original performance, the reverse leakage of the heterojunction diode is reduced, and the system power consumption and manufacturing cost are reduced; an additional avalanche current path is added, thereby improving the avalanche withstand capability of the device; when the device operates in the third quadrant, a current path is formed from the source, heterojunction, drift region, substrate to the drain, realizing low-voltage conduction of the device, effectively reducing conduction loss, and improving the third-quadrant conduction performance and reliability of the device.

[0045] Optional, you can continue to refer to Figure 1 In a possible embodiment, an insulating dielectric layer 15 may also be provided in the trench region 9; the insulating dielectric layer 15 covers the heavily doped second conductivity type heterogeneous material region 13; and the heavily doped first conductivity type polysilicon gate electrode region 14 is located on a side surface of the insulating dielectric layer 15 away from the heavily doped second conductivity type heterogeneous material region 13.

[0046] Specifically, if Figure 1As shown, in the embodiment of the present application, an insulating dielectric layer 15 may be provided at the bottom of the trench region 9. The insulating dielectric layer 15 covers the heavily doped second conductivity type heterogeneous material region 13. The heavily doped first conductivity type polysilicon gate electrode region 14 may be formed on a surface of the insulating dielectric layer 15 facing away from the heavily doped second conductivity type heterogeneous material region 13. In other words, the insulating dielectric layer 15 surrounds the top and sidewalls of the heavily doped second conductivity type heterogeneous material region 13, and the heavily doped second conductivity type heterogeneous material region 13 and the heavily doped first conductivity type polysilicon gate electrode region 14 are isolated by the insulating dielectric layer 15.

[0047] Optional, you can continue to refer to Figure 1 In a possible embodiment, the insulating dielectric layer 15 may fill the bottom corner of the trench region 9 ; the heavily doped second conductivity type semiconductor shielding layer 11 covers the insulating dielectric layer 15 at the bottom corner.

[0048] Specifically, if Figure 1 As shown, the insulating dielectric layer 15 can be filled inside the trench region 9 of a certain depth, so that the inner side of the bottom corner of the trench region 9 is covered by the insulating dielectric layer 15. At this time, the insulating dielectric layer 15 at the bottom corner can be wrapped by the heavily doped second conductivity type semiconductor shielding layer 11. When the device withstands reverse voltage, the heavily doped second conductivity type semiconductor shielding layer 11 will deplete and pinch off the lightly doped first conductivity type semiconductor region 12 around the heterojunction, so that the heterojunction is completely surrounded by the depletion region, effectively protecting the heterojunction interface, reducing the reverse leakage of the heterojunction diode, and ensuring that the breakdown voltage of the device is not affected.

[0049] In this configuration, the gate dielectric layer 10 can cover the sidewalls of the trench region 9 that are not covered by the insulating dielectric layer 15 .

[0050] Optional, you can continue to refer to Figure 1 In a possible embodiment, the device may further include an inter-electrode dielectric layer 16, which is located on the surface of the heavily doped first conductive type polysilicon gate electrode region 14 facing away from the insulating dielectric layer 15; the inter-electrode dielectric layer 16 is used to separate the heavily doped first conductive type polysilicon gate electrode region 14 and the metallized source 4.

[0051] Specifically, an inter-electrode dielectric layer 16 may be further provided above the trench region 9. The inter-electrode dielectric layer 16 covers the surface of the heavily doped first conductivity type polysilicon gate electrode region 14 that faces away from the insulating dielectric layer 15. The metallized source 4 covers the inter-electrode dielectric layer 16. The inter-electrode dielectric layer 16 is used to isolate the heavily doped first conductivity type polysilicon gate electrode region 14 from the metallized source 4 to prevent mutual interference between the two.

[0052] Optional, Figure 3 A schematic diagram of the structure of another trench silicon carbide MOSFET device provided in an embodiment of the present invention can be referred to Figure 3 In a possible embodiment, the trench silicon carbide MOSFET device may further include a heavily doped first conductivity type polysilicon shielding gate electrode region 17, which is located between the heavily doped second conductivity type heterogeneous material region 13 and the heavily doped first conductivity type polysilicon gate electrode region 14; the heavily doped first conductivity type polysilicon shielding gate electrode region 17 has the same potential as the metallized source 4.

[0053] Specifically, if Figure 3 As shown, in this embodiment, a heavily doped first conductive type polysilicon shielding gate electrode region 17 can also be formed in the trench region 9. The heavily doped first conductive type polysilicon shielding gate electrode region 17 can be formed between the heavily doped second conductive type heterogeneous material region 13 and the heavily doped first conductive type polysilicon gate electrode region 14; and can be separated from the heavily doped first conductive type polysilicon gate electrode region 14 by an insulating dielectric layer 15.

[0054] Among them, the heavily doped first conductive type polysilicon shielding gate electrode region 17 can be made to have the same potential as the metallized source 4. In this way, when the device is reversely withstand voltage, the heavily doped first conductive type polysilicon shielding gate electrode region 17 can shield the electric field at the gate dielectric layer 10 at the corner of the heavily doped first conductive type polysilicon gate electrode region 14, further improving the reliability of the gate dielectric layer 10 and preventing the device from breaking down prematurely.

[0055] For example, in a possible embodiment, the heterogeneous material forming the heavily doped second conductivity type heterogeneous material region 13 includes at least one of silicon, polysilicon, germanium, silicon germanium, and gallium arsenide.

[0056] Specifically, in an embodiment of the present application, silicon, polysilicon, germanium, germanium silicon or gallium arsenide materials can be used to form a heavily doped second conductive type heterogeneous material region 13. The band gap width of the above materials is smaller than the band gap width of silicon carbide material, which can ensure that the barrier height of the heterojunction diode is smaller than the barrier height of the body diode.

[0057] Optionally, in a possible embodiment, the insulating dielectric layer 15 includes an oxide or a low-k dielectric. In this embodiment, the insulating dielectric layer 15 can be formed using an oxide or a low-k dielectric. A low-k dielectric is a material with a low dielectric constant. Oxides and low-k dielectrics have good insulation properties and can provide good isolation.

[0058] In a preferred embodiment, a low-k dielectric can be selected to form the insulating dielectric layer 15, thereby reducing the gate-source capacitance of the device and improving the switching speed of the device.

[0059] Of course, the material for preparing the insulating dielectric layer 15 is not limited thereto, and those skilled in the art can select appropriate materials according to actual needs, and this application does not impose any limitation thereto.

[0060] Optional, you can continue to refer to Figure 1 or Figure 3 In a possible embodiment, the thickness of the insulating dielectric layer 15 along the first direction X is greater than the thickness of the gate dielectric layer 10 along the second direction Y; the first direction X is parallel to the extension direction of the trench region 9, and the second direction Y is perpendicular to the first direction X.

[0061] Specifically, the insulating dielectric layer 15 is used to isolate the heavily doped second conductivity type heterogeneous material region 13 and the heavily doped first conductivity type polysilicon gate electrode region 14 stacked along the first direction X; the gate dielectric layer 10 is used to isolate the heavily doped first conductivity type polysilicon gate electrode region 14 and the heavily doped first conductivity type semiconductor source region 8, as well as the heavily doped first conductivity type polysilicon gate electrode region 14 and the second conductivity type semiconductor body region 6, stacked along the second direction Y. In this embodiment, the thickness of the insulating dielectric layer 15 along the first direction X can be set to be greater than the thickness of the gate dielectric layer 10 along the second direction Y. With this configuration, when avalanche breakdown occurs in the device, the avalanche current can be diverted away from the gate dielectric layer 10, further improving device reliability.

[0062] Optionally, in the present application, light doping and heavy doping are two relative parameters. The embodiments of the present invention do not limit the specific doping concentrations of the lightly doped region and the heavily doped region, and those skilled in the art can set them according to actual needs.

[0063] For example, in a possible embodiment, the doping concentration of the heavily doped region may be set at 1E19 cm -3 Above, the doping concentration of the lightly doped region can be set at 5E16cm -3 This configuration can achieve good ohmic contact between the film structure and the metal electrode in the device, thereby improving device performance.

[0064] Optionally, in a possible embodiment, the doping concentration of the first conductive type semiconductor current extension region 5 may be 1.1 to 1000 times the doping concentration of the lightly doped first conductive type semiconductor drift region 3 , so as to achieve the purpose of reducing the on-resistance.

[0065] Optionally, in a possible embodiment, the first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

[0066] Specifically, when the first conductivity type is N-type and the second conductivity type is P-type, the device is an N-type semiconductor device; when the first conductivity type is P-type and the second conductivity type is N-type, the device is a P-type semiconductor device. The conductivity type of each film layer can be changed by changing the type of doping ions in each film layer. The specific method for adjusting the conductivity type of the film layer by adjusting the ion doping conditions can be performed by any known means by those skilled in the art, and this is not elaborated on or limited in the embodiments of the present invention.

[0067] For example, in a preferred embodiment, the first conductivity type may be N-type, and the second conductivity type may be P-type. The operating principle of the trench silicon carbide MOSFET device provided by this application is described below using an N-type semiconductor device as an example. The metallized drain electrode 2 may be referred to as the drain electrode, and the metallized source electrode 4 may be referred to as the source electrode.

[0068] For example, when the device is forward-conducting, the gate potential is positive, that is, the heavily doped N-type polysilicon gate electrode region 14 is at a positive voltage, so that the P-type semiconductor body region 6 forms an inversion layer near the side wall of the trench region 9, enabling the flow of electrons from the source to the drain.

[0069] When the device withstands reverse voltage, the gate and source are at zero potential, and the drain is connected to a high potential. The device achieves voltage withstand through mutual depletion of the heavily doped P-type semiconductor shielding layer 11 and the lightly doped N-type semiconductor drift region 3, as well as mutual depletion of the P-type semiconductor body region 6 and the N-type semiconductor current extension region 5. The heavily doped P-type semiconductor shielding layer 11 wraps around the corner of the bottom of the trench region 9. When the reverse bias voltage reaches a certain value, the heavily doped P-type semiconductor shielding layer 11 will deplete and pinch off the lightly doped N-type semiconductor region 12 around the heterojunction, so that the heterojunction is completely surrounded by the depletion region, effectively protecting the heterojunction interface, reducing the reverse leakage of the heterojunction diode, and ensuring that the breakdown voltage of the device is not affected. Figure 4 A schematic diagram of current distribution when a heterojunction diode provided by an embodiment of the present invention breaks down is shown. Figure 5 This is a breakdown characteristic curve of the heterojunction diode provided by an embodiment of the present invention. Figure 4 Figure (a) shows the current distribution of the heterojunction diode formed by the heavily doped P-type heterogeneous material region 13 and the lightly doped N-type semiconductor region 12. Figure 4 Figure (b) shows the current distribution of the heterojunction diode formed by the heavily doped N-type heterogeneous material region and the lightly doped N-type semiconductor region 12. Figure 4 The darker the grayscale of the middle color, the greater the current passing through it; Figure 5 The middle curve a is the breakdown characteristic curve of the heterojunction diode formed by the heavily doped P-type heterogeneous material region 13 and the lightly doped N-type semiconductor region 12. Figure 5 The middle curve b is the breakdown characteristic curve of the heterojunction diode formed by the heavily doped N-type heterogeneous material region and the lightly doped N-type semiconductor region 12. Figure 4and Figure 5 Compared with the heterojunction diode formed by the heavily doped N-type heterogeneous material region and the lightly doped N-type semiconductor region 12, the heterojunction diode formed by the heavily doped P-type heterogeneous material region 13 and the lightly doped N-type semiconductor region 12 has a higher breakdown voltage and a smaller reverse current. This is because the barrier heights at the interfaces of the two heterojunction diodes are different, such as Figure 6 As shown, Figure 6 Figure (a) shows the energy band diagram of the heterojunction diode formed by the heavily doped P-type heteromaterial region 13 and the lightly doped N-type semiconductor region 12. It can be seen that the barrier height of the heterojunction formed by the heavily doped P-type heteromaterial region 13 and the lightly doped N-type semiconductor region 12 is 1.66 eV. Figure (b) shows the energy band diagram of the heterojunction diode formed by the heavily doped N-type heteromaterial region and the lightly doped N-type semiconductor region 12. It can be seen that the barrier height of the heterojunction formed by the heavily doped N-type heteromaterial region and the lightly doped N-type semiconductor region 12 is 0.67 eV. The barrier height at the interface of the heterojunction diode formed by the heavily doped P-type heteromaterial region 13 and the lightly doped N-type semiconductor region 12 is higher, while the barrier height at the interface of the heterojunction diode formed by the heavily doped N-type heteromaterial region and the lightly doped N-type semiconductor region 12 is lower. Therefore, the heterojunction diode formed by the heavily doped P-type heteromaterial region 13 and the lightly doped N-type semiconductor region 2 has a higher breakdown voltage and a smaller reverse current.

[0070] Figure 7 A current distribution diagram of a trench silicon carbide MOSFET device during avalanche provided by an embodiment of the present invention, Figure 8 This is a current distribution diagram of a silicon carbide MOSFET device during avalanche in a related technology provided by an embodiment of the present invention. The darker the grayscale in the figure, the greater the current passing through. Figure 7 As shown, when the device is in an avalanche state, since the heavily doped second conductivity type semiconductor shielding layer 11 is in direct contact with both sides of the bottom of the heavily doped second conductivity type heterogeneous material region 13, the avalanche current can be discharged in time through the path of drift region, shielding layer, heterogeneous material to the source. Figure 8 In the prior art, the silicon carbide MOSFET device in an avalanche state, due to the absence of heavily doped second conductivity type heterogeneous material region 13, can only discharge the avalanche current through the drift region, current expansion region, and the path from the body diode to the source. This can cause reliability issues in the device's gate dielectric layer and easily cause the device to burn out. Therefore, the structure of the present invention changes the avalanche current path, directing it away from the gate dielectric layer, thereby improving device reliability.

[0071] In addition, when the device operates in the third quadrant, the gate should be at zero potential or negative potential, the drain should be at zero potential, and the source should be connected to a positive voltage. Since the heavily doped P-type heterogeneous material region 13 is in direct contact with the lightly doped N-type semiconductor region 12 to form a heterojunction structure, and the heavily doped P-type heterogeneous material region 13 is at the same potential as the metallized source 4, a heterojunction diode structure is realized. The present invention utilizes the characteristics of the heterojunction diode with low turn-on voltage drop and unipolar conductivity, so that the forward turn-on voltage drop V ON <1.5V, achieving fast turn-on of the device, effectively reducing the third quadrant conduction loss and improving the reverse recovery performance of the device.

[0072] Optionally, the embodiments of the present invention do not limit the materials used to prepare the metallized source electrode 4 and the metallized drain electrode 2. Those skilled in the art may select materials based on actual needs. For example, in possible embodiments, the metallized source electrode 4 and the metallized drain electrode 2 may each include any one or more of titanium, titanium nitride, tungsten titanium, silver, aluminum, nickel, platinum, copper, silicon, or gold.

[0073] Specifically, in this embodiment, the metallized source 4 and the metallized drain 2 can be prepared using any one or more combinations of titanium, titanium nitride, tungsten titanium, silver, aluminum, nickel, platinum, copper, silicon or gold, but are not limited thereto.

[0074] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A trench silicon carbide MOSFET device, characterized in that: include: A metallized drain (2), a heavily doped first conductive type semiconductor substrate (1), a lightly doped first conductive type semiconductor drift region (3), and a metallized source (4) are stacked from bottom to top; a first conductive type semiconductor current expansion region (5), a second conductive type semiconductor body region (6), a heavily doped second conductive type semiconductor contact region (7), and a heavily doped first conductive type semiconductor source region (8) are further provided between the lightly doped first conductive type semiconductor drift region (3) and the metallized source (4); the first conductive type semiconductor current expansion region (5) is in contact with the lightly doped first conductive type semiconductor drift region (3), and the heavily doped second conductive type semiconductor contact region (7) and the heavily doped first conductive type semiconductor source region (8) are both in ohmic contact with the metallized source (4); The trench-type silicon carbide MOSFET device further comprises a trench region (9), wherein the trench region (9) extends downward from the heavily doped first conductive type semiconductor source region (8) toward a side surface of the metallized source electrode (4) to the first conductive type semiconductor current extension region (5); a gate dielectric layer (10) is provided on a portion of the sidewall of the trench region (9), and the gate dielectric layer (10) is in contact with the heavily doped first conductive type semiconductor source region (8), the second conductive type semiconductor body region (6), and a portion of the first conductive type semiconductor current extension region (5); A heavily doped second conductive type semiconductor shielding layer (11) and a lightly doped first conductive type semiconductor region (12) are further provided between the trench region (9) and the first conductive type semiconductor drift region (3); a heavily doped second conductive type heterogeneous material region (13) and a heavily doped first conductive type polysilicon gate electrode region (14) are provided insulated from each other inside the trench region (9); the heavily doped second conductive type heterogeneous material region (13) is electrically connected to the metallized source (4), the heavily doped second conductive type heterogeneous material region (13) is located at the bottom of the trench region (9) and is in contact with the heavily doped second conductive type semiconductor shielding layer (11) and the lightly doped first conductive type semiconductor region (12); the sidewall of the lightly doped first conductive type semiconductor region (12) is in contact with the heavily doped second conductive type semiconductor shielding layer (11); wherein the band gap width of the heterogeneous material forming the heavily doped second conductive type heterogeneous material region (13) is smaller than the band gap width of silicon carbide.

2. The trench silicon carbide MOSFET device according to claim 1, characterized in that: An insulating dielectric layer (15) is also provided in the trench region (9); the insulating dielectric layer (15) covers the heavily doped second conductive type heterogeneous material region (13); The heavily doped first conductivity type polysilicon gate electrode region (14) is located on a side surface of the insulating dielectric layer (15) away from the heavily doped second conductivity type heterogeneous material region (13).

3. The trench silicon carbide MOSFET device according to claim 2, characterized in that: The insulating dielectric layer (15) fills the bottom corner of the trench region (9); and the heavily doped second conductive type semiconductor shielding layer (11) covers the insulating dielectric layer (15) at the bottom corner.

4. The trench silicon carbide MOSFET device according to claim 3, characterized in that: The invention also includes an inter-electrode dielectric layer (16), which is located on a surface of the heavily doped first conductive type polysilicon gate electrode region (14) that is away from the insulating dielectric layer (15); the inter-electrode dielectric layer (16) is used to separate the heavily doped first conductive type polysilicon gate electrode region (14) and the metallized source (4).

5. The trench silicon carbide MOSFET device according to claim 3, characterized in that: The invention also includes a heavily doped first conductivity type polysilicon shielding gate electrode region (17), wherein the heavily doped first conductivity type polysilicon shielding gate electrode region (17) is located between the heavily doped second conductivity type heterogeneous material region (13) and the heavily doped first conductivity type polysilicon gate electrode region (14); the heavily doped first conductivity type polysilicon shielding gate electrode region (17) has the same potential as the metallized source (4).

6. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The heterogeneous material forming the heavily doped second conductive type heterogeneous material region (13) includes at least one of silicon, polysilicon, germanium, germanium silicon and gallium arsenide.

7. The trench silicon carbide MOSFET device according to claim 2, characterized in that: The insulating dielectric layer (15) comprises oxide or low-k dielectric.

8. The trench silicon carbide MOSFET device according to claim 3, characterized in that: The thickness of the insulating dielectric layer (15) along a first direction is greater than the thickness of the gate dielectric layer (10) along a second direction; the first direction is parallel to the extension direction of the trench region (9), and the second direction is perpendicular to the first direction.

9. The trench silicon carbide MOSFET device according to claim 1, wherein: The doping concentration of the heavily doped region is 1E19cm -3 Above, the doping concentration of the lightly doped region is 5E16cm -3 the following.

10. The trench silicon carbide MOSFET device according to claim 1, wherein: The doping concentration of the first conductive type semiconductor current extension region (5) is 1.1 to 1000 times the doping concentration of the lightly doped first conductive type semiconductor drift region (3).

11. The trench silicon carbide MOSFET device according to claim 1, wherein: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

12. The trench silicon carbide MOSFET device according to claim 1, wherein: The metallized source (4) and the metallized drain (2) both comprise any one or more of titanium, titanium nitride, tungsten titanium, silver, aluminum, nickel, platinum, copper, silicon or gold.

Images