Back contact battery and manufacturing method thereof, photovoltaic module

Abstract

The present invention discloses a back contact cell and a manufacturing method thereof, and a photovoltaic module, which relate to the technical field of solar cells and are used to simultaneously prevent leakage at the lateral interface and the longitudinal interface of the first doped semiconductor layer and the second doped semiconductor layer. The back contact cell comprises: a silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer. The first passivation layer and the first doped semiconductor layer are sequentially stacked on the backlight surface of the silicon substrate. The second passivation layer and the second doped semiconductor layer are sequentially stacked on the backlight surface. The stacked second passivation layer and the second doped semiconductor layer cover a partial area of ​​the stacked first passivation layer and the first doped semiconductor layer, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer and the first doped semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] Passivated back-contact solar cells refer to solar cells with a passivated contact structure in which both the positive and negative electrodes are located on the back of the cell, with no metal electrode blocking the front. Passivated back-contact solar cells have a large light absorption area and a low carrier recombination rate, which has attracted extensive attention from the photovoltaic academic and industrial communities and has become a hot development direction for high-efficiency solar cell technology.

[0003] However, in existing passivated back-contact solar cells, when one of the two types of passivation contact structures with opposite carrier collection types covers a partial area of ​​the other type, the two are difficult to be separated by a thinner passivation layer, and the risk of leakage current is relatively high, which in turn affects the further improvement of the performance of the passivated back-contact solar cells. Summary of the invention

[0004] The object of the present invention is to provide a back-contact cell and a method for manufacturing the same, as well as a photovoltaic module, for simultaneously preventing leakage at the lateral interface and the longitudinal interface between the first doped semiconductor layer and the second doped semiconductor layer, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0005] In a first aspect, the present invention provides a back-contact battery, which includes: a silicon substrate, a first passivation layer and a first doped semiconductor layer stacked in sequence on a backlight surface of the silicon substrate along the thickness direction of the silicon substrate. A second passivation layer and a second doped semiconductor layer stacked in sequence on the backlight surface along the thickness direction of the silicon substrate. The stacked second passivation layer and the second doped semiconductor layer cover a portion of the stacked first passivation layer and the first doped semiconductor layer, and the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer. An insulating layer is arranged on the backlight surface. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer from the first doped semiconductor layer.

[0006] When the above technical solution is adopted, the first passivation layer and the first doped semiconductor layer are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate. Among them, the passivation contact structure formed by the first passivation layer and the first doped semiconductor layer can achieve excellent interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. Similarly, the passivation contact structure formed by the second passivation layer and the second doped semiconductor layer also has the beneficial effects of the above-mentioned first passivation layer and the first doped semiconductor layer, which will not be repeated here.

[0007] In addition, the stacked second passivation layer and the second doped semiconductor layer cover a portion of the stacked first passivation layer and the first doped semiconductor layer. Furthermore, the back contact battery provided by the present invention also includes an insulating layer arranged on the backlight surface. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer from the first doped semiconductor layer. It can be understood that the insulating layer can not only separate the second passivation layer from the first doped semiconductor layer along the thickness direction of the silicon substrate, but also separate the second passivation layer from the first doped semiconductor layer along the direction parallel to the backlight surface. In this case, the insulating layer can prevent the carriers in the second doped semiconductor layer from passing through the second passivation layer into the first doped semiconductor layer by the tunneling effect, and can also prevent the carriers in the first doped semiconductor layer from passing through the second passivation layer into the second doped semiconductor layer by the tunneling effect. That is to say, the insulating layer can prevent the carriers collected by the second doped semiconductor layer from recombining with the carriers collected by the first doped semiconductor layer of opposite conductivity type, thereby preventing leakage at the lateral interface and the vertical interface between the first doped semiconductor layer and the second doped semiconductor layer, thereby facilitating improving the photoelectric conversion efficiency of the back contact battery.

[0008] As a possible implementation manner, the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.

[0009] When the above technical solution is adopted, in the actual manufacturing process, in order to form the first passivation layer and the first doped semiconductor layer only on a specific area of ​​the backlight surface, it is necessary to pattern the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer. Compared with the patterning method of photolithography combined with wet etching, and ink printing combined with wet etching, the cost of patterning by laser etching process is lower and more suitable for mass production. In addition, because the stacked second passivation layer and the second doped semiconductor layer cover part of the stacked first passivation layer and the first doped semiconductor layer, in the actual manufacturing process, the formation step of the stacked first passivation layer and the first doped semiconductor layer is earlier than the formation step of the stacked second passivation layer and the second doped semiconductor layer. In the above case, since amorphous silicon materials are easy to form polycrystalline silicon or single crystal silicon at high temperatures, and the chemical properties of tunneling passivation materials and polycrystalline silicon are relatively stable at high temperatures, compared with the stacked intrinsic amorphous silicon layer and the doped amorphous silicon layer, the stacked tunneling passivation layer and the doped polycrystalline silicon layer are less sensitive to high-temperature laser thermal damage, and can reduce the impact on the passivation effect during the laser film opening process, further increasing the process window and reducing the process difficulty. Therefore, when the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is a doped polycrystalline silicon layer, a laser etching process can be used to pattern the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer, thereby reducing the manufacturing cost of the back contact battery while ensuring that the first passivation layer and the first doped semiconductor layer have good film quality, which is beneficial to improving the yield and electrical performance of the back contact battery.

[0010] In addition, both the tunnel passivation layer and the doped polysilicon layer can be formed by deposition using low-pressure chemical vapor deposition equipment. The intrinsic amorphous silicon layer and the doped amorphous silicon layer need to be deposited using chemical vapor deposition equipment. Based on this, since the cost of low-pressure chemical vapor deposition equipment is lower than the cost of chemical vapor deposition equipment, when the first passivation layer can also be a tunnel passivation layer, and the first doped semiconductor layer can also be a doped polysilicon layer, the passivation material layer used to manufacture the first passivation layer and the doped semiconductor material layer used to manufacture the first doped semiconductor layer can be deposited by low-pressure chemical vapor deposition equipment, thereby reducing the manufacturing cost of the back contact battery.

[0011] As a possible implementation manner, the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer.

[0012] When the above technical solution is adopted, the intrinsic amorphous silicon layer has a better passivation effect than the tunnel passivation layer. Based on this, compared with the second passivation layer being the tunnel passivation layer and the second doped semiconductor layer being the doped polysilicon layer, when the second passivation layer is the intrinsic amorphous silicon layer and the second doped semiconductor layer, the recombination rate of carriers of opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell can be further improved.

[0013] As a possible implementation, the back contact cell further comprises: an aluminum oxide layer and a silicon nitride layer stacked in sequence on the light-facing surface of the silicon substrate in a direction away from the silicon substrate. Or, the back contact cell further comprises: a silicon oxide layer and a silicon nitride layer stacked in sequence on the light-facing surface of the silicon substrate in a direction away from the silicon substrate.

[0014] When the above technical solution is adopted, the stacked aluminum oxide layer and silicon nitride layer can passivate the light-facing surface, reduce the recombination rate of carriers at the light-facing surface, and further improve the photoelectric conversion efficiency of the back contact battery. In addition, silicon nitride can play a role in anti-reflection, which is conducive to refracting more light from the light-facing surface into the silicon substrate, further improving the utilization rate of light by the back contact battery. On this basis, when a passivation layer of amorphous silicon material is formed on the light-facing surface with a velvet structure of smaller size by a deposition process, epitaxial growth is likely to occur on the top of the velvet structure, so that the thickness of the part of the amorphous silicon material located at the top of the velvet structure is greater than the thickness of the part of the amorphous silicon material located at the base of the velvet structure, resulting in inconsistent thickness of the passivation layer of the amorphous silicon material in various regions, reducing the passivation effect of the passivation layer on the light-facing surface, and also affecting the formation of other film layers on the light-facing surface. Compared with the passivation layer of amorphous silicon material, epitaxial growth does not occur when the passivation layer of aluminum oxide material is deposited on the light-facing surface of the small velvet structure, so that the passivation effect of the passivation layer of aluminum oxide material is better. Therefore, the velvet surface of the light-facing surface of the silicon substrate can be selected from velvet surfaces with smaller pyramid sizes, and velvet surfaces with smaller sizes have better light trapping effects, further improving the silicon substrate's absorption of light. In addition, the beneficial effects of the stacked silicon oxide layer and silicon nitride layer can refer to the beneficial effects analysis of the stacked aluminum oxide layer and silicon nitride layer described above, which will not be repeated here.

[0015] Furthermore, the aluminum oxide layer, silicon nitride layer and silicon oxide layer can all be deposited by atomic layer deposition equipment. The intrinsic amorphous silicon layer needs to be deposited by chemical vapor deposition equipment. Based on this, since the cost of atomic layer deposition equipment is lower than that of chemical vapor deposition equipment, when an aluminum oxide layer (or silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as a passivation anti-reflection layer, an aluminum oxide (or silicon oxide) and silicon nitride layer can be deposited on the light-facing surface by atomic layer deposition equipment, thereby reducing the manufacturing cost of the back contact battery.

[0016] As a possible implementation, along the direction away from the silicon substrate, the insulating layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence. Or, along the direction away from the silicon substrate, the insulating layer includes a silicon oxide layer and a silicon nitride layer stacked in sequence.

[0017] When the above technical solution is adopted, the aluminum oxide layer, silicon nitride layer and silicon oxide layer all have good dielectric properties, which is beneficial for the insulating layer to separate the second passivation layer from the first doped semiconductor layer, thereby increasing the parallel resistance of the back contact battery and reducing the leakage risk of the back contact battery. In addition, aluminum oxide, silicon nitride and silicon oxide can also be used to manufacture a film layer with passivation and / or anti-reflection effects on the light-facing surface. Based on this, when the insulating layer includes a stacked aluminum oxide layer and a silicon nitride layer, or a stacked silicon oxide layer and a silicon nitride layer, the material of the insulating layer is the same as the material of the passivation anti-reflection layer, so that the passivation anti-reflection layer can be formed on the light-facing surface while the insulating layer is formed, which is beneficial to simplify the manufacturing process of the back contact battery and improve the manufacturing efficiency of the back contact battery.

[0018] As a possible implementation, the thickness of the insulating layer is 75nm to 125nm. The thickness of the insulating layer is within this range, which can prevent the part of the carriers collected by the second doped semiconductor layer from being recombined with the carriers collected by the first doped semiconductor layer of opposite conductivity type through the second passivation layer and the insulating layer in turn through the tunneling effect due to the small thickness of the insulating layer, thereby ensuring that the insulating layer has good insulating properties. At the same time, the insulating layer not only separates the second passivation layer from the first doped semiconductor layer along the direction of the silicon substrate, but also separates the second passivation layer from the first doped semiconductor layer along the direction parallel to the backlight surface of the silicon substrate. Therefore, the insulating layer is located at the longitudinal junction of the second passivation layer and the first doped semiconductor layer, and the first doped semiconductor layer and the second doped semiconductor layer are distributed above the backlight surface along the direction parallel to the backlight surface. In this case, it can be understood that when the thickness of the insulating layer is large, the cross-sectional area of ​​the portion of the insulating layer located at the longitudinal junction of the second passivation layer and the first doped semiconductor layer is large, and the surface area of ​​the backlight surface is a constant. Therefore, when the thickness of the insulating layer is 75nm to 125nm, it can also prevent the cross-sectional area of ​​at least one of the first doped semiconductor layer and the second doped semiconductor layer from being reduced due to the large thickness of the insulating layer, thereby affecting its carrier collection ability, ensuring that the carriers generated after the silicon substrate absorbs photons are promptly conducted out by the first doped semiconductor layer and the second doped semiconductor layer, thereby further improving the photoelectric conversion efficiency of the back contact battery.

[0019] As a possible implementation, the light-facing surface of the silicon substrate is a velvet surface, and the width of the tower base of the velvet surface is 1 μm to 3 μm.

[0020] When the above technical solution is adopted, within a certain range, the smaller the width of the tower base of the velvet surface, the better the light-trapping effect of the velvet surface. Based on this, when the light-facing surface of the silicon substrate is a velvet surface and the width of the tower base of the velvet surface is 1μm to 3μm, the width of the tower base of the light-facing surface is relatively small, and the light-facing surface has a higher light-trapping effect. In this case, in the actual application process, a passivation reflective layer made of amorphous silicon materials such as aluminum oxide and silicon oxide that matches the velvet surface with a smaller tower base width can be formed on the light-facing surface, so that more light can be transmitted into the silicon substrate through the light-facing surface, further improving the photoelectric conversion efficiency of the back-contact battery.

[0021] In a second aspect, the present invention further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0022] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0023] In a third aspect, the present invention also provides a method for manufacturing a back-contact battery, which comprises: first, providing a silicon substrate. Next, forming a first passivation layer and a first doped semiconductor layer stacked in sequence on the backlight surface of the silicon substrate along the thickness direction of the silicon substrate. Next, forming an insulating layer on the backlight surface. Next, forming a second passivation layer and a second doped semiconductor layer stacked in sequence on the backlight surface along the thickness direction of the silicon substrate. The stacked second passivation layer and the second doped semiconductor layer cover a portion of the stacked first passivation layer and the first doped semiconductor layer, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer and the first doped semiconductor layer.

[0024] The beneficial effects of the third aspect of the present invention can be analyzed by referring to the beneficial effects of the first aspect, and will not be described in detail here.

[0025] As a possible implementation, forming a first passivation layer and a first doped semiconductor layer in a stacked arrangement includes: first, sequentially forming a passivation material layer covering the backlight surface and an intrinsic semiconductor material layer located on the passivation material layer. Next, performing a diffusion treatment on the intrinsic semiconductor material layer so that the intrinsic semiconductor material layer forms a doped semiconductor material layer, and a doped glass layer is formed on the doped semiconductor material layer. Next, using a laser etching process, a portion of the doped glass layer located on the doped semiconductor material layer is removed. The remaining portion of the doped glass layer forms a mask layer. Next, under the masking action of the mask layer, the portion of the doped semiconductor material layer exposed outside the mask layer and the portion of the passivation material layer exposed outside the mask layer are sequentially removed to form a first passivation layer and a first doped semiconductor layer in a stacked arrangement.

[0026] In the case of adopting the above technical solution, in the actual application process, when the intrinsic semiconductor material layer located on the passivation material layer is diffused, the intrinsic semiconductor material layer is transformed into a doped semiconductor material layer, and a doped glass layer is formed on the surface of the doped semiconductor material layer. The doped glass layer can be, for example, a phosphorus silicate glass layer (PSG) or a borosilicate glass layer (BSG). In this case, after removing part of the doped glass layer located on the doped semiconductor material layer by laser etching, the remaining part of the doped glass layer can form a mask layer, so that the patterning of the doped semiconductor material layer and the passivation material layer can be achieved without the need to form other mask layers such as silicon nitride, which simplifies the manufacturing process of the back contact battery and reduces the manufacturing cost of the back contact battery.

[0027] As a possible implementation, after forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement, and before forming the insulating layer on the backlight surface, the method for manufacturing a back-contact cell further includes: removing the doped glass layer, the doped semiconductor material layer, and the passivation material layer on the light-facing surface and the side surface of the silicon substrate. Next, under the masking action of the mask layer, the light-facing surface of the silicon substrate is subjected to a texturing treatment so that the light-facing surface is a velvet surface. The mask layer is removed.

[0028] When the above technical solution is adopted, as mentioned above, during the texturing process, the mask layer used is obtained by patterning the doped glass layer formed on the doped semiconductor material layer during the diffusion process using a laser etching process, rather than a mask layer such as silicon nitride formed by additional deposition and other processes after obtaining the stacked first passivation layer and the first doped semiconductor layer. This can further simplify the manufacturing process of the back contact battery and reduce the manufacturing cost of the back contact battery.

[0029] As a possible implementation, the thickness of the above-mentioned doped glass layer is 40nm to 60nm. In this case, the thickness of the doped glass layer is within this range, which can prevent the mask layer formed by the remaining part of the doped glass layer from having a poor protective effect due to the small thickness of the doped glass layer, which makes it difficult to protect the first doped semiconductor layer and the first passivation layer located thereunder in the corresponding operation, thereby ensuring that the first doped semiconductor layer and the first passivation layer have good film-forming quality and improving the yield of the back contact battery. At the same time, it can also prevent problems such as reduced manufacturing efficiency and increased manufacturing costs due to the large thickness of the doped glass layer, which is conducive to improving the mass production of the back contact battery.

[0030] As a possible implementation, the diffusion time of the above diffusion treatment is 60 min to 120 min, and the diffusion temperature is 800° C. to 900° C. The beneficial effects in this case are similar to the beneficial effects described above when the thickness of the doped glass layer is 40 nm to 60 nm, which can be referred to above and will not be repeated here.

[0031] As a possible implementation method, a first passivation layer and a first doped semiconductor layer are formed in a stacked arrangement, including: first, a passivation material layer covering the backlight surface and a doped semiconductor material layer located on the passivation material layer are sequentially formed. Next, a laser etching process is used to pattern the doped semiconductor material layer and the passivation material layer to form a first passivation layer and a first doped semiconductor layer in a stacked arrangement. The first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer. The beneficial effects in this case can be referred to the analysis of the beneficial effects of the first passivation layer being a tunneling passivation layer and the first doped semiconductor layer being a doped polysilicon layer as described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 A schematic longitudinal cross-sectional view of a structure of a passivated back-contact solar cell in the related art;

[0034] Figure 2 It is a schematic longitudinal cross-sectional view of another structure of a passivated back-contact solar cell in the related art;

[0035] Figure 3 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0036] Figure 4A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0037] Figure 5 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0038] Figure 6 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 4 ;

[0039] Figure 7 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0040] Figure 8 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 6 ;

[0041] Fig. 9 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 7 ;

[0042] Fig.10 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 8 ;

[0043] Fig.11 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 9 ;

[0044] Fig.12 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 10 ;

[0045] Fig.13 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 10 one;

[0046] Fig.14 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 10 two;

[0047] Fig.15 A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 10 three;

[0048] Fig.16A schematic diagram of a back contact battery during the manufacturing process provided by an embodiment of the present invention Figure 10 Four.

[0049] Figure numerals: 11 is a silicon substrate, 12 is a passivation material layer, 121 is a first passivation layer, 13 is an intrinsic semiconductor material layer, 14 is a doped semiconductor material layer, 141 is a first doped semiconductor layer, 15 is a doped glass layer, 151 is a mask layer, 16 is an insulating material layer, 161 is an insulating layer, 17 is a second passivation layer, 18 is a second doped semiconductor layer, 19 is an aluminum oxide layer, 20 is a silicon nitride layer, 21 is a transparent conductive material layer, 211 is a first transparent conductive layer, 212 is a second transparent conductive layer, 22 is a first electrode, and 23 is a second electrode. DETAILED DESCRIPTION

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0051] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0052] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0054] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] Passivated back-contact solar cells refer to solar cells with a passivated contact structure in which both the positive and negative electrodes are located on the back of the cell, with no metal electrode blocking the front. Passivated back-contact solar cells have a large light absorption area and a low carrier recombination rate, which has attracted extensive attention from the photovoltaic academic and industrial communities and has become a hot development direction for high-efficiency solar cell technology.

[0056] Specifically, Figure 1 and Figure 2 As shown, the passivated back-contact solar cell in the related art generally includes a silicon substrate 11, a first passivation contact structure and a second passivation contact structure. Among them, along the direction parallel to the backlight surface of the silicon substrate 11, the above-mentioned first passivation contact structure and the second passivation contact structure are alternately distributed on the backlight surface. And the second passivation contact structure covers a partial area of ​​the first passivation contact structure. Specifically, along the direction away from the silicon substrate 11, the first passivation contact structure and the second passivation contact structure both include a passivation layer and a doped semiconductor layer stacked in sequence. Based on this, when the passivated back-contact solar cell is in operation, the corresponding types of carriers can pass through the passivation layers included in the first passivation contact structure and the second passivation contact structure respectively through the tunneling effect, and are conducted to the corresponding electrodes through the corresponding doped semiconductor layers included in the first passivation contact structure and the second passivation contact structure, thereby forming a photocurrent.

[0057] However, if Figure 1 and Figure 2As shown, in order to reduce the tunneling resistance of carriers, the thickness of the passivation layer included in the first passivation contact structure and the second passivation contact structure in the passivation back contact solar cell in the related art is usually small when designing. The conductivity type of the doped semiconductor layer included in the first passivation contact structure and the second passivation contact structure is opposite. In this case, when the second passivation contact structure covers a part of the first passivation contact structure, even if an insulating layer is provided at the longitudinal junction of the first passivation contact structure and the second passivation contact structure along the thickness direction of the silicon substrate, the insulating layer can only separate the first passivation contact structure and the second passivation contact structure in the longitudinal direction. At the lateral junction of the first passivation contact structure and the second passivation contact structure, the two are only separated by the passivation layer (for example, by the intrinsic semiconductor layer). However, the thin passivation layer makes it difficult to achieve the isolation of the carriers in the doped semiconductor layer of the first passivation contact structure and the carriers in the doped semiconductor layer of the second passivation contact structure, resulting in a high recombination rate of carriers of opposite conductivity types at the lateral interface between the two, and there is a risk of leakage, which further affects the performance improvement of the passivation back contact solar cell.

[0058] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Fig.13 As shown, the back contact cell includes: a silicon substrate 11 , a first passivation layer 121 , a first doped semiconductor layer 141 , a second passivation layer 17 , a second doped semiconductor layer 18 and an insulating layer 161 .

[0059] like Fig.13 As shown, along the thickness direction of the silicon substrate 11, the first passivation layer 121 and the first doped semiconductor layer 141 are sequentially stacked on the backlight surface of the silicon substrate 11. Along the thickness direction of the silicon substrate 11, the second passivation layer 17 and the second doped semiconductor layer 18 are sequentially stacked on the backlight surface. Among them, the stacked second passivation layer 17 and the second doped semiconductor layer 18 cover a partial area of ​​the stacked first passivation layer 121 and the first doped semiconductor layer 141, and the conductivity type of the second doped semiconductor layer 18 and the first doped semiconductor layer 141 is opposite. The insulating layer 161 is arranged on the backlight surface. The insulating layer 161 is at least located between the second passivation layer 17 and the first doped semiconductor layer 141, and is used to separate the second passivation layer 17 and the first doped semiconductor layer 141.

[0060] Specifically, in terms of conductivity type, the silicon substrate may be an N-type silicon substrate or a P-type silicon substrate. In terms of structure, the specific structure of the silicon substrate may be set according to the actual application scenario. Figure 3 As shown, the silicon substrate 11 may be a silicon substrate on which no film layer is formed, and both the backlight surface and the light-facing surface are polished surfaces. Fig.13As shown, the silicon substrate 11 may also be a silicon substrate on which no film layer is formed and whose light-facing surface is a velvet surface. Compared with the polished surface, the velvet surface structure has a good light trapping effect. Therefore, when the light-facing surface of the silicon substrate 11 is a velvet surface, more light can be refracted from the light-facing surface into the silicon substrate 11, thereby facilitating the improvement of the photoelectric conversion efficiency of the back contact battery. Specifically, when the light-facing surface of the silicon substrate 11 is a velvet surface, the width of the tower base of the velvet surface can be set according to actual needs, and is not specifically limited here.

[0061] For the above-mentioned first passivation layer and first doped semiconductor layer, the material and thickness of the first passivation layer and the first doped semiconductor layer, as well as the doping type and doping concentration of the doping elements in the first doped semiconductor layer can be set according to actual needs, as long as they can be applied to the back contact battery provided in the embodiment of the present invention.

[0062] For example, the first passivation layer may be an intrinsic amorphous silicon layer, and the first doped semiconductor layer may be a doped amorphous silicon layer. In this case, the first passivation layer and the first doped semiconductor layer may form a heterogeneous contact structure. Based on this, since the heterogeneous contact structure has a passivation effect superior to that of the tunnel passivation contact structure, when the stacked first passivation layer and the first doped semiconductor layer form a heterogeneous contact structure, the carrier recombination rate at the interface between the silicon substrate and the first passivation layer may be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.

[0063] For another example, the first passivation layer may be a tunnel passivation layer, and the first doped semiconductor layer may be a doped polysilicon layer. Figures 5 to 7 As shown, in order to form the first passivation layer 121 and the first doped semiconductor layer 141 only on a specific area of ​​the backlight surface, the passivation material layer 12 for manufacturing the first passivation layer 121 and the doped semiconductor material layer 14 for manufacturing the first doped semiconductor layer 141 need to be patterned. Compared with the patterning method of photolithography combined with wet etching and ink printing combined with wet etching, the laser etching process is less expensive and more suitable for mass production. Fig.13As shown, since the stacked second passivation layer 17 and the second doped semiconductor layer 18 cover partial areas of the stacked first passivation layer 121 and the first doped semiconductor layer 141, in the actual manufacturing process, the step of forming the stacked first passivation layer 121 and the first doped semiconductor layer 141 is earlier than the step of forming the stacked second passivation layer 17 and the second doped semiconductor layer 18. In the above case, since amorphous silicon materials are easy to form polycrystalline silicon or single crystal silicon at high temperatures, and the chemical properties of tunneling passivation materials and polycrystalline silicon are relatively stable at high temperatures, compared with the stacked intrinsic amorphous silicon layer and the doped amorphous silicon layer, the stacked tunneling passivation layer and the doped polycrystalline silicon layer are less sensitive to high-temperature laser thermal damage, and can reduce the impact on the passivation effect during the laser film opening process, further increasing the process window and reducing the process difficulty. Therefore, when the first passivation layer 121 is a tunneling passivation layer and the first doped semiconductor layer 141 is a doped polycrystalline silicon layer, a laser etching process can be used to achieve patterning of the passivation material layer 12 for manufacturing the first passivation layer 121 and the doped semiconductor material layer 14 for manufacturing the first doped semiconductor layer 141, thereby reducing the manufacturing cost of the back contact battery while ensuring that the first passivation layer 121 and the first doped semiconductor layer 141 have good film quality, which is beneficial to improving the yield and electrical performance of the back contact battery.

[0064] In addition, both the tunnel passivation layer and the doped polysilicon layer can be formed by deposition using low-pressure chemical vapor deposition equipment. The intrinsic amorphous silicon layer and the doped amorphous silicon layer need to be deposited using chemical vapor deposition equipment. Based on this, since the cost of low-pressure chemical vapor deposition equipment is lower than the cost of chemical vapor deposition equipment, when the first passivation layer can also be a tunnel passivation layer, and the first doped semiconductor layer can also be a doped polysilicon layer, the passivation material layer used to manufacture the first passivation layer and the doped semiconductor material layer used to manufacture the first doped semiconductor layer can be deposited by low-pressure chemical vapor deposition equipment, thereby reducing the manufacturing cost of the back contact battery.

[0065] Specifically, the material of the tunnel passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. The specific material of the tunnel passivation layer can be set according to actual needs.

[0066] For the above-mentioned second passivation layer and the second doped semiconductor layer, the material and thickness of the second passivation layer and the second doped semiconductor layer, as well as the doping type and doping concentration of the doping element in the second doped semiconductor layer can be set according to actual needs. Among them, the conductivity type of the second doped semiconductor layer and the first doped semiconductor layer is opposite. Based on this, in the actual application process, the second doped semiconductor can be a P-type doped semiconductor layer doped with boron or other elements, and the first doped semiconductor layer can be an N-type doped semiconductor layer doped with phosphorus or other elements. Alternatively, the second doped semiconductor layer can be an N-type doped semiconductor layer, and the first doped semiconductor layer can be a P-type doped semiconductor layer.

[0067] In addition, the second passivation layer may be a tunnel passivation layer, and the second doped semiconductor layer may be a doped polysilicon layer. Alternatively, the second passivation layer may be an intrinsic amorphous silicon layer, and the second doped semiconductor layer may be a doped amorphous silicon layer.

[0068] It is worth noting that when the first passivation layer is a tunneling passivation layer, the second doped semiconductor layer is a doped polysilicon layer, the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer, not only can the laser etching process be used to pattern the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer, ensuring that the first passivation layer and the first doped semiconductor layer have good film quality and increasing the process window, but also because the intrinsic amorphous silicon layer has a better passivation effect than the tunneling passivation layer. Based on this, compared with the second passivation layer being a tunneling passivation layer and the second doped semiconductor layer being a doped polysilicon layer, when the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer, the recombination rate of carriers of opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact battery can be further improved.

[0069] Furthermore, the area in which the stacked second passivation layer and the second doped semiconductor layer cover the stacked first passivation layer and the first doped semiconductor layer can be set according to the actual application scenario, and is not specifically limited here.

[0070] For the above-mentioned insulating layer, the insulating layer can be a single-layer structure formed by one or more insulating materials, or the insulating layer can also be a multi-layer composite structure formed by multiple insulating materials. Specifically, the specific structure of the insulating layer can be set according to actual needs. The above-mentioned insulating material can be any material with insulating properties. In addition, the thickness of the insulating layer and the formation range of the insulating layer on the backlight surface can be set according to actual needs, as long as the insulating layer can be at least located between the second passivation layer and the first doped semiconductor layer, and the second passivation layer and the first doped semiconductor layer can be separated by the insulating layer.

[0071] From the above content, we can see that Fig.13 As shown, the insulating layer 161 can not only separate the second passivation layer 17 and the first doped semiconductor layer 141 along the thickness direction of the silicon substrate 11, but also separate the second passivation layer 17 and the first doped semiconductor layer 141 along the direction parallel to the backlight surface. In this case, the insulating layer 161 can prevent the carriers in the second doped semiconductor layer 18 from passing through the second passivation layer 17 to enter the first doped semiconductor layer 141 through the tunneling effect, and can also prevent the carriers in the first doped semiconductor layer 141 from passing through the second passivation layer 17 to enter the second doped semiconductor layer 18 through the tunneling effect. That is, the insulating layer 161 can prevent the carriers collected by the second doped semiconductor layer 18 from recombining with the carriers collected by the first doped semiconductor layer 141 of the opposite conductivity type, thereby preventing leakage at the lateral interface and the longitudinal interface of the first doped semiconductor layer 141 and the second doped semiconductor layer 18 at the same time, thereby facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.

[0072] As a possible implementation, the thickness of the insulating layer is 75nm to 125nm. In this case, the thickness of the insulating layer is within this range, which can prevent the possibility that part of the carriers collected by the second doped semiconductor layer can pass through the second passivation layer and the insulating layer in turn through the tunneling effect and recombine with the carriers collected by the first doped semiconductor layer of opposite conductivity type due to the small thickness of the insulating layer, thereby ensuring that the insulating layer has good insulation performance. At the same time, Fig.13 As shown, the insulating layer 161 not only separates the second passivation layer 17 from the first doped semiconductor layer 141 along the thickness direction of the silicon substrate 11, but also separates the second passivation layer 17 from the first doped semiconductor layer 141 along the direction parallel to the backlight surface of the silicon substrate 11. Therefore, the insulating layer 161 is located at the longitudinal junction of the second passivation layer 17 and the first doped semiconductor layer 141, and the first doped semiconductor layer 141 and the second doped semiconductor layer 18 are distributed above the backlight surface along the direction parallel to the backlight surface. In this case, it can be understood that when the thickness of the insulating layer 161 is large, the cross-sectional area of ​​the portion of the insulating layer 161 located at the longitudinal junction of the second passivation layer 17 and the first doped semiconductor layer 141 is large, and the surface area of ​​the backlight surface is a constant. Therefore, when the thickness of the insulating layer 161 is 75nm to 125nm, it can also prevent the cross-sectional area of ​​one of the first doped semiconductor layer 141 and the second doped semiconductor layer 18 from being reduced due to the large thickness of the insulating layer 161, thereby affecting its carrier collection ability, ensuring that the carriers generated after the silicon substrate 11 absorbs photons are promptly conducted out by the first doped semiconductor layer 141 and the second doped semiconductor layer 18, thereby further improving the photoelectric conversion efficiency of the back contact battery.

[0073] Of course, the thickness of the insulating layer may also be set to other appropriate values ​​according to different application scenario requirements.

[0074] As a possible implementation, Fig.13 As shown, the back contact cell further includes: an aluminum oxide layer 19 and a silicon nitride layer 20 stacked in sequence on the light-facing surface of the silicon substrate 11 in a direction away from the silicon substrate 11. Or, the back contact cell further includes: a silicon oxide layer and a silicon nitride layer stacked in sequence on the light-facing surface of the silicon substrate in a direction away from the silicon substrate.

[0075] Specifically, the thicknesses of the aluminum oxide layer, silicon nitride layer, and silicon oxide layer can be set according to actual needs and are not specifically limited here.

[0076] When the above technical solution is adopted, the stacked aluminum oxide layer and silicon nitride layer can passivate the light-facing surface, reduce the recombination rate of carriers at the light-facing surface, and further improve the photoelectric conversion efficiency of the back contact battery. In addition, the silicon nitride layer can play a role in anti-reflection, which is conducive to refracting more light from the light-facing surface into the silicon substrate, further improving the utilization rate of light by the back contact battery. On this basis, when a passivation layer of amorphous silicon material is formed on the light-facing surface with a velvet structure of smaller size by a deposition process, epitaxial growth is likely to occur on the top of the velvet structure, so that the thickness of the part of the amorphous silicon material located at the top of the velvet structure is greater than the thickness of the part of the amorphous silicon material located at the base of the velvet structure, resulting in inconsistent thickness of the passivation layer of the amorphous silicon material in various regions, reducing the passivation effect of the passivation layer on the light-facing surface, and also affecting the formation of other film layers on the light-facing surface. Compared with the passivation layer of amorphous silicon material, epitaxial growth does not occur when the passivation layer of aluminum oxide material is deposited on the light-facing surface of the small velvet structure, so that the passivation effect of the passivation layer of aluminum oxide material is better. Therefore, the velvet on the light-facing surface of the silicon substrate can be selected from velvet with a smaller pyramid size, and the smaller velvet has a better light trapping effect, further improving the silicon substrate's absorption of light. In addition, the beneficial effects of the above-mentioned stacked silicon oxide layer and silicon nitride layer can refer to the analysis of the beneficial effects of the stacked aluminum oxide layer and silicon nitride layer described above, and will not be repeated here. In addition, the aluminum oxide layer, silicon nitride layer and silicon oxide layer can all be deposited and formed using atomic layer deposition equipment. The intrinsic amorphous silicon layer needs to be deposited and formed using chemical vapor deposition equipment. Based on this, since the cost of atomic layer deposition equipment is lower than that of chemical vapor deposition equipment, when an aluminum oxide layer (or silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as a passivation anti-reflection layer, aluminum oxide (or silicon oxide) and silicon nitride layers can be deposited on the light-facing surface by atomic layer deposition equipment, thereby reducing the manufacturing cost of the back contact battery.

[0077] It should be noted that, in addition to the silicon oxide layer, the silicon nitride layer and the aluminum oxide layer, the material of the film layer with passivation and anti-reflection functions formed on the light-facing surface may also be set to other suitable materials. For example, the film layer with passivation and anti-reflection functions formed on the light-facing surface may also include at least one of a silicon oxynitride layer, a titanium oxide layer and a silicon oxycarbide layer.

[0078] As a possible implementation, Fig.13 As shown, along the direction away from the silicon substrate 11, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer stacked in sequence. Alternatively, along the direction away from the silicon substrate 11, the insulating layer 161 includes a silicon oxide layer and a silicon nitride layer stacked in sequence.

[0079] When the above technical solution is adopted, the aluminum oxide layer, silicon nitride layer and silicon oxide layer all have good dielectric properties, which is beneficial for the insulating layer to separate the second passivation layer from the first doped semiconductor layer, thereby increasing the parallel resistance of the back contact battery and reducing the leakage risk of the back contact battery. In addition, aluminum oxide, silicon nitride and silicon oxide can also be used to manufacture a film layer with passivation and / or anti-reflection effects on the light-facing surface. Based on this, when the insulating layer includes a stacked aluminum oxide layer and a silicon nitride layer, or a stacked silicon oxide layer and a silicon nitride layer, the material of the insulating layer is the same as the material of the passivation anti-reflection layer, so that the passivation anti-reflection layer can be formed on the light-facing surface while the insulating layer is formed, which is beneficial to simplify the manufacturing process of the back contact battery and improve the manufacturing efficiency of the back contact battery.

[0080] It is understandable that, in addition to the silicon oxide layer, silicon nitride layer and aluminum oxide layer, in order to make the material of the insulating layer the same as that of the passivation anti-reflection layer, the insulating layer can also be set to other materials of the film layer with passivation and anti-reflection functions as described above.

[0081] As a possible implementation, Fig.13 As shown, the light-facing surface of the silicon substrate 11 is a velvet surface, and the width of the tower base of the velvet surface is 1 μm to 3 μm.

[0082] When the above technical solution is adopted, within a certain range, the smaller the width of the tower base of the velvet surface is, the better the light trapping effect of the velvet surface is. Based on this, when the light-facing surface of the silicon substrate is a velvet surface and the width of the tower base of the velvet surface is 1μm to 3μm, the width of the tower base of the light-facing surface is relatively small, and the light-facing surface has a higher light trapping effect, which can further improve the photoelectric conversion efficiency of the back contact battery.

[0083] It should be noted that in the existing heterojunction back contact cells, the passivation layer formed on the light-facing surface is usually an amorphous silicon layer. And, as mentioned above, in order to ensure the passivation effect of the amorphous silicon layer located on the light-facing surface on the light-facing surface, it is usually necessary to form it on a velvet structure with a relatively large base width. And within a certain range, the larger the base width of the velvet, the worse the light trapping effect of the velvet. Correspondingly, the higher the reflectivity of the light-facing surface. It can be seen from this that the amorphous silicon passivation layer located on the light-facing surface in the existing heterojunction back contact cells is poorly compatible with the velvet with a smaller base width, and it is difficult to reduce the reflectivity of the light-facing surface to light while improving the passivation effect of the light-facing surface. In this case, in actual application, when the backlight surface of the back-contact battery provided in the embodiment of the present invention is formed with a stacked intrinsic amorphous silicon layer and a doped amorphous silicon layer, a passivation reflective layer made of amorphous silicon materials such as aluminum oxide and silicon oxide that matches the velvet surface with a smaller width of the tower base can be formed on the light-facing surface, thereby improving the passivation effect of the backlight surface and allowing more light to be transmitted through the light-facing surface into the silicon substrate, thereby further improving the photoelectric conversion efficiency of the back-contact battery provided in the embodiment of the present invention.

[0084] In some cases, such as Fig.16 As shown, the back contact battery provided by the embodiment of the present invention may also include a first transparent conductive layer 211, a second transparent conductive layer 212, a first electrode 22 and a second electrode 23. Among them, the first transparent conductive layer 211 is formed at least on the first doped semiconductor layer 141, and the first electrode 22 is located on the portion of the first transparent conductive layer 211 corresponding to the first doped semiconductor layer 141, so as to facilitate the extraction of carriers collected by the first doped semiconductor layer 141. The above-mentioned second transparent conductive layer 212 is formed on the second doped semiconductor layer 18, and the second transparent conductive layer 212 and the first transparent conductive layer 211 are insulated from each other. The second electrode 23 is located on the second transparent conductive layer 212, so as to facilitate the extraction of carriers collected by the second doped semiconductor layer 18.

[0085] The material of the first transparent conductive layer or the second transparent conductive layer can be fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, indium hydroxide, etc. The thickness of the first transparent conductive layer and the second transparent conductive layer can be set according to actual needs and is not specifically limited here. The material of the first electrode and the second electrode can be a conductive material such as silver, aluminum, copper, nickel, etc.

[0086] In a second aspect, an embodiment of the present invention further provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0087] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0088] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a back contact battery. Figures 3 to 16 The cross-sectional view of the back contact battery during the manufacturing process is shown to describe the manufacturing process. Specifically, the manufacturing method of the back contact battery includes the following steps:

[0089] First, if Figure 1 As shown, a silicon substrate 11 is provided. The specific structure of the silicon substrate 11 can be referred to above and will not be described again here.

[0090] In actual application, the doped silicon substrate can be polished in a tank cleaning device using an alkaline cleaning solution such as KOH to obtain a silicon base. In this case, compared with the untreated bare silicon substrate, the backlight side and the light-facing side of the polished silicon substrate are both flat polished surfaces, which facilitates the subsequent formation of a structure that meets the process requirements based on the flat polished surface, thereby improving the yield of the back-contact battery.

[0091] like Figure 7 As shown, along the thickness direction of the silicon substrate 11, a first passivation layer 121 and a first doped semiconductor layer 141 are sequentially stacked on the backlight surface of the silicon substrate 11. Specifically, the materials and thickness of the first passivation layer 121 and the first doped semiconductor layer 141 can be referred to above, and will not be repeated here.

[0092] Exemplarily, the above-mentioned forming of the stacked first passivation layer and the first doped semiconductor layer may include the following steps: Figure 4 As shown in FIG. 1 , a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 located on the passivation material layer 12 are sequentially formed. Figure 5 As shown, the intrinsic semiconductor material layer is diffused to form a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the doped semiconductor material layer 14. Then, a laser etching process is used to remove part of the doped glass layer on the doped semiconductor material layer. The remaining part of the doped glass layer forms a mask layer. Finally, as shown in FIG. Figure 6 and Figure 7 As shown, under the masking effect of the mask layer 151, the portion of the doped semiconductor material layer exposed outside the mask layer and the portion of the passivation material layer exposed outside the mask layer are removed in sequence to form a stacked first passivation layer 121 and a first doped semiconductor layer 141.

[0093] In actual application, the formation process of the first passivation layer and the first doped semiconductor layer can be determined according to the materials of the first passivation layer and the first doped semiconductor layer. For example, when the first passivation layer is a tunnel passivation layer and the first doped semiconductor layer is doped polysilicon, Figure 4As shown, a low pressure chemical vapor deposition (LPCVD) process can be used to sequentially form a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 located on the passivation material layer 12. In the process of forming the passivation material layer 12 and the intrinsic semiconductor material layer 13, a passivation material layer and an intrinsic semiconductor material layer are also formed on the side and light-facing surface of the silicon substrate 11. Then, the intrinsic semiconductor material layer 13 is diffused by a diffusion device. Specifically, as Figure 5 As shown, when the intrinsic semiconductor material layer located on the passivation material layer 12 is diffused, the intrinsic semiconductor material layer is transformed into a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the surface of the doped semiconductor material layer 14. Among them, the processing conditions of the diffusion treatment can be determined according to the doping concentration of the doping element in the first doped semiconductor layer 141, the thickness and density of the doped glass layer 15 to be formed, and the actual application scenario, which are not specifically limited here. Of course, after the diffusion treatment, the above-mentioned wrap-plated intrinsic semiconductor material layer will also form a wrap-plated doped semiconductor material layer, and a wrap-plated doped glass layer will be formed on the wrap-plated doped semiconductor material layer. Then, after the doped glass layer 15 is patterned by a laser etching process, the remaining part of the doped glass layer can form a mask layer. The mask layer covers the part of the doped semiconductor material layer corresponding to the formation of the first doped semiconductor layer. As shown Figure 6 As shown, under the masking effect of the mask layer 151, laser etching, wet etching or dry etching processes can be used to pattern the doped semiconductor material layer and the passivation material layer to form a stacked first passivation layer 121 and a first doped semiconductor layer 141.

[0094] It is worth noting that the mask layer used in the process of patterning the doped semiconductor material layer and the passivation material layer is obtained by patterning the doped glass layer. In other words, the patterning of the doped semiconductor material layer and the passivation material layer can be achieved without the need to form additional mask layers such as silicon nitride, which simplifies the manufacturing process of the back contact battery and reduces the manufacturing cost of the back contact battery.

[0095] Specifically, the specific material of the above-mentioned doped glass layer can be determined according to the material and doping type of the first doped semiconductor layer. For example, when the first doped semiconductor layer is an N-type doped polysilicon layer doped with phosphorus, the doped glass layer is a phosphorus silicon glass layer. For another example, when the first doped semiconductor layer is a P-type doped polysilicon layer doped with boron, the doped glass layer is a borosilicate glass layer.

[0096] In addition, the thickness of the doped glass layer can be set according to actual needs, as long as the mask layer formed by the doped glass layer can have a corresponding masking function.

[0097] Exemplarily, the thickness of the doped glass layer may be 40 nm to 60 nm. For example, the thickness of the doped glass layer may be 40 nm, 45 nm, 50 nm, 55 nm or 60 nm. In this case, the thickness of the doped glass layer is relatively moderate, which can prevent the mask layer formed by the remaining part of the doped glass layer from having a poor protective effect due to the small thickness of the doped glass layer, thereby preventing the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect in the corresponding operation, thereby ensuring that the first doped semiconductor layer and the first passivation layer have good film-forming quality and improving the yield of the back-contact battery. At the same time, it can also prevent problems such as reduced manufacturing efficiency and increased manufacturing costs due to the large thickness of the doped glass layer, which is conducive to improving the mass production of the back-contact battery.

[0098] In addition, the diffusion time of the above diffusion treatment can be 60 min to 120 min, and the diffusion temperature can be 800° C. to 900° C. For example, the diffusion time can be 60 min, 70 min, 80 min, 90 min, 100 min, 110 min or 120 min. The diffusion temperature can be 810° C., 820° C., 830° C., 840° C., 850° C., 860° C., 870° C., 880° C., 890° C. or 900° C.

[0099] It is understandable that the height of the diffusion temperature and the length of the diffusion time will affect the thickness of the doped glass layer formed during the diffusion process and the compactness of the doped glass layer. Specifically, within a certain range, the longer the diffusion time and the higher the diffusion temperature, the thicker the doped glass layer formed and the higher the compactness, and the corresponding masking effect of the mask layer formed by the doped glass layer is stronger. On the contrary, within a certain range, the shorter the diffusion time and the lower the diffusion temperature, the smaller the thickness of the doped glass layer formed and the lower the compactness, and the corresponding masking effect of the mask layer formed by the doped glass layer is weaker. In this case, when the diffusion time is 60min to 120min and the diffusion temperature is 800℃ to 900℃, it can prevent the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect in the corresponding operation due to the short diffusion time and the low diffusion temperature, ensure that the first doped semiconductor layer and the first passivation layer have good film forming quality, and improve the yield of the back contact battery. At the same time, it can also prevent problems such as reduced manufacturing efficiency and increased manufacturing costs due to long diffusion time and high diffusion temperature, which is beneficial to improving the mass production of back-contact batteries.

[0100] It should be noted that, in addition to diffusing the intrinsic semiconductor material layer to form a doped semiconductor material layer, ion implantation or doping source coating and advancement processes may also be used to form the doped semiconductor material layer. A suitable process for forming the doped semiconductor material layer may be selected according to the actual application scenario requirements.

[0101] In addition, as described above, when the first passivation layer is a tunnel passivation layer and the first doped semiconductor layer is a doped polysilicon layer, in addition to forming the doped polysilicon layer by a low-pressure chemical vapor deposition process and a diffusion process, a plasma enhanced chemical vapor deposition process can also be used to form the doped polysilicon layer. Furthermore, when forming the doped polysilicon layer, the doped polysilicon layer can also be crystallized by in-situ annealing to reduce the stress in the doped polysilicon layer and improve the film formation quality of the doped polysilicon layer.

[0102] Furthermore, as mentioned above, the first passivation layer may be a tunnel passivation layer, and the first doped semiconductor layer may be a doped polysilicon layer. Figure 5 As shown in FIG. 1 , after sequentially forming a passivation material layer 12 covering the backlight surface and a doped semiconductor material layer 14 located on the passivation material layer 12, as shown in FIG. Figure 6 As shown, a laser etching process can be used to pattern the doped semiconductor material layer and the passivation material layer to form a stacked first passivation layer 121 and a first doped semiconductor layer 141. The beneficial effects in this case can be analyzed with reference to the beneficial effects of the first passivation layer 121 being a tunnel passivation layer and the first doped semiconductor layer 141 being a doped polysilicon layer as described above, and will not be repeated here.

[0103] Exemplarily, as described above, the light-facing surface of the silicon substrate may be a polished surface or a velvet surface. Wherein, when the light-facing surface of the silicon substrate is a velvet surface and the mask layer is formed on the first doped semiconductor layer, after forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement and before performing subsequent operations, the method for manufacturing the back contact battery further includes the following steps: Figure 7 As shown, the doped glass layer, the doped semiconductor material layer and the passivation material layer on the light-facing surface and the side surface of the silicon substrate 11 are removed.

[0104] The above-mentioned doped glass layer, doped semiconductor material layer and passivation material layer are removed by roller with liquid or water floating. Figure 8 As shown, under the masking effect of the mask layer 151, the light-facing surface of the silicon substrate 11 is textured so that the light-facing surface is a textured surface. The portion of the backlight surface exposed outside the mask layer 151 will also be

[0105] In addition, the solution used for the texturing process and the processing conditions can be determined according to the actual application scenario, and are not specifically limited here. Fig. 9 As shown, HF solution can be used to remove the mask layer 151. The concentration of the HF solution and the removal time can be set according to actual needs.

[0106] In the case of adopting the above technical solution, as mentioned above, in the texturing process, the mask layer used is a laser etching process to pattern the doped glass layer formed on the doped semiconductor material layer during the diffusion process.

[0107] The mask layer such as silicon nitride is obtained by the process, instead of being formed by additional deposition or other processes after obtaining the first passivation layer and the first doped semiconductor layer which are stacked, thereby further simplifying the manufacturing process of the back contact battery and reducing the back contact battery.

[0108] The manufacturing cost of the pool.

[0109] It should be noted that, as described above, the back contact battery manufactured by the manufacturing method provided in the embodiment of the present invention includes:

[0110] A silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer.

[0111] In Fig.13 As shown, the stacked second passivation layer 17 and the second doped semiconductor layer 18 cover a portion of the stacked first passivation layer 121 and the first doped semiconductor layer 141. In addition, the insulating layer 161 is at least located in the second passivation layer.

[0112] The second passivation layer 17 and the first doped semiconductor layer 141 are used to separate the second passivation layer 17 and the first doped semiconductor layer 141. In the above case, Fig.11 As shown, after forming the stacked first passivation layer 121 and the first doped semiconductor layer 141 and before forming the stacked second passivation layer and the second doped semiconductor layer, the above-mentioned back contact battery manufacturing method also includes the step of forming an insulating layer on the backlight surface.

[0113] 5 For example, Fig.10 As shown, plasma enhanced atomic layer deposition and other processes can be used to form a layer covering the back

[0114] The insulating material layer 16 on the optical surface and the first doped semiconductor layer 141. Then, as Fig.11As shown, the insulating material layer 16 can be patterned by laser etching or other processes to expose the area where the backlight surface contacts the second passivation layer 17 formed subsequently. The insulating material layer 16 covers the first passivation layer 121 and the first doped semiconductor layer 17 stacked on top of each other.

[0115] The insulating layer is formed in the corresponding region of the conductor layer 141. The corresponding region is a region where the stacked first passivation layer 121 and the first zero-doped semiconductor layer 141 are adjacent to the stacked second passivation layer and the second doped semiconductor layer.

[0116] It should be noted that when the insulating material layer is patterned by a laser etching process, after exposing the area where the backlight surface contacts the subsequently formed second passivation layer, the surface of the area damaged by the high-temperature laser etching can be cleaned and repaired by a wet etching process under the masking effect of the remaining part of the insulating material layer. This can reduce the defect recombination rate of carriers at the interface and improve the density of the second passivation layer formed on the area, further improving the passivation effect of the second passivation layer on the area and improving the photoelectric conversion efficiency of the back-contact battery.

[0117] like Fig.13 As shown, along the thickness direction of the silicon substrate 11, a second passivation layer 17 and a second doped semiconductor layer 18 are sequentially stacked on the backlight surface. The stacked second passivation layer 17 and the second doped semiconductor layer 18 cover a portion of the stacked first passivation layer 121 and the first doped semiconductor layer 141, and the second doped semiconductor layer 18 and the first doped semiconductor layer 141 have opposite conductivity types. Specifically, the information such as the material and thickness of the second passivation layer 17 and the second doped semiconductor layer 18 can be referred to the above, and will not be repeated here.

[0118] In actual application, Fig.12 As shown, chemical vapor deposition and other processes can be used to sequentially form a passivation material and a doped semiconductor material covering the backlight surface and the remaining portion of the insulating material layer 16. Fig.13 As shown, laser etching and other processes may be used to pattern the passivation material and the doped semiconductor material, so that the remaining passivation material forms the second passivation layer 17, and the remaining doped semiconductor material forms the second doped semiconductor layer 18. Finally, under the masking effect of the second doped semiconductor layer 18, wet etching and other processes may be used to pattern the remaining portion of the insulating material layer 16 to expose a portion of the first doped semiconductor layer 141. The remaining insulating material layer forms the insulating layer 161.

[0119] In some cases, as described above, when the manufactured back contact battery further includes a first transparent conductive layer, a second transparent conductive layer, a first electrode and a second electrode, Fig.14 As shown, a process such as physical vapor deposition can be used to form a transparent conductive material layer 21 covering the first doped semiconductor layer 141 and the second doped semiconductor layer 18. Fig.15 As shown, laser etching or other processes may be used to form an insulating groove penetrating the transparent conductive layer, the second doped semiconductor layer 18, and the second passivation layer 17, so as to separate the portion of the transparent conductive material layer located on the first doped semiconductor layer 141 from the portion of the transparent conductive material layer located on the second doped semiconductor layer 18. The portion of the transparent conductive material layer located at least on the first doped semiconductor layer 141 forms the first transparent conductive layer 211, and the portion of the transparent conductive material layer located on the second doped semiconductor layer 18 forms the second transparent conductive layer 212. Finally, as shown in FIG. Fig.16 As shown, the first electrode 22 on the first transparent conductive layer 211 and the second electrode 23 on the second transparent conductive layer 212 may be formed by screen printing or other processes.

[0120] The present invention also provides the following specific embodiments to further illustrate the method for manufacturing the back contact battery of the present invention. The specific operation steps are as follows:

[0121] Embodiment 1:

[0122] Step 1: Place the N-type silicon wafer or P-type silicon wafer into a tank polishing and cleaning machine for polishing. The polishing solution is a KOH solution with a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81°C to 87°C. The process time is 290s to 310s. After the polishing process, the surface morphology of the silicon substrate is a square structure with a size of 19μm to 23μm, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40% to 44%.

[0123] Step 2: In a low pressure chemical vapor deposition (LPCVD) furnace, a tunneling oxide material layer covering the backlight surface of the silicon substrate and an intrinsic polysilicon material layer on the tunneling oxide material layer are formed. The thickness of the tunneling oxide material layer is 1.2nm to 1.8nm, and the thickness of the intrinsic polysilicon material layer is 70nm to 170nm. In addition, a passivation material layer and a polysilicon material layer are formed on the side and light-facing surface of the silicon substrate in sequence.

[0124] Step 3: In a phosphorus diffusion furnace, phosphorus is doped on the intrinsic polysilicon material (Poly) layer, so that the intrinsic polysilicon material layer forms an N-type doped polysilicon material layer. The diffusion square resistance of the N-type doped polysilicon material layer is 70Ω / sq to 110Ω / sq. After the diffusion treatment, a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer and the coated polysilicon material layer.

[0125] Step 4: Use laser etching process to pattern the portion of the phosphosilicate glass layer corresponding to the backlight surface, the tunneling oxide material layer and the N-type doped polysilicon material layer, exposing the area corresponding to the backlight surface and the P+ region. The remaining portion of the tunneling oxide material layer forms the first passivation layer, and the remaining portion of the N-type doped polysilicon material layer forms the first doped semiconductor layer. The portion of the phosphosilicate glass layer located on the first doped semiconductor layer forms a mask layer.

[0126] Step 5: In a chain cleaning machine, place the light-facing surface of the silicon substrate facing downward into the HF tank, and use a roller-carrying liquid method or a water-floating method to clean the surface, and remove the phosphorus silicon glass layer on the side and light-facing surface of the silicon substrate at room temperature through a 9.5% to 10.5% HF solution, as well as the plated passivation material layer and the plated polysilicon material layer. The removal time is 55s to 65s. Then, the silicon substrate formed with the first passivation layer, the first doped semiconductor layer and the mask layer is placed in a tank cleaning machine for an alkali texturing process. The texturing solution includes a KOH solution with a concentration of 2.5% to 3.5%, and a texturing additive solution. The temperature of the texturing solution is 80°C to 84°C, and the process time is 570s to 630s. The etching amount is 0.5g to 0.7g, and the reflectivity of the light-facing surface of the silicon substrate after the texturing treatment is 9% to 11%. The width of the tower base on the light-facing side is a small velvet microstructure of 1μm to 3μm. At this time, the P+ area on the backlight side and the light-facing side are velvet-treated at the same time. Finally, the mask layer is removed in the HF tank. The concentration of the HF solution is 9.5% to 10.5%, and it is treated at room temperature for 95s to 105s.

[0127] Step 6: In a plasma enhanced atomic layer deposition (PEALD) device, an aluminum oxide layer and a silicon nitride layer are sequentially deposited on the backlight side and the light-facing side. The thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm.

[0128] Step 7: Use a laser to pattern the aluminum oxide layer and silicon nitride layer on the backlight surface to remove the aluminum oxide layer and silicon nitride layer located on the P+ region. The patterning process is designed corresponding to the screen pattern, and the laser type can be selected from green light nanosecond, ultraviolet picosecond, green light picosecond, and ultraviolet nanosecond.

[0129] Step 8: Perform a polishing process in a tank polishing and cleaning machine. The polishing solution is a KOH solution with a concentration of 5.5% to 6.5%, the temperature of the polishing solution is 81°C to 87°C, and the process time is 170s to 190s to remove the laser damage generated in the seventh step. At the same time, the laser grooved area is polished. Finally, it is treated in a HF solution with a concentration of 1%wt for 25s to 35s.

[0130] Step 9: In a chemical vapor deposition device, an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer covering the backlight surface are sequentially formed, wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the P-type doped amorphous silicon material layer is 10nm to 30nm.

[0131] Step 10: Use a laser to pattern the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer, so that the remaining portion of the intrinsic amorphous silicon material layer forms a second passivation layer, and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond, ultraviolet nanosecond.

[0132] Step 11: In the chain cleaning machine, place the backlight side of the silicon substrate facing down into the HF tank. The concentration of the HF solution is 29% to 31%, and it is treated at room temperature for 175s to 185s. The cleaning mode is roller liquid method or water drift method. After laser etching, the exposed parts of the aluminum oxide layer and silicon nitride layer on the backlight side are removed to expose part of the first doped semiconductor layer. Finally, enter the water tank and drying tank in turn for cleaning and drying. The remaining parts of the aluminum oxide layer and silicon nitride layer on the backlight side form an insulating layer.

[0133] Step 12: In a physical vapor deposition device, a transparent conductive material layer is formed covering the backlight surface, and the thickness of the transparent conductive material layer is 60nm to 100nm.

[0134] Step 13: Use a laser etching process to remove the local transparent conductive material layer, the second doped semiconductor layer and the second passivation layer to achieve insulation between the N+ region and the P+ region.

[0135] Step 14: Form the first electrode and the second electrode by screen printing or other processes. Fig.16 .

[0136] Furthermore, the present invention also provides the following comparative example for manufacturing a back contact battery, and the specific operation steps are as follows:

[0137] Comparative Example 1:

[0138] Step 1: Place the N-type silicon wafer or P-type silicon wafer into a tank polishing and cleaning machine for polishing. The polishing solution is a KOH solution with a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81°C to 87°C. The process time is 290s to 310s. After the polishing process, the surface morphology of the silicon substrate is a square structure with a size of 19μm to 23μm, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40% to 44%.

[0139] Step 2: Use plasma enhanced chemical vapor deposition equipment to form a first silicon nitride layer covering the backlight surface of the silicon substrate. The thickness of the first silicon nitride layer is 190nm to 210nm, and the refractive index is 2.3% to 2.5%. The side and light-facing surface of the silicon substrate will be formed with a coating of silicon nitride layer.

[0140] Step 3: In a tank cleaning machine, place the silicon substrate formed with the first silicon nitride layer and the surrounding silicon nitride layer into the HF tank. The concentration of the HF solution is 0.5% to 1.5%. And treat at room temperature for 25s to 35s to remove the surrounding silicon nitride layer. Then, place the silicon substrate with the first silicon nitride layer formed on the backlight side into the alkaline tank for texturing. The texturing solution includes a KOH solution with a concentration of 2% to 3%, and a texturing additive solution. The temperature of the texturing solution is 80°C to 84°C. The process time is 760s to 800s. Then, enter the container filled with HNO 3 The suede surface is smoothed in the tank of HF mixed solution. The ratio of the mixed solution is HNO 3 :HF=1:100. The total etching amount after the velvet smoothing treatment is 1.7g to 1.9g. The reflectivity of the light-facing side of the silicon substrate is 11% to 13%. The tower base width on the light-facing side is a large velvet microstructure of 3μm to 5μm. Finally, in a HF bath with a concentration of 8%wt, and treated at room temperature for 290s to 310s to remove the first silicon nitride layer remaining on the backlight side.

[0141] Step 4: In a chemical vapor deposition device, a first intrinsic amorphous silicon material layer, a phosphorus-doped N-type doped amorphous silicon material layer, a second silicon nitride layer, and a second intrinsic amorphous silicon material layer are sequentially formed on the backlight surface. The first intrinsic amorphous silicon material layer has a thickness of 5nm to 20nm, the N-type doped amorphous silicon material layer has a thickness of 10nm to 30nm, the second silicon nitride layer has a thickness of 170nm to 230nm, and the second intrinsic amorphous silicon material layer has a thickness of 10nm to 30nm.

[0142] Step 5: Use a laser to pattern the second intrinsic amorphous silicon material layer to expose the P+ region. The laser type can be green light nanosecond, ultraviolet picosecond, green light picosecond, ultraviolet nanosecond;

[0143] Step 6: In a tank cleaning device, the silicon substrate formed with the first intrinsic amorphous silicon material layer, the N-type doped amorphous silicon material layer, the second silicon nitride layer and the second intrinsic amorphous silicon material layer is placed in an HF tank, the concentration of the HF solution is 7.5% to 8.5%, and is treated at room temperature for 190s to 210s to remove the exposed portion of the second silicon nitride layer. Then, it is placed in an alkaline tank for etching to remove the exposed portions of the first intrinsic amorphous silicon material layer and the N-type doped amorphous silicon material layer, so that the remaining portion of the first intrinsic amorphous silicon material layer forms a first passivation layer, and the N-type doped amorphous silicon material layer forms a first doped semiconductor layer. The etching solution includes: KOH with a concentration of 0.4% to 0.6%, and H 2 O 2 solution, the temperature of the etching solution is 25° C., and the process time is 390 s to 410 s.

[0144] Step 7: In a chemical vapor deposition device, a third intrinsic silicon material layer and a boron-doped P-type doped amorphous silicon material layer are sequentially formed on the backlight surface. A fourth intrinsic amorphous silicon material layer and a third silicon nitride layer are sequentially formed on the light-facing surface. The thickness of the third intrinsic amorphous silicon material layer is 5nm to 30nm, the thickness of the P-type doped amorphous silicon material layer is 10nm to 25nm, the thickness of the fourth intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the third silicon nitride layer is 80nm to 105nm.

[0145] Step 8: Use a laser to pattern the third intrinsic silicon material layer and the P-type doped amorphous silicon material layer on the backlight surface, so that the remaining portion of the third intrinsic silicon material layer forms a second passivation layer, and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond, ultraviolet nanosecond.

[0146] Step 9: Use HF solution to remove the exposed portion of the second silicon nitride layer to expose a portion of the first doped semiconductor layer and to form an insulating layer on the portion of the second silicon nitride layer located on the first doped semiconductor layer. The concentration of the HF solution is 7% to 9%, and the treatment is performed at room temperature for 380s to 420s.

[0147] Step 10: In a chemical vapor deposition device, a transparent conductive material layer is formed covering the backlight surface, and the thickness of the transparent conductive material layer is 60nm to 100nm.

[0148] Step 11: Use a laser to etch the lateral junction between the first doped semiconductor layer and the second doped semiconductor layer to remove the local transparent conductive material layer, the local second passivation layer and the local second doped semiconductor layer, so that the portion of the transparent conductive material layer located on the first doped semiconductor layer forms a first transparent conductive layer, and the portion of the transparent conductive material layer located on the second doped semiconductor layer forms a second transparent conductive layer.

[0149] Step 12: Form the first electrode and the second electrode by screen printing or other processes. The final structure is shown in Figure 1 .

[0150] Comparative Example 2:

[0151] Step 1: Place the N-type silicon wafer or P-type silicon wafer into a tank polishing and cleaning machine for polishing. The polishing solution is a KOH solution with a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81°C to 87°C. The process time is 290s to 310s. After the polishing process, the surface morphology of the silicon substrate is a square structure with a size of 19μm to 23μm, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40% to 44%.

[0152] Step 2: In a low-pressure chemical vapor deposition furnace, a tunneling oxide material layer covering the backlight surface of the silicon substrate and an intrinsic polysilicon material layer located on the tunneling oxide material layer are formed. The thickness of the tunneling oxide material layer is 1.2nm to 1.8nm, and the thickness of the intrinsic polysilicon material layer is 70nm to 170nm. In addition, the side surface and the light-facing surface of the silicon substrate are sequentially formed with a coating passivation material layer and a coating polysilicon material layer.

[0153] Step 3: In a phosphorus diffusion furnace, phosphorus is doped into the intrinsic polysilicon material layer, so that the intrinsic polysilicon material layer forms an N-type doped polysilicon material layer. The diffusion square resistance of the N-type doped polysilicon material layer is 70Ω / sq to 110Ω / sq. After the diffusion treatment, a phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer and the coated polysilicon material layer.

[0154] Step 4: Using a plasma chemical vapor deposition setup, a silicon nitride layer is formed covering the backlight surface. The thickness of the silicon nitride layer is 40nm to 60nm, and its refractive index is 2.3% to 2.5%.

[0155] Step 5: Use a laser to pattern the silicon nitride layer on the backlight surface to expose the area of ​​the backlight surface corresponding to the P+ region. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond, and ultraviolet nanosecond.

[0156] Step 6: In a tank cleaning machine, the formed structure is placed in an HF tank to remove the portion of the phosphosilicate glass layer exposed outside the silicon nitride on the backlight side. The concentration of the HF solution is 0.5% to 1.5%, and it is treated at room temperature for 25s to 35s. Next, it enters the alkaline tank for texturing treatment to texturize the exposed areas on the light-facing side and the backlight side. The texturing solution includes KOH with a concentration of 2.5% to 3.5%, and a texturing additive solution. The temperature of the texturing solution is 80°C to 84°C, and the process time is 570s to 630s. The texturing etching amount is 0.5g to 0.7g. After the texturing treatment, the reflectivity of the light-facing side is 9% to 11%, and the base width of the light-facing side is a small velvet microstructure of 1μm to 3μm.

[0157] Step 7: In a plasma enhanced atomic layer deposition device, an aluminum oxide layer and a silicon nitride layer are sequentially formed on the light-facing surface. The thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm. Then, the exposed area of ​​the backlight surface is polished by treating it in a 1%wt HF solution for 30s.

[0158] Step 8: In a chemical vapor deposition device, an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer covering the backlight surface are sequentially formed, wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 30nm, and the thickness of the P-type doped amorphous silicon layer is 10nm to 25nm.

[0159] Step 9: Use a laser to pattern the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer so that the remaining portion of the intrinsic amorphous silicon material layer forms a second passivation layer, and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond, ultraviolet nanosecond.

[0160] Step 10: Use HF solution to remove the exposed part of the silicon nitride layer to expose a part of the first doped semiconductor layer, wherein the concentration of the HF solution is 7% to 9% and the treatment is carried out at room temperature for 380s to 420s.

[0161] Step 11: In a physical vapor deposition device, a transparent conductive material layer is formed covering the backlight surface, and the thickness of the transparent conductive material layer is 60nm to 100nm.

[0162] Step 12: Use a laser etching process to remove the local transparent conductive material layer, the second doped semiconductor layer and the second passivation layer to achieve insulation between the N+ region and the P+ region.

[0163] Step 13: Form the first electrode and the second electrode by screen printing or other processes. The final structure is shown in Figure 2.

[0164] Table 1 tests the back-contact cells manufactured by the above-mentioned Example 1, Comparative Example 1 and Comparative Example 2, and compares the parameters of the above-mentioned three back-contact cells.

[0165] Table 1: Comparison of parameters of back contact cells manufactured in Example 1, Comparative Example 1 and Comparative Example 2

[0166]

[0167] like Fig.16 As shown, in the back contact cell manufactured in Example 1, the insulating layer 161 is at least located between the second passivation layer 17 and the first doped semiconductor layer 141. In addition, along the direction away from the silicon substrate 11, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer. Figure 1 As shown, in the back contact cell manufactured in Comparative Example 1, an insulating layer 161 of silicon nitride material is formed only at the longitudinal boundary between the first doped semiconductor layer 141 and the second passivation layer 17. Figure 2 As shown, in the back contact battery manufactured in comparative example 2, a doped glass layer and an insulating layer 161 located on the doped glass layer are formed only at the longitudinal junction between the first doped semiconductor layer 141 and the second passivation layer 17. Based on this, it can be seen from Table 1 that the parallel resistance and short-circuit current of the back contact battery manufactured in Example 1 are higher than the parallel resistance and short-circuit current corresponding to the back contact batteries manufactured in comparative examples 1 and 2, respectively, and the open circuit voltage of the back contact battery manufactured in Example 1 is lower than the open circuit voltage corresponding to the back contact batteries manufactured in comparative examples 1 and 2, thereby helping to reduce the leakage risk of the back contact battery, and thus making the conversion efficiency of the back contact battery manufactured in Example 1 higher than the conversion efficiency corresponding to the back contact batteries manufactured in comparative examples 1 and 2.

[0168] In addition, if Fig.16 As shown, in the back contact cell manufactured in Example 1, an aluminum oxide layer and a silicon nitride layer located on the aluminum oxide layer are sequentially formed on the light-facing surface in the direction away from the silicon substrate. Figure 1As shown, in the back contact cell manufactured in Comparative Example 1, an amorphous silicon passivation layer and a silicon nitride layer located on the amorphous silicon passivation layer are sequentially formed on the light-facing surface along the direction away from the silicon substrate. Based on this, because the amorphous silicon has light absorption characteristics, the amorphous silicon passivation layer located on the light-facing surface will produce parasitic absorption, resulting in a reduction in the light incident on the silicon substrate. In addition, as mentioned above, the amorphous silicon passivation layer is difficult to match the light-facing surface with a small velvet structure, while the aluminum oxide layer can match the light-facing surface with a small velvet structure. In this case, it can be seen from Table 1 that the light-facing surface tower base width and light-facing surface reflectivity of the back contact cell manufactured in Example 1 are respectively smaller than the light-facing surface tower base width and light-facing surface reflectivity corresponding to the back contact cell manufactured in Comparative Example 1, thereby facilitating the enhancement of the light trapping effect of the light-facing surface, allowing more light to be incident on the silicon substrate, and ultimately making the conversion efficiency of the back contact cell manufactured in Example 1 greater than the conversion efficiency corresponding to the back contact cell manufactured in Comparative Example 1.

[0169] Furthermore, if Fig.16 As shown, in the back contact cell manufactured in Example 1, the first passivation layer 121 and the first doped semiconductor layer 141 form a tunnel passivation contact structure. The second passivation layer 17 and the second doped semiconductor layer 18 form a heterogeneous contact structure. Figure 1 As shown, in the back contact battery manufactured in Comparative Example 1, the first passivation layer 121 and the first doped semiconductor layer 141 constitute a heterogeneous contact structure. At the same time, the second passivation layer 17 and the second doped semiconductor layer 18 also constitute a heterogeneous contact structure. Based on this, as mentioned above, at high temperatures, compared with the heterogeneous contact structure, the chemical properties of the tunneling passivation contact structure are more stable, so after the laser film opening process, the passivation effect on the tunneling passivation contact structure is relatively small. In addition, it can be seen from Table 1 that the N+ region laser process window of the back contact battery manufactured in Example 1 is larger than the N+ region laser process window corresponding to the back contact battery manufactured in Comparative Example 1.

[0170] In summary, it can be seen from Table 1 that the filling factor of the back-contact battery manufactured in Example 1 is higher than the corresponding filling factor of the back-contact battery manufactured by Comparative Example 1 and Comparative Example 2, that is, the quality of the back-contact battery manufactured in Example 1 is better than the back-contact batteries manufactured in Comparative Example 1 and Comparative Example 2.

[0171] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0172] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: Silicon substrate, A first passivation layer and a first doped semiconductor layer are sequentially stacked on the backlight surface of the silicon substrate along the thickness direction of the silicon substrate; A second passivation layer and a second doped semiconductor layer are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate; wherein the stacked second passivation layer and the second doped semiconductor layer cover a partial area of ​​the stacked first passivation layer and the first doped semiconductor layer, and the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types; An insulating layer disposed on the backlight surface; the insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer from the first doped semiconductor layer; the insulating layer extends from the sidewalls of the stacked first passivation layer and the first doped semiconductor layer to the silicon substrate, contacts the silicon substrate, and extends in a direction away from the first doped semiconductor layer; the stacked second passivation layer and the second doped semiconductor layer at least cover the portion of the insulating layer that contacts the silicon substrate; A passivation anti-reflection layer is arranged on the light-facing surface of the silicon substrate; the material of the insulating layer is the same as that of the passivation anti-reflection layer; the insulating layer includes at least two layers, and the material of the insulating layer has passivation and anti-reflection functions.

2. The back contact cell according to claim 1, characterized in that: The first passivation layer is a tunnel passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.

3. The back contact battery according to claim 2, characterized in that: The second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer.

4. The back contact cell according to claim 1, characterized in that: The back contact cell further comprises: an aluminum oxide layer and a silicon nitride layer stacked in sequence on the light-facing surface of the silicon substrate in a direction away from the silicon substrate; or, The back contact cell further comprises: a silicon oxide layer and a silicon nitride layer which are sequentially stacked on the light-facing surface of the silicon substrate in a direction away from the silicon substrate.

5. The back contact battery according to any one of claims 1 to 4, characterized in that: Along the direction away from the silicon substrate, the insulating layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence; or, Along a direction away from the silicon substrate, the insulating layer includes a silicon oxide layer and a silicon nitride layer stacked in sequence.

6. The back contact battery according to any one of claims 1 to 4, characterized in that: The thickness of the insulating layer is 75 nm to 125 nm.

7. The back contact battery according to any one of claims 1 to 4, characterized in that: The light-facing surface of the silicon substrate is a velvet surface; the tower base width of the velvet surface is 1 μm to 3 μm.

8. A photovoltaic module, characterized in that: Comprising a back contact battery as claimed in any one of claims 1 to 7.

9. A method for manufacturing a back contact battery, characterized in that: include: Providing a silicon substrate; Forming a first passivation layer and a first doped semiconductor layer sequentially stacked on a backlight surface of the silicon substrate along a thickness direction of the silicon substrate; forming an insulating layer on the backlight surface; and forming a passivation anti-reflection layer on the light-facing surface of the silicon substrate; The material of the insulating layer is the same as that of the passivation anti-reflection layer; the insulating layer comprises at least two layers, and the material of the insulating layer has passivation and anti-reflection functions; A second passivation layer and a second doped semiconductor layer are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate; wherein the stacked second passivation layer and the second doped semiconductor layer cover a portion of the stacked first passivation layer and the first doped semiconductor layer, and the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types; The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer and the first doped semiconductor layer; the insulating layer extends from the side walls of the stacked first passivation layer and the first doped semiconductor layer to the silicon substrate, and is in contact with the silicon substrate, and extends in a direction away from the first doped semiconductor layer; the stacked second passivation layer and the second doped semiconductor layer at least cover the portion of the insulating layer that is in contact with the silicon substrate.

10. The method for manufacturing a back contact battery according to claim 9, characterized in that: The first passivation layer and the first doped semiconductor layer are formed in a stacked manner, comprising: sequentially forming a passivation material layer covering the backlight surface and an intrinsic semiconductor material layer located on the passivation material layer; Performing diffusion treatment on the intrinsic semiconductor material layer so that the intrinsic semiconductor material layer forms a doped semiconductor material layer, and forming a doped glass layer on the doped semiconductor material layer; Using a laser etching process, a portion of the doped glass layer located on the doped semiconductor material layer is removed; wherein the remaining portion of the doped glass layer forms a mask layer; Under the masking effect of the mask layer, the portion of the doped semiconductor material layer exposed outside the mask layer and the portion of the passivation material layer exposed outside the mask layer are removed in sequence to form the first passivation layer and the first doped semiconductor layer which are stacked.

11. The method for manufacturing a back contact battery according to claim 10, characterized in that: The thickness of the doped glass layer is 40 nm to 60 nm; and / or, The diffusion time of the diffusion treatment is 60 minutes to 120 minutes, and the diffusion temperature is 800° C. to 900° C.

12. The method for manufacturing a back contact battery according to claim 10, characterized in that: After forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement and before forming the insulating layer on the backlight surface, the method for manufacturing the back contact battery further includes: Removing the wrap-around doped glass layer, the wrap-around doped semiconductor material layer and the wrap-around passivation material layer located on the light-facing surface and the side surface of the silicon substrate; Under the masking action of the mask layer, a texturing process is performed on the light-facing surface of the silicon substrate so that the light-facing surface is a texturing surface; The mask layer is removed.

13. The method for manufacturing a back contact battery according to any one of claims 9 to 12, characterized in that: The first passivation layer and the first doped semiconductor layer are formed in a stacked manner, comprising: sequentially forming a passivation material layer covering the backlight surface and a doped semiconductor material layer located on the passivation material layer; The doped semiconductor material layer and the passivation material layer are patterned by laser etching process to form the first passivation layer and the first doped semiconductor layer which are stacked; wherein the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.

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