Preparation method of Josephson junction and superconducting electronic device

Abstract

The present invention provides a method for preparing a Josephson junction and a superconducting electronic device. By preparing a first superconducting layer and a second superconducting layer with different thicknesses, after predefining the Josephson junction, the second superconducting layer can be overetched for the first time to form a first superconducting strip line, and the insulating protective layer can be directly grown and stripped. Then, a third superconducting layer is prepared, and the second superconducting strip line is etched. At the same time, the second superconducting layer, i.e., the first superconducting strip line, is overetched for the second time. By using a double overetching process, a method for preparing a Josephson junction of a submicron or even deep submicron scale is provided. The method can solve the precision limitations of existing process equipment, thereby reducing the cost of process equipment, and is suitable for the reliable preparation of high-performance practical superconducting quantum interference devices and other superconducting electronic devices based on Josephson junctions.

Description

Technical Field

[0001] The present invention belongs to the technical field of superconductivity and relates to a method for preparing a Josephson junction and a superconducting electronic device. Background Art

[0002] The common Josephson junction is a superconductor-insulator-superconductor (SIS) "sandwich" structure, and is also a quantum device with the Josephson tunneling effect. For example, a superconducting magnetic sensor called a superconducting quantum interference device (SQUID) can be formed by combining a Josephson junction and a superconducting ring. It has the characteristics of high sensitivity and low noise, and the magnetic field noise can be as low as <1fT / Hz. 1 / 2 (fT=10 -15 T) is the most sensitive practical magnetic sensor currently available and is widely used in biomagnetic detection, extremely low-field nuclear magnetic resonance, geophysical exploration and other fields.

[0003] The fabrication of Josephson junctions and SQUIDs today benefits from the rapid advancement of semiconductor technology, leveraging mature planar micro-nanofabrication techniques such as thin-film lithography and etching for chip development. As modern semiconductor transistors continue to shrink in size, the demands placed on equipment such as lithography machines are becoming increasingly stringent, leading to a surge in equipment costs.

[0004] For the preparation of Josephson junctions and SQUIDs, electron beams, focused ion beams, stepper lithography, contact ultraviolet lithography and other technical means can be used. However, when it comes to wafer-level batch chip preparation, steppers are the first choice in terms of process accuracy and efficiency. Currently, steppers with process accuracy at the level of 100 nanometers cost approximately tens of millions of RMB, which has become a heavy cost for chip iteration and process upgrades. In the future, when moving to deep submicron Josephson junction technology, the increase in equipment costs has become an important issue that cannot be ignored. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for preparing a Josephson junction and a superconducting electronic device, so as to solve the problem of the limitation of the lithography accuracy of semiconductor devices encountered in the prior art when preparing Josephson junctions.

[0006] To achieve the above-mentioned and other related objects, the present invention provides a method for preparing a Josephson junction, comprising the following steps:

[0007] providing a substrate;

[0008] forming a first superconducting layer, an insulating barrier layer, and a second superconducting layer stacked from bottom to top on the substrate, wherein the first superconducting layer has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness;

[0009] etching the second superconducting layer and the insulating barrier layer to expose a portion of the first superconducting layer;

[0010] Etching the exposed first superconducting layer to form a lower extraction electrode, and etching the second superconducting layer to form a first superconducting strip line on the insulating barrier layer;

[0011] forming an insulating protective layer, wherein the insulating protective layer covers the insulating barrier layer and exposes a surface of the first superconducting strip line and a surface of the lower extraction electrode;

[0012] forming a third superconducting layer on the first superconducting strip line;

[0013] The third superconducting layer is etched to form a second superconducting strip line and an upper extraction electrode, and the first superconducting strip line is etched to expose the insulating barrier layer. The second superconducting strip line and the first superconducting strip line intersect to form a Josephson junction.

[0014] Optionally, a ratio of the thickness of the second superconducting layer to the thickness of the first superconducting layer is in a range of 1:4 to 1:2.

[0015] Optionally, the thickness of the first superconducting layer is 100 nm to 200 nm, and the thickness of the second superconducting layer is 50 nm to 100 nm.

[0016] Optionally, the second superconducting strip line is formed perpendicular to the first superconducting strip line.

[0017] Optionally, the size of the formed Josephson junction ranges from 300 nm to 600 nm.

[0018] Optionally, the insulating protection layer includes one or a combination of a silicon oxide layer, a silicon dioxide layer and a silicon nitride layer.

[0019] Optionally, the substrate includes one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate and a silicon carbide substrate; and the substrate includes a wafer-level substrate.

[0020] Optionally, the first superconducting layer includes at least one of a niobium nitride layer and a niobium layer; the second superconducting layer includes at least one of a niobium nitride layer and a niobium layer; the third superconducting layer includes at least one of a niobium nitride layer and a niobium layer; and the insulating barrier layer includes at least one of an aluminum layer, an aluminum oxide layer and an aluminum nitride layer.

[0021] The present invention also provides a method for preparing a superconducting electronic device, which comprises preparing a Josephson junction by adopting any of the above-mentioned methods for preparing a Josephson junction.

[0022] Optionally, the superconducting electronic device is a superconducting quantum interference device, and after forming the insulating protective layer, it also includes a step of forming a passivation layer covering the insulating protective layer, and the preparation step of the passivation layer is after forming the resistance layer of the superconducting quantum interference device.

[0023] As described above, the method for preparing a Josephson junction and a superconducting electronic device of the present invention prepares a first superconducting layer and a second superconducting layer with different thicknesses. After predefining the Josephson junction, the second superconducting layer can be overetched for the first time to form a first superconducting strip line, and the insulating protective layer can be directly grown and stripped. Then, a third superconducting layer is prepared, and the second superconducting strip line is etched. At the same time, the second superconducting layer, i.e., the first superconducting strip line, is overetched for the second time. By using a double overetching process, a method for preparing a Josephson junction at a submicron or even deep submicron scale is provided. This method can solve the precision limitations of existing process equipment, thereby reducing the cost of process equipment, and is suitable for the reliable preparation of high-performance practical superconducting quantum interference devices and other superconducting electronic devices based on Josephson junctions. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a schematic diagram of the process flow for preparing a Josephson junction in an embodiment of the present invention.

[0025] Figure 2 It is a schematic diagram of the structure after forming the second superconducting layer in an embodiment of the present invention.

[0026] Figure 3 It is a schematic diagram of the structure after etching the second superconducting layer and the insulating barrier layer to form a predefined position of the Josephson junction in an embodiment of the present invention.

[0027] Figure 4 It is a schematic diagram of the structure after the lower extraction electrode and the first superconducting strip line are formed in an embodiment of the present invention.

[0028] Figure 5 It is a schematic diagram of the structure after forming the insulating protection layer in an embodiment of the present invention.

[0029] Figure 6 It is a schematic diagram of the structure after the upper extraction electrode and the second superconducting strip line are formed in an embodiment of the present invention.

[0030] Figure 7 Display as Figure 6 Scanning electron micrograph of area A in center.

[0031] Component number description

[0032] 100 substrate

[0033] 200 First superconducting layer

[0034] 201 Lower layer lead electrode

[0035] 300 Insulation barrier layer

[0036] 400 Second superconducting layer

[0037] 401 First Superconducting Strip Line

[0038] 500 Insulation Protection Layer

[0039] 601 Upper lead electrode

[0040] 602 Second superconducting strip line

[0041] 700 Josephson knot

[0042] Area A

[0043] Steps S1 to S7 DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0046] For ease of description, spatial relational terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0047] Expressions such as "between..." may be used herein to indicate inclusiveness of both endpoints, and expressions such as "plurality" may be used to indicate two or more, unless otherwise specifically limited. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] like Figure 1 As shown, this embodiment provides a method for preparing a Josephson junction, comprising the following steps:

[0050] S1: providing a substrate;

[0051] S2: forming a first superconducting layer, an insulating barrier layer, and a second superconducting layer stacked from bottom to top on the substrate, wherein the first superconducting layer has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness;

[0052] S3: etching the second superconducting layer and the insulating barrier layer to expose a portion of the first superconducting layer;

[0053] S4: etching the exposed first superconducting layer to form a lower extraction electrode, and etching the second superconducting layer to form a first superconducting strip line on the insulating barrier layer;

[0054] S5: forming an insulating protective layer, wherein the insulating protective layer covers the insulating barrier layer and exposes the surface of the first superconducting strip line and the surface of the lower extraction electrode;

[0055] S6: forming a third superconducting layer on the first superconducting strip line;

[0056] S7: etching the third superconducting layer to form a second superconducting strip line and an upper extraction electrode, and etching the first superconducting strip line to expose the insulating barrier layer, and the second superconducting strip line and the first superconducting strip line intersect to form a Josephson junction.

[0057] The following combination Figures 2 to 7 The preparation of the Josephson junction is further introduced, including:

[0058] First, if Figure 2 , perform steps S1 and S2, provide a substrate 100 and form a first superconducting layer 200, an insulating barrier layer 300 and a second superconducting layer 400 stacked from bottom to top on the substrate 100, wherein the first superconducting layer 200 has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness.

[0059] As an example, the substrate 100 may include one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate, and the specific substrate can be selected as needed. The substrate 100 may be a wafer-level substrate, such as a 6-inch, 8-inch, or 12-inch wafer-level substrate, or may be an irregularly shaped or regular small sample substrate. The morphology and size of the substrate 100 are not excessively limited herein.

[0060] As an example, the first superconducting layer 200 may include at least one of a niobium nitride layer and a niobium layer; the second superconducting layer 400 may include at least one of a niobium nitride layer and a niobium layer; and the insulating barrier layer 300 may include at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer.

[0061] Specifically, the first superconducting layer 200, the insulating barrier layer 300, and the second superconducting layer 400 can be grown separately using magnetron sputtering technology. In this embodiment, the materials of the first superconducting layer 200 and the second superconducting layer 400 are both made of the relatively common niobium (Nb), and the material of the insulating barrier layer 300 is made of aluminum oxide formed by oxidation of aluminum in oxygen. The oxidation time and oxidation pressure determine the thickness of the aluminum oxide and also determine the critical current density of the subsequently prepared Josephson junction. However, the selection of materials for the first superconducting layer 200, the insulating barrier layer 300, and the second superconducting layer 400 is not limited to this.

[0062] In order to meet the needs of subsequent over-etching process, in the three-layer film here, the first superconducting layer 200 and the second superconducting layer 400 have different film thicknesses, and the second superconducting layer 400 located on the upper layer is thinner than the first superconducting layer 200 located on the lower layer.

[0063] As an example, the ratio of the thickness of the second superconducting layer 400 to the thickness of the first superconducting layer 200 may be in a range of 1:4 to 1:2.

[0064] Specifically, in order to meet the needs of subsequent over-etching processes, the ratio of the thickness of the second superconducting layer 400 to the thickness of the first superconducting layer 200 can range from 1:4, 1:3, 1:2, etc. In this embodiment, the ratio of the thickness of the second superconducting layer 400 to the thickness of the first superconducting layer 200 is preferably 1:2, but is not limited to this.

[0065] The thickness of the first superconducting layer 200 may be 100 nm to 200 nm, such as 100 nm, 150 nm, 200 nm, etc., and the thickness of the second superconducting layer 400 may be 50 nm to 100 nm, such as 50 nm, 80 nm, 100 nm, etc.

[0066] Then, if Figure 3 , executing step S3 , etching the second superconducting layer 400 and the insulating barrier layer 300 to expose a portion of the first superconducting layer 200 .

[0067] Specifically, by using photolithography and etching technology to remove part of the second superconducting layer 400 and the insulating barrier layer 300, the position of the Josephson junction to be prepared subsequently can be predefined. Here, the method for etching the second superconducting layer 400 can be reactive ion etching, and the method for etching the insulating barrier layer 300 can be ion beam etching technology, but it is not limited to this. This step is the preliminary preparation work for the preparation of the Josephson junction.

[0068] Then, if Figure 4 , executing step S4 , etching the exposed first superconducting layer 200 to form a lower extraction electrode 201 , and at the same time etching the second superconducting layer 400 to form a first superconducting strip line 401 on the insulating barrier layer 300 .

[0069] Specifically, the predefined position formed in step S3 is etched by photolithography and etching technology to form the first superconducting strip line 401 by etching the second superconducting layer 400, and the outside of the predefined position will be etched away except for the necessary electrodes, so as to form the lower-layer lead-out electrode 201 by etching the first superconducting layer 200.

[0070] During the etching process, the second superconducting layer 400 located at the upper layer at the predefined location and the first superconducting layer 200 located below the predefined location are etched simultaneously. However, due to the different thicknesses of the first superconducting layer 200 and the second superconducting layer 400, the thinner second superconducting layer 400 located at the upper layer is subjected to the first overetching. As a result, the actual etched size of the formed first superconducting strip line 401 is smaller than the designed size. During the overetching process, the insulating barrier layer 300 at the predefined location can be used as an etch stop layer to prevent the overetching from affecting the first superconducting layer 200 at the predefined location.

[0071] Then, if Figure 5 , performing step S5 to form an insulating protection layer 500 , wherein the insulating protection layer 500 covers the insulating barrier layer 300 and exposes the surface of the first superconducting strip line 401 and the surface of the lower extraction electrode 201 .

[0072] Specifically, after executing step S4, the photoresist mask (not shown) located on the surface of the lower lead-out electrode 201 and the first superconducting strip line 401 used in the etching process may not be removed first, and the growth of the insulating protective layer 500 may be performed immediately afterwards. After the growth of the insulating protective layer 500 is completed, the photoresist mask may be stripped to re-expose the surface of the first superconducting strip line 401 and the surface of the lower lead-out electrode 201.

[0073] As an example, the insulating protection layer 500 may include one or a combination of a silicon oxide layer, a silicon dioxide layer, and a silicon nitride layer.

[0074] Specifically, the insulating protective layer 500 can play a good protective role. According to needs, the insulating protective layer 500 can be a single layer or a stack of different materials, and there is no excessive restriction here.

[0075] Then, if Figure 6 , perform steps S6 and S7 to form a third superconducting layer (not shown) on the first superconducting strip line 401, and etch the third superconducting layer to form a second superconducting strip line 602 and an upper extraction electrode 601. At the same time, the first superconducting strip line 401 is etched to expose the insulating barrier layer 300, and the second superconducting strip line 602 and the first superconducting strip line 401 intersect to form a Josephson junction 700.

[0076] Specifically, while etching the second superconducting strip line 602, in addition to retaining the overlapping portion with the first superconducting strip line 401, the other portions of the first superconducting strip line 401 need to be removed to expose the insulating barrier layer 300. This is also the second over-etching of the second superconducting layer 400 located on the upper layer.

[0077] As an example, the third superconducting layer may include at least one of a niobium nitride layer and a niobium layer.

[0078] Specifically, the preparation of the third superconducting layer, the selection of the material, etc. can be found in the above description of the first superconducting layer 200 and the second superconducting layer 400, which will not be elaborated here.

[0079] As an example, the second superconducting strip line 602 is formed perpendicular to the first superconducting strip line 401 .

[0080] Specifically, in this embodiment, in order to further reduce the size of the formed Josephson junction 700, the second superconducting strip line 602 is preferably perpendicular to the first superconducting strip line 401, but the angle between the second superconducting strip line 602 and the first superconducting strip line 401 is not limited thereto.

[0081] As an example, the size of the formed Josephson junction 700 ranges from 300 nm to 600 nm.

[0082] Specifically, the size of the formed Josephson junction 700 can be 300nm, 400nm, 500nm, 600nm, etc. In the embodiment, the cross strip line method is used to further reduce the size of the Josephson junction by performing two over-etching operations. Figure 4 and Figure 6 The first over-etching of the second superconducting layer 400 can be understood as over-etching in the horizontal direction, while the second over-etching of the second superconducting layer 400 can be understood as over-etching in the vertical direction. Therefore, the second superconducting layer 400 can be over-etched from two perpendicular directions to reduce the size of the formed Josephson junction 700. This method can overcome the lithography accuracy limitation of the equipment itself and realize the preparation of a smaller-sized Josephson junction.

[0083] like Figure 7 The scanning electron microscope image shows that the junction area at the intersection of the two stripes is approximately 575nm × 384nm. This dimension is smaller than the lithographic precision of the equipment used (700nm), thus achieving a smaller junction area and even breaking the precision limit of the lithographic equipment. Therefore, this method can reduce process equipment costs and provide a feasible technical solution for the preparation of submicron Josephson junctions and even deep submicron Josephson junctions.

[0084] This embodiment also provides a method for preparing a superconducting electronic device. The method for preparing a superconducting electronic device includes preparing a Josephson junction using the above-mentioned method for preparing a Josephson junction, thereby preparing a superconducting electronic device based on the Josephson junction.

[0085] Specifically, the preparation of the Josephson junction can be found in the above introduction and will not be described in detail here.

[0086] As an example, the superconducting electronic device can be a superconducting quantum interference device (SQUID). Of course, the superconducting electronic device can also be other superconducting electronic devices based on Josephson junctions. When the superconducting electronic device is a SQUID, it is preferred that after forming the insulating protective layer 500, a passivation layer (not shown) covering the insulating protective layer 500 is formed. The passivation layer preparation step can be performed after forming the resistance layer (not shown) of the superconducting quantum interference device. Thus, based on the passivation layer, the insulation protection of the edge area of ​​the predefined position can be further improved. At the same time, in the preparation process of the SQUID, the passivation layer is placed after the resistance layer, which can also play the role of electrical isolation between the resistance and the subsequent metal layer. The type of the passivation layer may include one or a combination of a silicon oxide layer, a silicon dioxide layer, and a silicon nitride layer, and is not overly limited here. The specific type of the superconducting electronic device and the preparation of other related components are not overly limited here, and can be selected and prepared according to existing technologies.

[0087] In summary, the method for preparing a Josephson junction and a superconducting electronic device of the present invention prepares a first superconducting layer and a second superconducting layer with different thicknesses. After predefining the Josephson junction, the second superconducting layer can be overetched for the first time to form a first superconducting strip line, and the insulating protective layer can be directly grown and peeled off. Then, the third superconducting layer is prepared, and the second superconducting strip line is etched. At the same time, the second superconducting layer, i.e., the first superconducting strip line, is overetched for the second time. Through a double overetching process, a method for preparing a Josephson junction at a submicron or even deep submicron scale is provided, which can solve the precision limitations of existing process equipment, thereby reducing the cost of process equipment, and is suitable for the reliable preparation of high-performance practical superconducting quantum interference devices and other superconducting electronic devices based on Josephson junctions.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a Josephson junction, characterized in that: The following steps are involved: providing a substrate; forming a first superconducting layer, an insulating barrier layer, and a second superconducting layer stacked from bottom to top on the substrate, wherein the first superconducting layer has a first thickness, the second superconducting layer has a second thickness, and the first thickness is greater than the second thickness; etching the second superconducting layer and the insulating barrier layer to expose a portion of the first superconducting layer; Etching the exposed first superconducting layer to form a lower extraction electrode, and etching the second superconducting layer to form a first superconducting strip line on the insulating barrier layer; forming an insulating protective layer, wherein the insulating protective layer covers the insulating barrier layer and exposes a surface of the first superconducting strip line and a surface of the lower extraction electrode; forming a third superconducting layer on the first superconducting strip line; The third superconducting layer is etched to form a second superconducting strip line and an upper extraction electrode, and the first superconducting strip line is etched to expose the insulating barrier layer, and the second superconducting strip line crosses the first superconducting strip line.

2. The method for preparing a Josephson junction according to claim 1, wherein: The ratio of the thickness of the second superconducting layer to the thickness of the first superconducting layer is in a range of 1:4 to 1:

2.

3. The method for preparing a Josephson junction according to claim 1, wherein: The thickness of the first superconducting layer is 100 nm to 200 nm, and the thickness of the second superconducting layer is 50 nm to 100 nm.

4. The method for preparing a Josephson junction according to claim 1, wherein: The second superconducting strip line is formed perpendicular to the first superconducting strip line.

5. The method for preparing a Josephson junction according to claim 1, wherein: The size of the formed Josephson junction ranges from 300 nm to 600 nm.

6. The method for preparing a Josephson junction according to claim 1, wherein: The insulating protection layer includes one or a combination of a silicon oxide layer, a silicon dioxide layer and a silicon nitride layer.

7. The method for preparing a Josephson junction according to claim 1, wherein: The substrate includes one of a silicon substrate, a magnesium oxide substrate, a sapphire substrate and a silicon carbide substrate; and the substrate includes a wafer-level substrate.

8. The method for preparing a Josephson junction according to claim 1, wherein: The first superconducting layer includes at least one of a niobium nitride layer and a niobium layer; the second superconducting layer includes at least one of a niobium nitride layer and a niobium layer; the third superconducting layer includes at least one of a niobium nitride layer and a niobium layer; and the insulating barrier layer includes at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer.

9. A method for preparing a superconducting electronic device, characterized in that: The method for preparing the superconducting electronic device comprises preparing a Josephson junction by using the method for preparing a Josephson junction according to any one of claims 1 to 8.

10. The method for preparing a superconducting electronic device according to claim 9, wherein: The superconducting electronic device is a superconducting quantum interference device, and after forming the insulating protection layer, it also includes the step of forming a passivation layer covering the insulating protection layer, and the preparation step of the passivation layer is after forming the resistance layer of the superconducting quantum interference device.

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