An insulated gate bipolar transistor and a method of manufacturing the same

Abstract

The application provides an insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a substrate, a trench gate structure, an emission region, an insulation buried layer, a contact region, an interlayer dielectric layer, an emitter conductive layer and a conductive connection part. The substrate is provided with a collector region, a field stop layer, a drift layer and a base region which are sequentially stacked. The insulation buried layer is located in the base region and below the emission region, and is spaced apart from the trench gate structure by a preset distance. In one aspect, the application increases the insulation buried layer below the emission region to block the hole current from flowing through the emission region and the base region, so that it is very difficult for the PN junction to be positively biased, and the latch-up effect caused by the positively biased PN junction is prevented. In another aspect, the contact hole penetrating through the insulation buried layer connects the emitter conductive layer to the P-type base region to form a groove-shaped emitter. The deep groove-shaped emitter can shorten the hole flow path, accelerate the extraction of holes and achieve good turn-off characteristics. Therefore, the application can not only improve the anti-latch-up capability of the IGBT, but also improve the turn-off capability of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and relates to an insulated gate bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] The insulated gate bipolar transistor (IGBT) combines the voltage control of the metal oxide semiconductor field effect transistor (MOS) and the current conduction modulation of the bipolar junction transistor (BJT), has the characteristics of high input impedance, small switching loss, high speed, small voltage drive power, and is widely used in power transmission, high-speed train traction, industrial driving, clean energy and many other fields. The IGBT is prone to latch-up failure due to the parasitic PNPN structure, which limits its use in some fields.

[0003] The existing trench type IGBT is provided with an N+ active region, a P-type base region, an N-drift layer and a P+ collector region in the vertical direction. Since the N+ active region, the P-type base region, the N-drift layer and the P+ collector region form a parasitic PNPN structure, when the collector current is very large, the voltage drop generated by the collector current through the base resistance causes the PN junction composed of the P-type base region and the N+ active region to be forward-biased, so that the current no longer flows through the channel, but directly flows from the P-type base region to the emitter, the gate electrode loses control of the IGBT, the current sharply rises, the voltage decreases, and the device fails. At this time, the sum of the current amplification coefficients of the PNP tube and the NPN is α PNP + α NPN = 1, and this phenomenon is usually referred to as latch-up. In order to improve the latch-up of the device, it is usually considered to reduce α PNP and α NPN The commonly used method is to increase the concentration of the P-type base region below the N+ active region and reduce the P-type base region body resistance, thereby improving the latch-up capability of the IGBT. However, the concentration of the P-type base region below the N+ active region cannot be increased all the time, and if the concentration is too high, the N+ active region will be compensated, which will affect the opening of the device. Therefore, the P-type base region body resistance always exists, although it can be reduced, but cannot be eliminated, so when the hole current continuously increases, the PN junction will be forward-biased, thereby causing latch-up. Therefore, the method of reducing the base resistance has limited ability to improve the latch-up. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an insulated gate bipolar transistor and a manufacturing method thereof, which can solve the problem of difficult elimination of latch-up in the prior art.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides an insulated gate bipolar transistor, comprising:

[0006] A substrate is provided with a collector region, a field stop layer, a drift layer and a base region stacked in sequence from bottom to top;

[0007] At least two spaced-apart trench gate structures extending through the base region from the upper surface of the base region into the drift layer;

[0008] An emitter region located on the upper surface of the base region and adjacent to the trench gate structures;

[0009] An insulating buried layer located in the base region below the emitter region and spaced apart from the trench gate structures by a predetermined distance;

[0010] A contact region located in the base region below the insulating buried layer;

[0011] An interlayer dielectric layer located on the trench gate structures and the emitter region;

[0012] An emitter conductive layer located on the interlayer dielectric layer;

[0013] A conductive connection extending through the interlayer dielectric layer, the emitter region and the insulating buried layer to the contact region, the emitter conductive layer being electrically connected to the contact region through the conductive connection;

[0014] The collector region, the base region and the contact region are of a first conductivity type, the field stop layer, the drift layer and the emitter region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0015] Optionally, the insulating buried layer is adjacent to the emitter region and to the contact region.

[0016] Optionally, one side of the insulating buried layer close to the conductive connection is spaced apart from the emitter region, and the other side of the insulating buried layer close to the trench gate structures is adjacent to the emitter region.

[0017] Optionally, the collector region and the contact region have a higher doping concentration than the base region, and the field stop layer and the emitter region have a higher doping concentration than the drift layer.

[0018] Optionally, the insulated gate bipolar transistor further comprises a carrier storage layer located between the drift layer and the base region, the carrier storage layer being of the same conductivity type as the drift layer and having a higher doping concentration than the drift layer.

[0019] Optionally, the trench gate structures comprise a gate conductive layer and a gate dielectric layer, the gate dielectric layer surrounding the side and bottom surfaces of the gate conductive layer.

[0020] The application further provides a manufacturing method of an insulated gate bipolar transistor, comprising the following steps:

[0021] providing a substrate pre-formed with a field stop layer;

[0022] forming a drift layer above the field stop layer;

[0023] forming at least two spaced-apart trench gate structures, the trench gate structures extending into the drift layer from the upper surface of the drift layer;

[0024] forming a base region in the upper layer of the drift layer, the junction depth of the base region being smaller than the groove depth of the trench gate structures;

[0025] forming an insulating buried layer in the base region, the insulating buried layer being spaced apart from the trench gate structures by a preset distance;

[0026] forming an emitter region in the upper layer of the base region, the emitter region being located above the insulating buried layer;

[0027] forming an interlayer dielectric layer covering the trench gate structures and the emitter region;

[0028] forming a contact hole penetrating the interlayer dielectric layer, the emitter region and the insulating buried layer from the upper surface of the interlayer dielectric layer, the bottom of the contact hole exposing the base region;

[0029] forming a contact region on the surface of the base region exposed at the bottom of the contact hole;

[0030] forming a conductive material layer covering the upper surface of the interlayer dielectric layer and filling the contact hole, the conductive material layer on the interlayer dielectric layer being an emitter conductive layer, the conductive material layer in the contact hole being a conductive connecting part, the emitter conductive layer being electrically connected to the contact region through the conductive connecting part;

[0031] wherein the base region and the contact region are of a first conductive type, and the emitter region is of a second conductive type, the first conductive type being opposite to the second conductive type.

[0032] Optionally, the step of forming the insulating buried layer in the base region and spacing the insulating buried layer from the trench gate structures by a preset distance further comprises: implanting oxygen into the base region to obtain the insulating buried layer.

[0033] Optionally, the insulating buried layer is adjacent to the emitter region and adjacent to the contact region.

[0034] Optionally, one side of the insulating buried layer close to the conductive connecting part is spaced apart from the emitter region, and the other side of the insulating buried layer close to the trench gate structure is adjacent to the emitter region.

[0035] Optionally, the doping concentration of the contact region is higher than the doping concentration of the base region.

[0036] Optionally, after the formation of the drift layer above the field stop layer, before the formation of the at least two spaced-apart trench gate structures, the method further comprises:

[0037] forming a carrier storage layer having the second conductivity type in the drift layer, the carrier storage layer having a doping depth less than the groove depth of the trench gate structure, and the carrier storage layer having a doping concentration higher than the doping concentration of the drift layer; and

[0038] forming the base region on the upper layer of the drift layer, the base region having a junction depth less than the groove depth of the trench gate structure, further comprising that the junction depth of the base region is also less than the doping depth of the carrier storage layer.

[0039] As described above, the insulated gate bipolar transistor and the manufacturing method thereof have the following advantages. On one hand, by adding the insulating buried layer below the emitter region, the hole current is blocked from flowing through the emitter region and the base region, so that it is very difficult for the PN junction to be positively biased, and the latch-up effect caused by the positively biased PN junction is prevented. On the other hand, by etching the contact hole penetrating through the insulating buried layer, the emitter conductive layer is connected to the P-type base region to form a groove-type emitter. The deep groove emitter can shorten the path of the hole flow, accelerate the extraction of the hole, and achieve good turn-off characteristics. Therefore, the application can not only improve the anti-latch-up capability of the IGBT, but also improve the turn-off capability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 Fig. 1 shows a structure schematic diagram of an insulated gate bipolar transistor.

[0041] Figure 2 Fig. 2 shows a structure schematic diagram of another insulated gate bipolar transistor.

[0042] Figure 3 Fig. 3 shows a flow chart of a manufacturing method of an insulated gate bipolar transistor.

[0043] ELEMENT REFERENCE

[0044] 1 collector region

[0045] 2 field stop layer

[0046] 3 drift layer

[0047] 4 trench gate structure

[0048] 401 gate conductive layer

[0049] 402 gate dielectric layer

[0050] 5 base region

[0051] 6 emitter region

[0052] 7 insulating buried layer

[0053] 8 contact region

[0054] 9 interlayer dielectric layer

[0055] 10 emitter conductive layer

[0056] 11 conductive connection portion

[0057] 12 carrier storage layer

[0058] S1-S8 steps DETAILED DESCRIPTION

[0059] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is to be understood that

[0060] Reference will now be made to the drawings, wherein: Figures 1 to 3 It is to be understood that the above-mentioned embodiments are only illustrative of the application and that modifications and variations can be effected without departing from the scope of the application as defined in the appended claims.

[0061] Embodiment 1

[0062] In this embodiment, an insulated gate bipolar transistor is provided. Please refer to Figure 1, shown as a structural schematic diagram of the insulated gate bipolar transistor, comprising a substrate, at least two trench gate structures 4 arranged in a horizontal direction, an emission region 6, an insulating buried layer 7, a contact region 8, an interlayer dielectric layer 9, an emitter conductive layer 10, and a conductive connection part 11, wherein the substrate is provided with a collector region 1, a field stop layer 2, a drift layer 3, and a base region 5 which are sequentially stacked from bottom to top, the trench gate structure 4 penetrates the base region 5 from the upper surface of the base region 5 and extends into the drift layer 3; the emission region 6 is on the upper surface of the base region 5 and is adjacent to the trench gate structure; the insulating buried layer 7 is located in the base region 5 and below the emission region 6, and is spaced apart from the trench gate structure 4 by a predetermined distance; the contact region 8 is located in the base region 5 and below the insulating buried layer 7; the interlayer dielectric layer 9 is located on the trench gate structure 4 and the emission region 6; the emitter conductive layer 10 is located on the interlayer dielectric layer 9; the conductive connection part 11 penetrates the interlayer dielectric layer 9, the emission region 6, and the insulating buried layer 7 and extends to the contact region 8, and the emitter conductive layer 10 is electrically connected to the contact region 8 through the conductive connection part.

[0063] As an example, the insulating buried layer 7 is adjacent to the emission region 6 and is adjacent to the contact region 8. Specifically, the insulating buried layer 7 is configured to block as many hole paths between the PN junction between the emission region 6 and the base region 5 as possible without affecting the electron path (the insulating buried layer 7 cannot be in contact with the trench gate structure 4). In this embodiment, all the upper surfaces of the insulating buried layer 7 are in contact with the lower surface of the emission region 6, and the lower surface of the insulating buried layer 7 is in contact with the contact region 8. The material of the insulating buried layer 7 can include silicon dioxide.

[0064] In other embodiments, as shown in Figure 2 the side of the insulating buried layer 7 close to the conductive connection part 11 is spaced apart from the emission region 6, and the side of the insulating buried layer 7 close to the trench gate structure 4 is adjacent to the emission region 6. That is, the upper surface of the side of the insulating buried layer 7 close to the conductive connection part 11 is spaced apart from the emission region 6, and the lower surface of the side of the insulating buried layer 7 close to the conductive connection part 11 is in contact with the contact region 8; the upper surface of the side of the insulating buried layer 7 close to the trench gate structure 4 is in contact with the emission region 6, and the lower surface of the side of the insulating buried layer 7 close to the trench gate structure 4 is spaced apart from the contact region 8. In addition, the side of the insulating buried layer 7 close to the trench gate structure 4 is also spaced apart from the trench gate structure 4 by a predetermined distance.

[0065] Specifically, the insulating buried layer 7 can block the hole current from flowing through the PN junction composed of the emitter region 6 and the base region 5, so that it is very difficult for the PN junction to be positively biased, and the latch-up effect caused by the positive bias of the PN junction is prevented. In addition, since the conductive connection part 11 penetrates the interlayer dielectric layer 9, the emitter region 6 and the insulating buried layer 7 in the vertical direction, the emitter conductive layer 10 and the conductive connection part 11 form a groove-type emitter, and the deep groove emitter can shorten the hole flow path, accelerate the extraction of holes, and improve the turn-off capability of the device. Also based on the fact that the conductive connection part 11 penetrates the insulating buried layer 7, the insulating buried layer 7 does not block the path of the holes from the base region 5 to the emitter stage through the contact region 8, thereby eliminating the problem that the holes can only flow from the PN junction to the emitter stage through the two sides of the insulating buried layer, which makes the PN junction very easy to be positively biased and opened, thereby causing a worse latch-up capability. Among them, Figure 2 The insulating gate bipolar transistor shown in Figure 1 The insulating gate bipolar transistor shown in has similar performance, that is, also has stronger anti-latch-up capability and better turn-off characteristics.

[0066] As an example, the collector region 1, the base region 5 and the contact region 8 are of a first conductivity type, and the doping concentration of the collector region 1 and the contact region 8 is higher than that of the base region 5; the field stop layer 2, the drift layer 3 and the emitter region 6 are of a second conductivity type, and the doping concentration of the field stop layer 2 and the emitter region 6 is higher than that of the drift layer 3; the first conductivity type can be P-type or N-type, and the first conductivity type is opposite to the second conductivity type. For example, in this embodiment, the collector region 1 is selected to be P-type heavily doped silicon, the field stop layer 2 is selected to be N-type heavily doped silicon, the drift layer 3 is selected to be N-type lightly doped silicon, the base region 5 is selected to be P-type silicon, the contact region 8 is selected to be P-type heavily doped silicon, and the emitter region 6 is selected to be N-type heavily doped silicon. It should be pointed out that the above-mentioned lightly doped, doped and heavily doped are relative relationships, and the doping concentration satisfies lightly doped < doped < heavily doped. Under the premise of satisfying the relative relationship, the specific doping concentration of each region can be adjusted as needed, which should not be too limited to the protection scope of the present application. In addition, the materials of the collector region 1, the field stop layer 2, the drift layer 3, the base region 5, the emitter region 6 and the contact region 8 are not limited to silicon, but can also be other suitable semiconductor materials, such as germanium, germanium silicon, III-V compounds, etc.

[0067] As an example, in order to optimize the distribution of the minority carriers in the device in the on-state, further enhance the conductance modulation effect, and reduce the forward on-state voltage drop of the device, the insulated gate bipolar transistor further comprises a carrier storage layer 12 located between the drift layer 3 and the base region 5, the carrier storage layer 12 has the same conductivity type as the drift layer 3, and the doping concentration of the carrier storage layer 12 is higher than that of the drift layer 3. For example, in this embodiment, the carrier storage layer 12 is made of N-type heavily doped silicon

[0068] As an example, the trench gate structure 4 comprises a gate conductive layer 401 and a gate dielectric layer 402, and the gate dielectric layer 402 surrounds the side surface and bottom surface of the gate conductive layer 401. The material of the gate conductive layer 401 includes but is not limited to polysilicon, and the material of the gate dielectric layer 402 includes but is not limited to silicon oxide.

[0069] The insulated gate bipolar transistor of this embodiment can prevent the latch-up effect caused by the positive bias of the PN junction in two ways. On the one hand, by adding an insulating buried layer below the emitter region, the hole current is prevented from flowing through the emitter region and the base region, so that it is very difficult for the PN junction to be positively biased, thereby preventing the latch-up effect caused by the positive bias of the PN junction. On the other hand, by the conductive connection part penetrating through the insulating buried layer, the emitter conductive layer is connected to the contact region in the base region, which can shorten the hole flow path and accelerate the extraction of holes, thereby achieving good turn-off characteristics. That is, the insulated gate bipolar transistor of this embodiment not only has stronger anti-latch-up capability, but also has better turn-off characteristics.

[0070] Embodiment two

[0071] In this embodiment, a manufacturing method of an insulated gate bipolar transistor is provided, which can be used to manufacture the insulated gate bipolar transistor described in embodiment one. Please refer to Figure 3 , which shows a flowchart of the manufacturing method of the insulated gate bipolar transistor, comprising the following steps:

[0072] S1: providing a substrate pre-formed with a field stop layer;

[0073] S2: forming a drift layer above the field stop layer;

[0074] S3: forming at least two spaced trench gate structures, which extend into the drift layer from the upper surface of the drift layer;

[0075] S4: forming a base region in the upper layer of the drift layer, and the junction depth of the base region is smaller than the groove depth of the trench gate structure;

[0076] S5: forming an insulating buried layer in the base region, and the insulating buried layer is spaced apart from the trench gate structure by a predetermined distance;

[0077] S6: An emission region is formed on the upper surface of the base region, and the emission region is located above the insulating buried layer;

[0078] S7: Form an interlayer dielectric layer, the interlayer dielectric layer covering the trench gate structure and the emission region;

[0079] S8: Form a contact hole, the contact hole extending from the upper surface of the interlayer dielectric layer through the interlayer dielectric layer, the emitter region and the insulating buried layer, the bottom of the contact hole exposing the base region;

[0080] S9: A contact area is formed on the surface of the base area exposed at the bottom of the contact hole;

[0081] S10: A conductive material layer is formed and covers the upper surface of the interlayer dielectric layer and fills the contact hole. The conductive material layer on the interlayer dielectric layer is an emitter conductive layer, and the conductive material layer in the contact hole is a conductive connection portion. The emitter conductive layer is electrically connected to the contact area through the conductive connection portion.

[0082] Specifically, the base region and the contact region are of a first conductivity type, and the emission region is of a second conductivity type, with the first conductivity type being the opposite of the second conductivity type.

[0083] As an example, in step S2, the drift layer can be formed by epitaxial growth or ion implantation.

[0084] As an example, in step S5, the insulating buried layer is obtained by oxygenating the base region. Specifically, the oxygen injection is a SIMO (Simulated Injection of Oxygen for Oxygen) technology, which forms the desired oxide layer at the target location by injecting a large dose of high-energy oxygen ions. For example, for... Figure 1 The insulating buried layer shown can be formed through a single ion implantation, for example... Figure 2 The insulating buried layer shown can be divided into two ion implantation processes: the side of the insulating buried layer 7 near the conductive connection portion 11 and the side of the insulating buried layer 7 near the trench gate structure 4. The implantation areas and implantation depths are different.

[0085] As an example, between step S2 and step S3, the method further includes: forming a carrier storage layer with a second conductivity type in the drift layer, wherein the doping depth of the carrier storage layer is less than the trench depth of the trench gate structure, and the doping concentration of the carrier storage layer is higher than the doping concentration of the drift layer; and step S4 further includes: the junction depth of the base region is also less than the doping depth of the carrier storage layer.

[0086] As an example, the substrate includes a second conductivity type substrate and a second conductivity type epitaxial layer epitaxially grown on the surface of the substrate, wherein the doping concentration of the substrate is higher than the doping concentration of the epitaxial layer. Please refer to... Figure 1 In one specific implementation, an N-type lightly doped epitaxial layer is first grown on an N-type heavily doped Si substrate, and a cell region and a terminal region located around the cell region are defined. Implantation and push-junction are performed in the terminal region to form a terminal structure. Figure 1 (Not shown in the text) Ion implantation and push-junction are performed in the epitaxial layer of the cell region to form the N-type heavily doped carrier storage layer 12. The portion of the epitaxial layer below the carrier storage layer 12 serves as the drift layer 3. Trenches are then etched in the epitaxial layer, with the bottom of the trenches extending into the drift layer 3. A gate dielectric layer and a gate conductive layer are then deposited and etched to form the trench gate structure 4. Ion implantation and push-junction are then performed on the upper part of the epitaxial layer to form the P-type doped base region 5 through self-alignment. Oxygen implantation isolation technology is then used to implant oxygen into a predetermined area of ​​the base region 5 to form the insulating buried layer 7. Ion implantation and push-bonding are performed on the top of the extension layer to obtain the N-type heavily doped emitter region 6. Then, silicon oxide, silicon nitride or other suitable insulating material is deposited as the interlayer dielectric layer 9. Contact holes are formed through the interlayer dielectric layer 9, the emitter region 6 and the insulating buried layer 7 and the base region 5 is exposed. A conductive metal or other suitable conductive material layer is deposited and etched to obtain the conductive connection portion 11 and the emitter conductive layer 10. Finally, etching is performed to form a pad (not shown). Ion implantation and thinning are performed on the back side of the substrate to form the P-type heavily doped collector region 1. The portion of the substrate located on the collector region 1 serves as the field cutoff layer 2.

[0087] As an example, the substrate can also be of the second conductivity type. In one specific implementation, the substrate is an N-type lightly doped single-crystal silicon substrate. First, the cell region and the terminal region located around the cell region are defined. Implantation and push-junction are performed in the terminal region to form a terminal structure. Figure 1 Figure 1The ion implantation and push-junction in the single crystal silicon substrate of the cell region form the N-type heavily doped carrier storage layer 12, wherein the part of the single crystal silicon substrate below the carrier storage layer 12 serves as the drift layer 3, then the single crystal silicon substrate is etched to form a groove, the bottom of the groove extends into the drift layer 3, then the gate dielectric layer and the gate conductive layer are deposited and etched to form the trench gate structure 4, then the ion implantation and push-junction on the upper part of the single crystal silicon substrate form the P-type doped base region 5 in self-alignment, then the oxygen implantation isolation technology is used to implant oxygen in the preset region of the base region 5 to form the insulating buried layer 7, the ion implantation and push-junction on the top of the single crystal silicon substrate form the N-type heavily doped emitter region 6, then the silicon oxide, silicon nitride or other suitable insulating material is deposited as the interlayer dielectric layer 9, the contact hole is etched to pass through the interlayer dielectric layer 9, the emitter region 6 and the insulating buried layer 7 and expose the base region 5, the conductive metal or other suitable conductive material layer is deposited and etched to form the conductive connection part 11 and the emitter conductive layer 10, finally, the etching is performed to form the pad (not shown), and the ion implantation is performed on the back surface of the single crystal silicon substrate in sequence to form the N-type heavily doped field stop layer 2 and the P-type heavily doped collector region 1. The back surface of the single crystal silicon substrate can be thinned according to needs.

[0088] In summary, the insulated gate bipolar transistor and the manufacturing method thereof can block the hole current from flowing through the emitter region and the base region by adding the insulating buried layer below the emitter region, so that it is very difficult for the PN junction to be positively biased, and the latch-up effect caused by the positively biased PN junction is prevented. In addition, the contact hole is etched to pass through the insulating buried layer, so that the emitter conductive layer is connected to the P-type base region to form a groove type emitter. The deep groove emitter can shorten the hole flow path and accelerate the extraction of holes to achieve good turn-off characteristics. Therefore, the anti-latch-up capability of the IGBT can be improved, and the turn-off capability of the device can be improved, and the defects in the prior art are effectively overcome, so that the application has high industrial utilization value.

[0089] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. An insulated gate bipolar transistor, characterized by, The insulated gate bipolar transistor comprises: a substrate provided with a collector region, a field stop layer, a drift layer and a base region stacked in sequence from bottom to top; at least two spaced-apart trench gate structures penetrating the base region from the upper surface of the base region and extending into the drift layer; an emitter region located on the upper surface of the base region and adjacent to the trench gate structures; an insulating buried layer located in the base region below the emitter region and spaced apart from the trench gate structures by a preset distance; a contact region located in the base region below the insulating buried layer; an interlayer dielectric layer located on the trench gate structures and the emitter region; an emitter conductive layer located on the interlayer dielectric layer; a conductive connection portion penetrating the interlayer dielectric layer, the emitter region and the insulating buried layer and extending to the contact region, the emitter conductive layer being electrically connected to the contact region through the conductive connection portion; wherein the collector region, the base region and the contact region are of a first conductivity type, the field stop layer, the drift layer and the emitter region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type; the insulating buried layer is adjacent to the emitter region and adjacent to the contact region.

2. The insulated gate bipolar transistor of claim 1, wherein: The side of the insulating buried layer close to the conductive connection portion is spaced apart from the emitter region, and the side of the insulating buried layer close to the trench gate structures is adjacent to the emitter region.

3. The insulated gate bipolar transistor of claim 1, wherein: The doping concentration of the collector region and the contact region is higher than the doping concentration of the base region, and the doping concentration of the field stop layer and the emitter region is higher than the doping concentration of the drift layer.

4. The insulated gate bipolar transistor of claim 1, wherein: The insulated gate bipolar transistor further comprises a carrier storage layer located between the drift layer and the base region, the carrier storage layer being of the same conductivity type as the drift layer and having a doping concentration higher than that of the drift layer.

5. The insulated gate bipolar transistor of claim 1, wherein: The trench gate structure comprises a gate conductive layer and a gate dielectric layer, the gate dielectric layer surrounding the side and bottom surfaces of the gate conductive layer.

6. A method of fabricating an insulated gate bipolar transistor, characterized by, The method comprises the following steps: providing a substrate pre-formed with a field stop layer; forming a drift layer above the field stop layer; forming at least two spaced-apart trench gate structures penetrating the drift layer from the upper surface of the drift layer; forming a base region on the upper surface of the drift layer, the base region having a junction depth smaller than the groove depth of the trench gate structures; forming an insulating buried layer in the base region, the insulating buried layer being spaced apart from the trench gate structures by a preset distance; forming an emitter region on the upper surface of the base region, the emitter region being located above the insulating buried layer; forming an interlayer dielectric layer covering the trench gate structures and the emitter region; forming a contact hole penetrating the interlayer dielectric layer, the emitter region and the insulating buried layer from the upper surface of the interlayer dielectric layer, the bottom of the contact hole exposing the base region; forming a contact region on the surface of the base region exposed at the bottom of the contact hole; The conductive material layer formed on the upper surface of the interlayer dielectric layer and filling the contact hole is an emitter conductive layer, and the conductive material layer in the contact hole is a conductive connecting part, and the emitter conductive layer is electrically connected with the contact area through the conductive connecting part. The base area and the contact area are of a first conductive type, the emitter area is of a second conductive type, and the first conductive type is opposite to the second conductive type; the insulating buried layer is adjacent to the emitter area and adjacent to the contact area.

7. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein: The insulating buried layer is formed in the base area by injecting oxygen into the base area.

8. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein: The side of the insulating buried layer close to the conductive connecting part is spaced apart from the emitter area, and the side of the insulating buried layer close to the trench gate structure is adjacent to the emitter area.

9. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein: The doping concentration of the contact area is higher than that of the base area.

10. The method of fabricating an insulated gate bipolar transistor of claim 6, wherein: The forming of the drift layer, after the drift layer is formed above the field stop layer and before the forming of the at least two spaced-apart trench gate structures, further comprises: forming a carrier storage layer having the second conductive type in the drift layer, the doping depth of the carrier storage layer is less than the groove depth of the trench gate structure, and the doping concentration of the carrier storage layer is higher than the doping concentration of the drift layer; and The forming of the base area on the upper surface of the drift layer, the junction depth of the base area being less than the groove depth of the trench gate structure, further comprises: the junction depth of the base area is also less than the doping depth of the carrier storage layer.

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