Detection circuit and device for detecting a connector

Abstract

The application provides a detection circuit and equipment for detecting a connector, which comprises a mainboard and a subboard, wherein the mainboard is provided with a first connector and a complex programmable logic device; the subboard comprises a second connector and a self-oscillation signal generation unit; the complex programmable logic device is connected with the first connector, the first connector is connected with the second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generation unit is connected with a power supply; the self-oscillation signal generation unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; and the complex programmable logic device is used for determining whether the second connector connected with the first connector is correct according to the received pulse signal and a preset signal corresponding to the first connector, so that the subboard connector connected with the connector on the mainboard can be determined based on the complex programmable logic device on the mainboard.

Description

TECHNICAL FIELD

[0001] The present application relates to the electronic field, and in particular to a detection circuit and device for detecting a connector. BACKGROUND

[0002] At present, in an electronic device, a main board and at least one sub-board can be usually provided. The main board and the sub-board are connected through a connector.

[0003] In the related art, in order to ensure the accuracy of the connection between the main board and the sub-board through the connector, that is, the connector of the main board is accurately connected to the corresponding connector of the sub-board, a complex programmable logic device on the main board usually sends a pulse width modulation signal to a complex programmable logic device on the sub-board through the connector of the main board, the connector of the sub-board connected to the connector of the main board, and the complex programmable logic device on the sub-board. The complex programmable logic device on the sub-board performs frequency division processing on the received pulse width modulation signal and returns the processed signal to the complex programmable logic device on the main board, so that the complex programmable logic device in the main board detects according to the received signal to determine the connection accuracy of the currently connected main board connector and sub-board connector.

[0004] However, when there is no complex programmable logic device on the sub-board, at this time, adding an additional complex programmable logic device easily leads to occupying more space, resulting in an increase in the manufacturing cost of the electronic device. SUMMARY

[0005] The present application provides a detection circuit and device for detecting a connector to solve the problem of relying on a complex programmable logic device on a sub-board for connector detection in the related art.

[0006] In a first aspect, the present application provides a detection circuit for detecting a connector, the detection circuit comprising: a main board and a sub-board,

[0007] wherein the main board is provided with a first connector and a complex programmable logic device; the sub-board comprises a second connector and a self-oscillation signal generation unit;

[0008] The complex programmable logic device is connected to the first connector, the first connector is connected to the second connector, the second connector is connected to the output end of the self-oscillation signal generation unit, and the self-oscillation signal generation unit is connected to a power supply;

[0009] The self-oscillation signal generation unit is configured to generate a pulse signal in a power supply state and output the pulse signal to the complex programmable logic device, and the complex programmable logic device is configured to determine whether the second connector connected to the first connector is correct according to the received pulse signal and a preset signal corresponding to the first connector.

[0010] In a possible implementation, the self-oscillation signal generation unit comprises a first NOT gate module, a first resistor and a first capacitor.

[0011] The first end of the first capacitor is connected to the power supply end of the first NOT gate module and the power supply. The second end of the first capacitor is grounded. The output end of the first NOT gate module is connected to the second end of the first resistor and the second connector. The power supply end of the first NOT gate module is connected to the power supply.

[0012] In a possible implementation, the self-oscillation signal generation unit further comprises a second resistor and a second capacitor.

[0013] The first end of the second capacitor is connected to the power supply end of the first NOT gate module and the power supply. The second end of the second capacitor is grounded.

[0014] The first end of the second resistor is connected to the output end of the first NOT gate module and the second end of the first resistor. The second end of the second resistor is connected to the second connector. The output end of the first NOT gate module is connected to the second connector through the second resistor.

[0015] In a possible implementation, the number of the first connectors arranged on the mainboard is plural. The subboard comprises a second connector corresponding to the first connector one by one, and a self-oscillation signal generation unit corresponding to the second connector one by one.

[0016] The pulse signals generated by different self-oscillation signal generation units are different.

[0017] In a possible implementation, the mainboard is provided with a third connector. The subboard is provided with a fourth connector and a third resistor.

[0018] The first input end of the third connector and the first output end of the third connector are connected to the complex programmable logic device respectively. The second output end of the third connector is connected to the first input end of the fourth connector. The first output end of the fourth connector is connected to the first end of the third resistor. The second end of the third resistor is connected to the second input end of the fourth connector. The second output end of the fourth connector is connected to the second input end of the third connector.

[0019] The complex programmable logic device is configured to send a pulse width modulation signal to the fourth connector through the third connector, and the fourth connector is configured to return the pulse width modulation signal received by the second connector to the complex programmable logic device through the third connector.

[0020] The complex programmable logic device is further configured to determine whether the fourth connector connected with the third connector is correct according to the pulse modulation signal sent by the third connector and the pulse width modulation signal returned by the third connector.

[0021] In a possible implementation, the mainboard is provided with a fifth connector, and the subboard is provided with a sixth connector and an inverter circuit.

[0022] The first input end of the fifth connector and the first output end of the fifth connector are connected with the complex programmable logic device respectively; the second output end of the fifth connector and the first input end of the sixth connector are connected with the complex programmable logic device respectively; the first output end of the sixth connector is connected with the input end of the inverter circuit, the output end of the inverter circuit is connected with the second input end of the sixth connector, and the second output end of the sixth connector is connected with the second input end of the fifth connector.

[0023] The complex programmable logic device is configured to send a pulse width modulation signal to the sixth connector through the fifth connector, and the inverter circuit is configured to perform inversion processing on the phase of the pulse width modulation signal and send the processed signal to the complex programmable logic device through the sixth connector and the fifth connector.

[0024] The complex programmable logic device is further configured to determine whether the sixth connector connected with the fifth connector is correct according to the pulse modulation signal sent by the fifth connector and the pulse width modulation signal returned by the fifth connector.

[0025] In a possible implementation, the inverter circuit comprises a triode, a fourth resistor, a fifth resistor and a sixth resistor.

[0026] The first end of the triode is connected with the first end of the fourth resistor and the second input end of the sixth connector respectively; and the second end of the fourth resistor is connected with a power supply.

[0027] The second end of the triode is connected with the first end of the fifth resistor and the first end of the sixth resistor respectively; the third end of the triode is connected with the second end of the fifth resistor and then grounded; and the second end of the sixth resistor is connected with the first output end of the sixth connector.

[0028] In a possible implementation, the inverter circuit comprises a diode, a second NOT gate module, a seventh resistor and a third capacitor.

[0029] An anode of the diode is connected with a first output end of the sixth connector; a cathode of the diode is connected with a first end of the seventh resistor, a first end of the third capacitor and an input end of the second NOT gate module respectively; a second end of the seventh resistor and a second end of the third capacitor are connected and then grounded; a power supply end of the second NOT gate module is connected with a power supply; and an output end of the second NOT gate module is connected with a second input end of the sixth connector.

[0030] In a possible implementation, the inverter circuit further comprises a fourth capacitor and an eighth resistor.

[0031] The first end of the fourth capacitor is connected with the power supply end of the second NOT gate module and the power supply respectively; and the second end of the fourth capacitor is grounded.

[0032] The first end of the eighth resistor is connected with the output end of the second NOT gate module; the second end of the eighth resistor is connected with the second input end of the sixth connector; and the output end of the second NOT gate module is connected with the second input end of the sixth connector through the eighth resistor.

[0033] In a second aspect, the present application provides an electronic device comprising the detection circuit in any of the first aspect.

[0034] The application provides a detection circuit and a device for detecting a connector, which comprises a main board and a sub-board, wherein the main board is provided with a first connector and a complex programmable logic device; the sub-board comprises a second connector and a self-oscillation signal generation unit; the complex programmable logic device is connected with the first connector, the first connector is connected with the second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generation unit is connected with a power supply; the self-oscillation signal generation unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; and the complex programmable logic device is used for determining whether the second connector connected with the first connector is correct according to the received pulse signal and a preset signal corresponding to the first connector. In the application, the self-oscillation signal generation unit is arranged on the sub-board, and the generated pulse signal is sent to the complex programmable logic device on the main board, so that the complex programmable logic device on the main board can compare the received pulse signal with the preset signal corresponding to the first connector, and if the comparison result is the same, it indicates that the first connector is connected accurately. Therefore, the detection circuit can avoid the problem that the received signal cannot be processed when the complex programmable logic device does not exist in the sub-board. Furthermore, the problem of large occupied space caused by the additional complex programmable logic device on the sub-board can be avoided. Furthermore, after the second connector connected with the first connector is identified, the type of the sub-board where the second connector is located can be further determined, and the connection relationship between the connectors of the main board and the sub-board can be further determined. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0036] Figure 1 A structural schematic diagram of a detection circuit provided by the application;

[0037] Figure 2 A structural schematic diagram of a detection circuit for detecting a connector provided by an embodiment of the application;

[0038] Figure 3 A structural schematic diagram of a second detection circuit for detecting a connector provided by an embodiment of the application;

[0039] Figure 4 A structural schematic diagram of a third detection circuit for detecting a connector provided by an embodiment of the application;

[0040] Figure 5A fourth structure diagram of a detection circuit for detecting a connector is provided for the embodiments of the present application;

[0041] Figure 6 A fifth structure diagram of a detection circuit for detecting a connector is provided for the embodiments of the present application;

[0042] Figure 7 A sixth structure diagram of a detection circuit for detecting a connector is provided for the embodiments of the present application;

[0043] Figure 8 A seventh structure diagram of a detection circuit for detecting a connector is provided for the embodiments of the present application.

[0044] Figure 9 A second structure diagram of an inverter circuit is provided for the embodiments of the present application.

[0045] Figure 10 A third structure diagram of an inverter circuit is provided for the embodiments of the present application.

[0046] Figure 11 A seventh structure diagram of a detection circuit for detecting a connector is provided for the embodiments of the present application.

[0047] The specific embodiments of the present application have been shown through the above-described drawings, and will be described in more detail hereinafter. These drawings and the following description are not intended to limit the scope of the present application in any way, but to explain the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0048] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The same reference numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application.

[0049] Currently, in an electronic device, a main board and at least one sub-board are usually provided. For example, the devices on the main board are used to realize the core functions of the electronic device. The devices on the sub-board are used to realize the additional functions of the electronic device. When the main board and the sub-board are connected, the main board connector and the corresponding sub-board connector are usually connected one by one.

[0050] In the related art, in order to ensure the accuracy of the connection between the main board and the sub-board, i.e., the main board connector is connected to the corresponding sub-board connector, a detection circuit is provided. As shown in Figure 1 Figure 1 ​A structural diagram of a detection circuit provided in the present application is shown in FIG. 1. Figure 1 The detection circuit shown in FIG. 1 is a structural diagram of a circuit provided in the related art, as shown in FIG. 2. Figure 1 Figure 1 The mainboard and the subboard are included in FIG. 3. The mainboard includes a first Complex Programmable Logic Device (CPLD) and a connector 1. The subboard includes a second CPLD and a connector 2. The connector 1 is connected with the connector 2. In order to detect the accuracy of the connection between the connector 1 and the connector 2, i.e., whether the connector 2 is the connector on the subboard that the connector 1 should be connected with, the first CPLD sends a PWM (Pulse Width Modulation) signal to the second CPLD through the connector 1 and the connector 2. The second CPLD processes the received PWM signal by frequency division, and returns the processed signal to the first CPLD through the connector 2 and the connector 1. After the first connector receives the processed signal, it compares the frequency ratio of the PWM signal it sends and the processed signal it receives. If the frequency ratio meets the preset requirement, it means that the connection between the connector 1 and the connector 2 is correct. If the frequency ratio does not meet the preset requirement, it means that the connection between the connector 1 and the connector 2 is incorrect.

[0051] However, when the subboard does not include the second CPLD chip, the accuracy of the connection between the connector cannot be detected. If the second CPLD chip is added to the subboard, it will occupy more space resources, which is not conducive to improving the integration of the electronic device.

[0052] The detection circuit for detecting the connector provided in the present application solves the above technical problems.

[0053] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0054] Figure 2 A structural diagram of a detection circuit for detecting the connector provided in the present application is shown in FIG. 1. Figure 2 ​As shown, the device comprises: a detection circuit comprising: a mainboard and a daughterboard, wherein the mainboard is provided with a first connector and a complex programmable logic device; the daughterboard comprises: a second connector and a self-oscillation signal generation unit; the complex programmable logic device is connected with the first connector, the first connector is connected with the second connector, and the second connector is connected with the output end of the self-oscillation signal generation unit; the self-oscillation signal generation unit is connected with a power supply; the self-oscillation signal generation unit is used for generating a pulse signal in a power supply state and outputting the pulse signal to the complex programmable logic device; and the complex programmable logic device is used for determining whether the second connector connected with the first connector is correct according to the received pulse signal and a preset signal corresponding to the first connector.

[0055] Exemplarily, the detection circuit provided in the embodiment comprises a mainboard and a daughterboard. The daughterboard is provided with a self-oscillation signal generation unit, wherein the self-oscillation signal generation unit is connected with a power supply and is used for receiving a power supply signal output by the power supply (indicated by STB in the figure). When the self-oscillation signal generation unit is in a power supply state, the self-oscillation signal generation unit can generate a pulse signal without external excitation. Then, the self-oscillation signal generation unit transmits the generated pulse signal to the programmable logic device through the second connector on the daughterboard connected with the self-oscillation signal generation unit, the first connector on the mainboard connected with the second connector, and the complex programmable logic device connected with the first connector.

[0056] When the programmable logic device receives the pulse signal returned by the first connector, the programmable logic device finds a preset signal corresponding to the first connector and compares the preset signal with the pulse signal returned by the first connector. If it is determined that the pulse signal returned by the first connector is the same as the preset signal corresponding to the first connector, it is determined that the first connector is currently in a connection state, and the second connector connected with the first connector is the connector corresponding to the first connector, that is, the connector connected with the first connector is correct. If it is determined that the pulse signal returned by the first connector is not the same as the preset signal corresponding to the first connector, it is indicated that the connection mode of the first connector is incorrect, that is, the currently connected second connector is not the connector to which the first connector should be connected. It should be noted that the circuit structure of the self-oscillation signal generation unit is not limited in the embodiment.

[0057] It can be understood that in the embodiment, the self-oscillation signal generating unit can be arranged on the daughter board to send the generated pulse signal to the complex programmable logic device on the main board, so that the complex programmable logic device on the main board can compare the received pulse signal with the preset signal corresponding to the first connector receiving the pulse signal, and if the comparison result is the same, it indicates that the first connector is connected accurately. Further, the above detection circuit can avoid the problem that when there is no complex programmable logic device in the daughter board, the received signal cannot be processed. Furthermore, it can further avoid the problem of large space occupation caused by the additional complex programmable logic device on the daughter board. Moreover, after identifying the second connector connected by the first connector, it can further determine the type of the daughter board where the second connector is located, and further determine the connection relationship between the connectors of the main board and the daughter board.

[0058] In some embodiments, Figure 3 A second structure diagram of a detection circuit for detecting a connector is provided in the embodiments of the present application. As shown in Figure 3 Based on the structure of the device shown in Figure 2 In the embodiments, the self-oscillation signal generating unit includes a first NAND gate module, a first resistor and a first capacitor; the input end of the first NAND gate module is connected with the first end of the first resistor and the first end of the first capacitor respectively; the second end of the first capacitor is grounded; the output end of the first NAND gate module is connected with the second end of the first resistor and the second connector respectively; and the power supply end of the first NAND gate module is connected with a power supply.

[0059] Exemplarily, the self-oscillation circuit in the detection circuit provided in the embodiments includes a first NAND gate module, a first resistor and a first capacitor. Figure 3 In the embodiments, the first resistor is identified as R1, the first capacitor is identified as C1, and the first NAND gate module is identified as U1. The input end (identified as port A in the figure) of the first NAND gate module is connected to the output end (identified as port Y in the figure) of the first NAND gate module through the first resistor, and the input end of the first NAND gate module is also connected with the first capacitor, and the second end of the first capacitor is grounded. In addition, the output end of the first NAND gate module is connected with the second connector on the daughter board. The power supply end (identified as VCC in the figure) of the first NAND gate module is connected with a power supply.

[0060] When the first NOT gate module is in the power supply state, at this time, if the signal outputted by the output end of the first NOT gate module is low, since the input end of the first NOT gate module and the output end of the first NOT gate module are connected together through the first resistor, the low signal received by the input end of the first NOT gate module is subjected to level conversion, and then the high signal outputted by the first NOT gate module. Further, when the first NOT gate module outputs the high signal, at this time, the input end of the first NOT gate module also receives the high signal outputted by the first NOT gate module, and the received high signal is subjected to level conversion, and then the output end of the first NOT gate module outputs the low signal again, and the above process is repeatedly performed, and then the pulse signal is formed. Since the output end of the first NOT gate module is also connected with the second connector, the second connector can receive the pulse signal outputted by the first NOT gate module, so that the complex programmable logic device on the mainboard can receive the pulse signal through the second connector and the first connector.

[0061] In addition, in the embodiment, the pulse width of the pulse signal generated by the first NOT gate module can be adjusted by adjusting the resistance value of the first resistor and / or the capacitance value of the first capacitor.

[0062] It can be understood that, in the embodiment, the self-oscillation signal generation unit is composed of the first NOT gate module, the first resistor and the first capacitor, the circuit structure is simple, easy to implement, and does not need to input external excitation.

[0063] In some embodiments, Figure 4 A third detection circuit structure for detecting a connector provided in the embodiment is shown in FIG. 6. Figure 4 As shown in FIG. 6, based on the device structure shown in FIG. 5, the self-oscillation signal generation unit in the embodiment further includes a second resistor and a second capacitor. Figure 3 The first end of the second capacitor is connected with the power supply end of the first NOT gate module and the power supply, respectively, the second end of the second capacitor is grounded, the first end of the second resistor is connected with the output end of the first NOT gate module and the second end of the first resistor, respectively, the second end of the second resistor is connected with the second connector, and the output end of the first NOT gate module is connected with the second connector through the second resistor.

[0064] Exemplarily, based on the above-mentioned embodiments, the self-oscillation signal generation unit in the embodiment further includes the second resistor and the second capacitor, Figure 4The second resistor is marked as R2, and the second capacitor is marked as C2. The output end of the first NOT gate module is connected with the second end of the first resistor and the first end of the second resistor respectively, and the second end of the second resistor is connected with the second connector. In this way, the pulse signal output by the first NOT gate module can be transmitted to the input end of the first NOT gate module through the first resistor, and can also be transmitted to the second connector through the second resistor. By setting the second resistor, the current value of the transmitted signal can be limited, so as to prevent the device from being damaged due to a large current value.

[0065] In addition, the second capacitor can also be connected at the power supply input end of the first NOT gate module. The first end of the second capacitor is connected with the power supply and the power supply input end of the first NOT gate module respectively, and the second end of the second capacitor is grounded. In this way, the power supply signal output by the power supply can be filtered, so as to maintain the stability of the power supply signal and ensure the normal operation of the first NOT gate module.

[0066] It can be understood that, in the embodiment, the stability of the power supply signal input into the first NOT gate module can be ensured by setting the second capacitor. Furthermore, the second resistor can also be set to limit the current of the signal output by the first NOT gate module, so as to ensure the safety of the devices in the detection circuit.

[0067] In some embodiments, Figure 5 A fourth structure diagram of a detection circuit for detecting a connector is provided in the embodiments of the present application, as shown in Figure 5 Based on the structure of the detection circuit shown in Figure 2 In the embodiments, the number of first connectors provided on the mainboard is multiple. The subboard includes: a second connector connected with the first connector one by one, and a self-oscillation signal generation unit connected with the second connector one by one. The pulse signals generated by different self-oscillation signal generation units are different.

[0068] For example, based on the device shown in Figure 2 In the embodiments, the number of first connectors connected with the complex programmable logic device can be multiple, Figure 5Take three first connectors (i.e., the first connector 1, the first connector 2, and the first connector 3 in the figure) as an example. At this time, three second connectors (i.e., the second connector 1, the second connector 2, and the second connector 3 in the figure) and three self-oscillation signal generation units (i.e., the self-oscillation signal generation unit 1, the self-oscillation signal generation unit 2, and the self-oscillation signal generation unit 3 in the figure) can also be arranged on the daughter board. Among them, the first connector and the second connector are connected one by one, and the second connector and the self-oscillation signal generation unit are connected one by one. Among them, different self-oscillation signal generation units can be used to generate different pulse signals. Further, the complex programmable logic device on the main board can determine which second connector the first connector is currently connected to by detecting the pulse signal returned by the first connector, and further determine the accuracy of the connection of the first connector.

[0069] In some embodiments, Figure 6 A fifth structure diagram of a detection circuit for detecting a connector provided in an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, Figure 6 As shown in FIG. 6, Figure 2 Based on the structure of the detection circuit shown in FIG. 6, in the present embodiment, a third connector is arranged on the main board, and a fourth connector and a third resistor are arranged on the daughter board. Among them, the first input end of the third connector and the first output end of the third connector are connected with the complex programmable logic device respectively; the second output end of the third connector is connected with the first input end of the fourth connector; the first output end of the fourth connector is connected with the first end of the third resistor; the second end of the third resistor is connected with the second input end of the fourth connector, and the second output end of the fourth connector is connected with the second input end of the third connector; the complex programmable logic device is used to send a pulse width modulation signal to the fourth connector through the third connector, and the fourth connector is used to return the pulse width modulation signal received by the second connector to the complex programmable logic device through the third connector; the complex programmable logic device is further used to determine whether the fourth connector connected with the third connector is correct according to the pulse modulation signal sent by the third connector and the pulse width modulation signal returned by the third connector.

[0070] Exemplarily, as shown in FIG. 7, Figure 6As shown, in the embodiment, the mainboard can further include a third connector, and the daughterboard can be provided with a fourth connector and a third resistor (indicated by R3 in the figure). The complex programmable logic device on the mainboard can be connected with a first input end of the third connector, a second output end of the third connector can be connected with a first input end of the fourth connector, and a first output end of the fourth connector can be connected with the third resistor. Thus, the complex programmable logic device on the mainboard can transmit the pulse modulation signal to the first end of the third resistor through the first input end of the third connector, the second output end of the third connector, the first input end of the fourth connector, and the first output end of the fourth connector in sequence. After the pulse modulation signal passes through the third resistor, the pulse modulation signal can be returned to the complex programmable logic device connected with the first output end of the third connector through the second input end of the fourth connector connected with the second end of the third resistor, the second output end of the fourth connector, the second input end of the third connector connected with the second output end of the fourth connector, and the first output end of the third connector in sequence.

[0071] In actual application, the resistance of the third resistor can be 0 ohm. Thus, through the connection relationship of the third connector, the fourth connector, and the third resistor, when the complex programmable logic device sends the pulse modulation signal to the third resistor through the third connector and the fourth connector, the pulse modulation signal can be directly returned to the complex programmable logic device.

[0072] It can be understood that by arranging a third resistor at the connector of the daughterboard, the pulse width and the duty cycle of the returned pulse modulation signal will not change after the pulse modulation signal received by the connector. Thus, the subsequent complex programmable logic device can determine whether it is connected to the fourth connector shown in the figure by whether the transmitted signal and the returned signal are the same.

[0073] In some embodiments, Figure 7 A sixth structure diagram of a detection circuit for detecting a connector provided by the embodiment of the present application is shown in FIG. 6. Figure 7 As shown in FIG. 6, in the embodiment, the mainboard can further include a third connector, and the daughterboard can be provided with a fourth connector and a third resistor (indicated by R3 in the figure). The complex programmable logic device on the mainboard can be connected with a first input end of the third connector, a second output end of the third connector can be connected with a first input end of the fourth connector, and a first output end of the fourth connector can be connected with the third resistor. Thus, the complex programmable logic device on the mainboard can transmit the pulse modulation signal to the first end of the third resistor through the first input end of the third connector, the second output end of the third connector, the first input end of the fourth connector, and the first output end of the fourth connector in sequence. After the pulse modulation signal passes through the third resistor, the pulse modulation signal can be returned to the complex programmable logic device connected with the first output end of the third connector through the second input end of the fourth connector connected with the second end of the third resistor, the second output end of the fourth connector, the second input end of the third connector connected with the second output end of the fourth connector, and the first output end of the third connector in sequence. Figure 2The main board is further provided with a fifth connector; the sub-board is further provided with a sixth connector and an inverter circuit; wherein the first input end of the fifth connector is connected with the complex programmable logic device, and the first output end of the fifth connector is connected with the complex programmable logic device; the second output end of the fifth connector is connected with the first input end of the sixth connector; the first output end of the sixth connector is connected with the input end of the inverter circuit, and the output end of the inverter circuit is connected with the second input end of the sixth connector; the second output end of the sixth connector is connected with the second input end of the fifth connector; the complex programmable logic device is used for sending a pulse width modulation signal to the sixth connector through the fifth connector, the inverter circuit is used for performing phase inversion processing on the pulse width modulation signal, and the processed signal is sent to the complex programmable logic device through the sixth connector and the fifth connector; the complex programmable logic device is further used for determining whether the sixth connector connected with the fifth connector is correct according to the pulse modulation signal sent by the fifth connector and the pulse width modulation signal returned by the fifth connector.

[0074] Exemplarily, as shown in Figure 7 the structure schematic diagram, in the embodiment, the main board is further provided with a fifth connector, and the sub-board is further provided with a sixth connector and an inverter circuit. Figure 2

[0075] The complex programmable logic device on the main board can be connected with the first input end of the fifth connector, the second output end of the fifth connector is connected with the first input end of the sixth connector, and the first output end of the sixth connector is connected with the inverter circuit, so that the complex programmable logic device on the main board can transmit a pulse modulation signal to the first end of the inverter circuit through the first input end of the fifth connector, the second output end of the fifth connector, the first input end of the sixth connector, the first output end of the sixth connector in sequence. After the pulse modulation signal passes through the inverter circuit, it will pass through the second input end of the sixth connector connected with the second end of the inverter circuit, the second output end of the sixth connector, the second input end of the fifth connector connected with the second output end of the sixth connector, the first output end of the fifth connector in sequence, and return the pulse modulation signal processed by the inverter circuit to the complex programmable logic device connected with the first output end of the fifth connector.

[0076] The inverter circuit is used for performing phase inversion processing on the received pulse width modulation signal, that is, converting the high level signal in the pulse width modulation signal into a low level signal, and converting the low level signal in the low level signal in the pulse width modulation signal into a high level signal, and then returning the processed signal to the complex programmable logic device.

[0077] ​When the complex programmable logic device determines that the phases of the signal it sends and the signal it receives are exactly opposite, it can be determined that the connected connector is the sixth connector shown in the figure.

[0078] It is understandable that in this embodiment, an inverter circuit is provided at the connector of the daughter board so that after the pulse modulation signal is received by the connector 5, the received pulse modulation signal can be inverted, thereby

[0079] The subsequent complex programmable logic device can determine whether to connect to the sixth connector shown in the figure based on whether the phases of the sent signal and the returned signal are opposite.

[0080] In some embodiments, Figure 8 This is a schematic diagram of the structure of an inverter circuit provided in an embodiment of the present application.

[0081] The circuit includes: a transistor, a fourth resistor, a fifth resistor and a sixth resistor; the first end of the transistor is connected to the first end of the fourth resistor and the second input end of the sixth connector respectively; the second end of the fourth resistor is connected to the power supply; the transistor

[0082] The second end of the transistor is connected to the first end of the fifth resistor and the first end of the sixth resistor respectively; the third end of the transistor is connected to the second end of the fifth resistor and then grounded; the second end of the sixth resistor is connected to the first output end of the sixth connector.

[0083] For example, the inverter circuit provided in this embodiment may be composed of a transistor and three resistors (i.e., the fourth

[0084] resistor, a fifth resistor, and a sixth resistor). For example, Figure 8 As shown, Figure 8 The fourth resistor, the fifth resistor and the sixth resistor are R4, R5 and R6 respectively.

[0085] The second input end of the sixth connector is connected to output the processed pulse width signal to the sixth connector. The second resistor of the fourth resistor is connected to a power supply (labeled STB in the figure). In addition, the second end of the third connector is connected to the first output end of the sixth connector via the sixth resistor, for receiving the pulse width modulated signal received by the sixth connector.

[0086] In addition, the first end of the fifth resistor is connected to the first end of the sixth resistor and the second end of the transistor respectively, and the second end of the fifth resistor is connected to the third end of the transistor and then grounded.

[0087] When the pulse width modulation signal received by the sixth connector is transmitted to the second end of the transistor through the sixth resistor, at this time, the transistor determines whether to be turned on according to the level of the received pulse width modulation signal; when the pulse width signal received by the second end of the transistor is a high level signal, at this time, the transistor is in a turned-on state (i.e. a conducting state), and the first end of the transistor outputs a low level signal.

[0088] When the pulse width signal received by the second end of the transistor is a low level signal, at this time, the transistor is in an off state (i.e. a non-conducting state), and the first end of the transistor outputs a high level signal.

[0089] Further, the above-mentioned transistor and three resistors form an inverter circuit, which realizes the function of inverting the phase of the received pulse modulation signal.

[0090] In an example, the inverter circuit can also be composed of a PNP type transistor; or can also be composed of a mos tube, and the specific principle can be referred to related technologies, which will not be described here.

[0091] 0In some embodiments, Figure 9 A structure diagram of a second inverter circuit provided by the embodiment of the application is shown in FIG. 6, and the inverter circuit includes: a diode, a second NOT gate module, a seventh resistor and a third capacitor; the anode of the diode is connected with the first output end of the sixth connector; the cathode of the diode is connected with the first end of the seventh resistor, the first end of the third capacitor and the input end of the second NOT gate module respectively; the second end of the seventh resistor and the second end of the third capacitor are connected and then grounded; the power supply end of the second NOT gate module is connected with a power supply; and the output end of the second NOT gate module is connected with the second input end of the sixth connector.

[0092] For example, in the embodiment, the anode of the diode (indicated by D1 in the figure) in the inverter circuit is used to connect the first output end of the sixth connector, for receiving the pulse width modulation signal received by the sixth connector. The cathode of the diode is connected with the first end of the seventh resistor (indicated by R7 in the figure), the first end of the third capacitor (indicated by C3 in the figure) and the input end (indicated by A in the figure) of the second NOT gate module (indicated by U2 in the figure) respectively, and the second end of the seventh resistor and the second end of the third capacitor are connected and then grounded, wherein the third capacitor and the seventh resistor are used to pull the level of the input end of the second NOT gate module low when no signal is output at the cathode of the diode. In addition, the power supply end of the second NOT gate module is connected with a power supply, for receiving the power supply signal output by the power supply, and the output end of the second NOT gate module is connected with the second input end of the sixth connector, for outputting the adjusted signal to the sixth connector.

[0093] When the signal level received at the anode of the diode is high, the signal is transmitted to the input end of the second NOT gate module through the diode, and after being processed by the second NOT gate module (i.e., the signal level is converted to low), the processed signal is transmitted to the sixth connector. When the signal level received at the anode of the diode is low, the diode is cut off, and at this time, the level of the input end of the second NOT gate module is pulled low by the seventh resistor and the third capacitor, and then the second NOT gate module inputs a high level signal. In addition, when the cathode of the diode does not receive a signal, the second NOT gate module also inputs a high level signal.

[0094] It can be understood that in the embodiment, the inverter circuit is formed by setting the diode, the seventh capacitor, the third resistor and the second NOT gate module, so that the subsequent complex programmable logic device can determine whether to be connected to the sixth connector according to whether the phase of the transmitted signal and the returned signal is opposite.

[0095] In some embodiments, Figure 10 A third inverter circuit structure diagram is provided for the embodiment of the application, and based on the device structure shown in Figure 9 The inverter circuit in the embodiment further includes a fourth capacitor and an eighth resistor, wherein the first end of the fourth capacitor is connected to the power supply end of the second NOT gate module and the power supply, respectively, the second end of the fourth capacitor is grounded, the first end of the eighth resistor is connected to the output end of the second NOT gate module, the second end of the eighth resistor is connected to the second input end of the sixth connector, and the output end of the second NOT gate module is connected to the second input end of the sixth connector through the eighth resistor.

[0096] Exemplarily, in the embodiment, Figure 9 Based on the embodiment shown in

[0097] The first end of the fourth capacitor is connected to the power supply end of the second NOT gate module and the power supply, respectively, for filtering the power supply signal output by the power supply, so that the second NOT gate module can receive a stable power supply signal. In addition, the output end of the second NOT gate module can be connected to the second input end of the sixth connector through the eighth resistor, wherein the eighth resistor is used for current limiting to protect the devices in the circuit.

[0098] In some embodiments, the first output end of the sixth connector can also be connected to the anode of the diode in the inverter circuit through a ninth resistor to play a current limiting role.

[0099] In some embodiments, the complex programmable logic device in the mainboard can be connected with the baseboard management controller in the electronic device, so that the baseboard management controller can obtain the determination result of whether the connection of the connector is correct determined by the complex programmable logic device, so as to timely inform the user. In actual application, the complex programmable logic device and the baseboard management controller can communicate in the IIC mode.

[0100] In some embodiments, Figure 11 A seventh structure diagram of a detection circuit for detecting a connector is provided in the embodiment, as shown in the figure, on the basis of the structure diagram shown in Figure 5 On the basis of the structure diagram shown, the mainboard in the embodiment can further include a third connector and a fifth connector, and the subboard can further be provided with a sixth connector, a fourth connector, a third resistor and an inverter circuit. The specific connection relationship can refer to the description in the above embodiments. In actual application, the two pulse width modulation signals sent by the complex programmable logic circuit to the third connector and the fifth connector can be two signals with different duty cycles. The specific principle of the embodiment can refer to the description in the above embodiments, which will not be described here.

[0101] The embodiment provides an electronic device including the detection circuit shown in any one of the above embodiments. In actual application, the electronic device can be a server device.

[0102] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples given are considered exemplary only, and the true scope and spirit of the application is indicated by the appended claims. It will be appreciated by persons skilled in the art that numerous variations and / or modifications can be made to the application as described above without departing from the scope or spirit of the application. It is intended that all such variations and / or modifications be included within the scope of the application. The specification and examples given are considered exemplary only, and the true scope and spirit of the application is indicated by the appended claims.

[0103] It should be understood that the application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A detection circuit for detecting a connector, characterized in that: The detection circuit includes: a main board and a sub-board, The main board is provided with a first connector and a complex programmable logic device; the daughter board includes: a second connector and a self-oscillation signal generating unit; The complex programmable logic device is connected to the first connector, the first connector is connected to the second connector, the second connector is connected to the output end of the self-oscillation signal generating unit; the self-oscillation signal generating unit is connected to a power supply; The self-oscillation signal generating unit is used to generate a pulse signal in a power supply state, and output the pulse signal to the complex programmable logic device in sequence through a second connector on a daughterboard connected to the self-oscillation signal generating unit, a first connector on a mainboard connected to the second connector, and a complex programmable logic device connected to the first connector; the complex programmable logic device is used to determine whether the second connector connected to the first connector is correct based on the received pulse signal and a preset signal corresponding to the first connector; There are multiple first connectors set on the main board; the daughter board includes: second connectors connected to the first connectors in a one-to-one correspondence, and self-excitation signal generation units connected to the second connectors in a one-to-one correspondence; wherein different self-excitation signal generation units generate different pulse signals.

2. The detection circuit according to claim 1, characterized in that The self-oscillation signal generating unit includes: a first NOT gate module, a first resistor and a first capacitor; Among them, the input end of the first NOT gate module is connected to the first end of the first resistor and the first end of the first capacitor respectively; the second end of the first capacitor is grounded; the output end of the first NOT gate module is connected to the second end of the first resistor and the second connector respectively; the power supply end of the first NOT gate module is connected to the power supply.

3. The detection circuit according to claim 2, characterized in that: The self-oscillation signal generating unit further includes: a second resistor and a second capacitor; The first end of the second capacitor is connected to the power supply end of the first NOT gate module and the power supply respectively; the second end of the second capacitor is grounded; The first end of the second resistor is connected to the output end of the first NOT gate module and the second end of the first resistor respectively, and the second end of the second resistor is connected to the second connector; the output end of the first NOT gate module is connected to the second connector through the second resistor.

4. The detection circuit according to claim 1, characterized in that: The main board is provided with a third connector; the daughter board is provided with a fourth connector and a third resistor; The first input end of the third connector and the first output end of the third connector are respectively connected to the complex programmable logic device; the second output end of the third connector is connected to the first input end of the fourth connector; the first output end of the fourth connector is connected to the first end of the third resistor; the second end of the third resistor is connected to the second input end of the fourth connector, and the second output end of the fourth connector is connected to the second input end of the third connector; The complex programmable logic device is used to send a pulse width modulated signal to the fourth connector through the third connector, and the fourth connector is used to return the pulse width modulated signal received by the second connector to the complex programmable logic device through the third connector; The complex programmable logic device is further configured to determine whether a fourth connector connected to the third connector is correct based on a pulse modulation signal sent by the third connector and a pulse width modulation signal returned by the third connector.

5. The detection circuit according to claim 1, characterized in that: The main board is provided with a fifth connector; the sub-board is provided with a sixth connector and an inverter circuit; The first input end of the fifth connector and the first output end of the fifth connector are respectively connected to the complex programmable logic device; the second output end of the fifth connector and the first input end of the sixth connector are respectively connected to the complex programmable logic device; the first output end of the sixth connector is connected to the input end of the inverter circuit, the output end of the inverter circuit is connected to the second input end of the sixth connector, and the second output end of the sixth connector is connected to the second input end of the fifth connector; The complex programmable logic device is used to send a pulse width modulated signal to the sixth connector through the fifth connector, and the inverter circuit is used to invert the phase of the pulse width modulated signal and send the processed signal to the complex programmable logic device through the sixth connector and the fifth connector; The complex programmable logic device is further configured to determine whether the sixth connector connected to the fifth connector is correct based on the pulse modulation signal sent by the fifth connector and the pulse width modulation signal returned by the fifth connector.

6. The detection circuit according to claim 5, characterized in that: The inverter circuit includes: a transistor, a fourth resistor, a fifth resistor and a sixth resistor; The first end of the transistor is connected to the first end of the fourth resistor and the second input end of the sixth connector respectively; the second end of the fourth resistor is connected to the power supply; The second end of the transistor is connected to the first end of the fifth resistor and the first end of the sixth resistor respectively; the third end of the transistor is connected to the second end of the fifth resistor and then grounded; the second end of the sixth resistor is connected to the first output end of the sixth connector.

7. The detection circuit according to claim 5, characterized in that: The inverter circuit includes: a diode, a second NOT gate module, a seventh resistor and a third capacitor; The anode of the diode is connected to the first output end of the sixth connector; the cathode of the diode is respectively connected to the first end of the seventh resistor, the first end of the third capacitor and the input end of the second NOT gate module; the second end of the seventh resistor and the second end of the third capacitor are connected and then grounded; the power supply end of the second NOT gate module is connected to the power supply; and the output end of the second NOT gate module is connected to the second input end of the sixth connector.

8. The detection circuit according to claim 7, characterized in that: The inverter circuit further includes: a fourth capacitor and an eighth resistor; Wherein, the first end of the fourth capacitor is connected to the power supply end of the second NOT gate module and the power supply respectively; the second end of the fourth capacitor is grounded; The first end of the eighth resistor is connected to the output end of the second NOT gate module; the second end of the eighth resistor is connected to the second input end of the sixth connector; the output end of the second NOT gate module is connected to the second input end of the sixth connector through the eighth resistor.

9. An electronic device, characterized in that: The method comprises the detection circuit according to any one of claims 1 to 8.

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