Silicon Carbide Metal Oxide Semiconductor Gate Type Semiconductor Device

Abstract

The present invention provides a silicon carbide metal oxide semiconductor gate type semiconductor device. The silicon carbide metal oxide semiconductor gate type semiconductor device includes: a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, and a metal layer. The first doped region includes a plurality of base portions, a plurality of first extension portions, and a plurality of first connection portions, and these base portions and these first connection portions extend along the first horizontal direction and are alternately arranged between these first extension portions. A plurality of channel regions are defined between the second doped region and the first doped region. The gate electrode includes a gate bus region and an active region, and the minimum gate width Wg of the plurality of gate electrode openings in the active region satisfies the following formula: Wg > Wjfet + 2 × Lch + 2 × Lx.

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide metal oxide semiconductor gated (MOS-gated) semiconductor device. Background Art

[0002] Silicon Carbide (SiC) is an emerging power semiconductor material. Due to its wide bandgap, SiC has superior performance compared to traditional silicon power devices, including high dielectric strength to electric field and low intrinsic carrier concentration.

[0003] The high dielectric strength of SiC makes the on-resistance of the theoretical unipolar characteristics of the drift layer much lower than the limit of silicon, while the low intrinsic carrier concentration enables SiC power devices to operate stably at high temperatures.

[0004] To meet the requirements of electromagnetic interference (EMI) specifications for power supplies, an external gate resistor with a relatively high external gate resistance value (Rg,ext) is usually connected to the gate of a silicon-based super-junction MOSFET (SJ-MOSFET) to suppress the oscillation of the gate voltage (Vg) and drain-source voltage (Vds) caused by a high voltage change rate (dV / dt) during switching transients. Since SiC metal oxide semiconductor field effect transistors (SiC MOSFETs) are wide bandgap semiconductors, they can provide the same on-resistance effect on a smaller-sized wafer. For example, under the condition of the same on-resistance, the wafer size of a 650V SiC MOSFET can be reduced to 1 / 4 to 1 / 20 of that of a silicon-based SJ-MOSFET. The internal gate resistance value (Rg,int) is the equivalent series resistance (ESR) of the MOSFET gate and is usually inversely proportional to the wafer size of the MOSFET, that is, the smaller the wafer size, the larger the internal gate resistance value (Rg,int). Accordingly, the internal gate resistance value (Rg,int) of SiC MOSFETs is usually higher than that of silicon-based SJ-MOSFETs with similar on-resistance. Since the peak value of the voltage change rate (dV / dt) of SiC MOSFETs during switching transients is much lower than that of silicon-based SJ-MOSFETs with the same switching loss, an external gate resistor with a small or zero resistance value can be used without worrying about the EMI performance. Based on the switching loss P of the MOSFET sw Follows the following formula:

[0005] P sw ∝(Rg,ext + Rg,int)

[0006] A relatively high internal gate resistance value (Rg,int) may limit to a certain extent the optimal performance that a SiC MOSFET can achieve.

[0007] At the same time, for some devices with relatively low switching frequencies that require multiple MOSFETs to be connected in parallel to achieve higher power levels, a relatively high internal gate resistance value (Rg,int) may be required to minimize unbalanced switching between MOSFETs. Therefore, a simpler and more economical way is needed to reduce or adjust the internal gate resistance value (Rg,int) according to device requirements. SUMMARY OF THE INVENTION

[0008] The object of the present invention is to improve the performance of conventional silicon carbide semiconductor devices.

[0009] To achieve the above object, the present invention provides a silicon carbide metal-oxide-semiconductor gate (MOS-gated) semiconductor device, comprising: a silicon carbide substrate; a drift layer disposed on the silicon carbide substrate, the drift layer having a first conductivity type and including a main surface; a first doped region disposed in the drift layer, the first doped region having a second conductivity type opposite to the first conductivity type, wherein the first doped region and the drift layer form a plurality of first p-n junctions and a plurality of junction gate field-effect transistor (JFET) regions, the first doped region includes a plurality of base portions, a plurality of first extension portions, and a plurality of first connection portions, the first extension portions extend along a second horizontal direction and are arranged side by side with intervals therebetween, the base portions and the first connection portions extend along the first horizontal direction and are alternately arranged between the first extension portions; a second doped region disposed in the first doped region, the second doped region having the first conductivity type, and the second doped region and the first doped region form a plurality of second p-n junctions, wherein a plurality of channel regions are defined between the second doped region and the first doped region along the main surface; a plurality of third doped regions disposed in the base portions of the first doped region, the third doped regions having the second conductivity type, and the third doped regions are surrounded by the second doped region; a gate insulating layer formed on the main surface; a gate electrode formed on the gate insulating layer, including a gate bus region and an active region, wherein the active region of the gate electrode includes a plurality of gate electrode openings, and a minimum gate width (W g ) satisfies the following formula:

[0010] W g >W jfet +2×L ch +2×Lx

[0011] Among them, L ch is a channel length of these channel regions, and W jfet is a minimum width of these JFET regions, and L x is a minimum overlap length between the gate electrode and the second doped region; an interlayer dielectric layer formed on the gate electrode; and a metal layer formed on the interlayer dielectric layer, including a first part and a second part that are electrically isolated from each other. The first part is disposed above the active region of the gate electrode, and the second part is disposed above the gate bus region of the gate electrode. Among them, the first part is electrically coupled to the third doped region and the second doped region through a plurality of source contacts formed by penetrating the gate electrode openings, and the second part is electrically coupled to the gate electrode through a gate contact. Description of the Drawings

[0012] Figure 1A is a top view schematic diagram of a silicon carbide MOS-gated semiconductor device according to an embodiment of the present invention.

[0013] Figure 1B is Figure 1A a partial enlarged schematic diagram of

[0014] Figure 1C is Figure 1B a partial enlarged schematic diagram of

[0015] Figure 2A is a cross-sectional perspective view of a silicon carbide MOS-gated semiconductor device according to an embodiment of the present invention.

[0016] Figure 2B is a top view schematic diagram of the gate electrode and the gate electrode opening.

[0017] Figure 2C is a top view schematic diagram of the first doped region in the drift layer.

[0018] Figure 2D is a top view schematic diagram of the second doped region and the third doped region in the first doped region.

[0019] Figures 3 to 9 are schematic diagrams of silicon carbide MOS-gated semiconductor devices according to different embodiments of the present invention.

[0020] Figure 10 is a top view of a silicon carbide MOS-gated semiconductor device according to an embodiment of the present invention. Detailed Description of the Invention

[0021] The following disclosure and drawings provide details regarding embodiments or examples of the present invention. The following detailed description provides many different embodiments or examples for implementing different features of the present case. However, these specific examples are not intended to limit that these embodiments must have the specific details described herein to be practiced.

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the present case. Of course, these specific examples are not intended to limit. For example, if an embodiment of the present invention describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the above first characteristic component and the above second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the above first characteristic component and the above second characteristic component, so that the above first characteristic component and the second characteristic component may not be in direct contact. In addition, the same reference signs and / or labels may be reused in the different embodiments disclosed below. These repetitions are for the purpose of simplicity and clarity and are not intended to limit a specific relationship between the different embodiments and / or structures discussed.

[0023] In addition, spatially relative terms such as "above", "below", "lower", and similar terms may be used herein. These spatially relative terms are for the purpose of facilitating the description of the relationship between one or more elements or characteristic components in the drawings and another or more elements or characteristic components. In addition to the orientation relationships depicted in the drawings, these spatially relative terms encompass different orientations of the device in use or operation. The device may be positioned in other ways, and the same spatially relative terms may be used accordingly to interpret.

[0024] In this document, the terms used in the description of various embodiments are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, or the number of elements is deliberately limited, the singular forms "a", "an", and "the" used herein also include the plural forms. It should also be understood that although the terms "first", "second", etc. are used to describe various elements in this document in certain cases, these elements are not limited by these terms, and these terms are only used to distinguish different elements.

[0025] Although some embodiments perform steps in a specific order, these steps can still be performed in another reasonable order. For different embodiments, some of the features described below can be replaced or eliminated. It should be understood that some additional operations can be performed before, during, or after the described method, and in other embodiments of the method, certain operations can be replaced or omitted.

[0026] Figure 1A and Figure 1BA top view of a gate electrode in a silicon carbide metal oxide semiconductor gated (MOS-gated) semiconductor device according to an embodiment of the present invention. The gate electrode includes a gate bus region 10 and an active region 20. In Figure 1A In the illustrated embodiment, the gate bus region 10 includes only a gate pad region disposed in a central region 21 of the active region 20. The gate pad region has four side edges 10a, 10b, 10c, 10d adjacent to the active region 20. The active region 20 includes a plurality of gate electrode openings 201 formed therein. As Figure 1B shown, the active region 20 can be divided into a plurality of repeating unit cells 20a arranged in sequence. The repeating unit cells 20a are arranged in repetition along a first horizontal direction X to form a plurality of rows (R1 to R6 as shown in the figure), and adjacent rows are staggered along a second horizontal direction Y, wherein adjacent unit cells 20a are alternately displaced by a displacement D. In one embodiment, the displacement D is half of the length (pitch) of the unit cells 20a.

[0027] Figure 1C Corresponding to Figure 1B is a partially enlarged top view of the active region 20 in

[0028] and is a perspective view from the top surface of a drift layer. In this embodiment, the drift layer corresponding to the active region 20 of the silicon carbide MOS-gated semiconductor device includes a first doped region 203, a second doped region 204, and a plurality of third doped regions 205 formed above the drift layer. The drift layer and the second doped region 204 have a first conductivity type, and the first doped region 203 and the third doped regions 205 have a second conductivity type, which is opposite to the first conductivity type.

[0028] Please refer to Figure 1C and Figure 2A Figure 2A is a cross-sectional perspective view of the silicon carbide MOS-gated semiconductor device of the present invention. This is a structural schematic diagram that only partially illustrates the structure of the silicon carbide MOS-gated semiconductor device. The silicon carbide MOS-gated semiconductor device includes a substrate 30, a drift layer 40, a first doped region 203, a second doped region 204, a plurality of third doped regions 205, a gate insulating layer 50, a gate electrode layer 51, an interlayer dielectric layer 52, and a metal layer 53. The substrate 30 is a silicon carbide substrate with n-type heavy doping (n+). The drift layer 40 is n-type lightly doped (n-) formed on the substrate 30. In this embodiment, the first conductivity type is n-type lightly doped (n-), and the second conductivity type is p-type.

[0029] The first doped region 203 is formed in the drift layer 40 adjacent to a main surface 41, and is formed, for example, by implanting aluminum ions into a nitrogen-doped n-type SiC drift layer.

[0030] The second doped region 204 is formed in the first doped region 203. The formation method is, for example, implanting a high dose of phosphorus ions into the drift layer 40, and forming a plurality of p-n junctions with the p-type first doped region 203, so that the second doped region 204 is surrounded by the first doped region 203 in the upper region adjacent to the main surface 41.

[0031] The third doped region 205 is formed, for example, by implanting a high dose of aluminum ions into the drift layer 40, so that the third doped region 205 is adjacent to a source portion 2041a of the second doped region 204 and contacts the first doped region 203.

[0032] The gate insulating layer 50 is formed on the main surface 41 of the drift layer 40. The formation method is, for example, through thermal oxidation of silicon carbide or deposition of silicon dioxide, and then annealing in an environment with a nitrogen-containing gas, and the nitrogen-containing gas includes but is not limited to nitrogen (N2), nitric oxide (NO), and / or nitrogen dioxide (N2O). The gate electrode layer 51 is formed above the gate insulating layer 50. The gate insulating layer 50 includes a first portion 501 and a second portion 502. The first portion 501 is located below the gate bus region 10 of the gate electrode layer 51 and has a first thickness, and the second portion 502 is located below the active region 20 of the gate electrode layer 51 and has a second thickness, and the second thickness is less than the first thickness.

[0033] Please refer to Figure 2B , for Figure 1B a schematic diagram of one unit cell 20a in , illustrating the gate electrode layer 51 and the gate electrode opening 201. The material of the gate electrode layer 51 is, for example, degenerate n-type or p-type poly-silicon that provides low thin film resistance, and is formed on the gate insulating layer 50 through deposition, and a part of the gate electrode layer 51 forms the gate electrode opening 201 through dry etching. After forming the gate electrode opening 201, the interlayer dielectric layer 52 is deposited to form isolation between the gate insulating layer 50 and the metal layer 53. The material of the interlayer dielectric layer 52 includes borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon dioxide (SiO2), tetraethylorthosilicate, silicon nitride (Six N y ) or the like. A plurality of source contacts 54 are provided in the gate electrode opening 201. These source contacts 54 are etched through the interlayer dielectric layer 52 and the gate insulating layer 50 to expose a part of the third doped region 205 and the second doped region 204. By removing a part of the drift layer 40, an ohmic contact layer (not shown), such as a nickel silicide (Ni x Si y ) layer, is formed in the third doped region 205 and a part of the second doped region 204.

[0034] Please refer to Figure 2A , at least one gate contact 55 is formed after these source contacts 54. The metal layer 53 is deposited on the interlayer dielectric layer 52 and fills into these source contacts 54 and the gate contact 55. For example, the metal layer 53 is a metal layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD), including AlCu, AlSiCu, Al, Ti, TiN, TiW, etc. A first part 531 and a second part 532 of the metal layer 53 are separated by dry etching, wet etching, or a combination of dry etching and wet etching, and then a dielectric layer (not shown) including silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si x N y ) is filled into the gap between the first part 531 and the second part 532 of the metal layer 53 to isolate the first part 531 and the second part 532. The first part 531 of the metal layer 53 is defined above the active region 20 of the gate electrode layer 51, but is isolated from the gate electrode layer 51 due to the setting of the interlayer dielectric layer 52. The first part 531 is electrically coupled to the third doped region 205 and the second doped region 204 through these source contacts 54. The second part 531 of the metal layer 53 is defined above the gate bus region 10 of the gate electrode layer 51 and is electrically coupled to the gate electrode layer 51 through the gate contact 55.

[0035] In an embodiment, the gate bus region 10 of the gate electrode layer 51 includes a gate pad region, and the second part 532 of the metal layer 53 is disposed above the gate pad region and electrically coupled to the gate electrode layer 51 (not shown), wherein the shape of the second part 532 is a rounded rectangle or a circle.

[0036] In another embodiment, the gate bus region 10 of the gate electrode layer 51 includes a gate pad region and a plurality of gate runner regions, and the second portion 532 of the metal layer 53 is disposed above the gate pad region and the gate runner regions, and is electrically coupled to the gate electrode layer 51 to reduce the gate resistance (not shown in the figure).

[0037] Refer to Figure 2A and Figure 2C , wherein Figure 2C shows the first doped region 203 of one of the unit cells 20a. The first doped region 203 includes a plurality of base portions 2031, a plurality of first extension portions 2032, and a plurality of first connection portions 2033. The base portions 2031, the first extension portions 2032, and the first connection portions 2033 are connected to each other to form a kind of network structure in the drift layer 40. The first extension portions 2032 extend along the second horizontal direction Y. In addition, the first extension portions 2032 are arranged side by side and spaced apart from each other. The base portions 2031 and the first connection portions 2033 extend along the first horizontal direction X and are alternately arranged between any two of the first extension portions 2032. In one embodiment, some of the base portions 2031 and the first connection portions 2033 extend along the first horizontal direction X to form a plurality of two-dimensionally connected H-shaped structures. A plurality of junction gate field-effect transistor (JFET) regions 206 are formed between any two of the first extension portions 2032. After the second doped region 204 is formed in the first doped region 203, a plurality of channel regions 207 are formed between a first p-n junction and a second p-n junction adjacent to the main surface 41, wherein the first p-n junction is formed by the first doped region 203 and the second doped region 204, and the second p-n junction is formed by the first doped region 203 and the drift layer 40, as Figure 1C and Figure 2D shown.

[0038] Please refer to Figure 2A and Figure 2D , the second doped region 204 includes a plurality of source portions 2041, a plurality of second extension regions 2042, and a plurality of second connection portions 2043. The second extension regions 2042 and the second connection portions 2043 are respectively formed in the first extension portions 2032 and the first connection portions 2033. The source portions 2041 are formed in the base portions 2031. The second doped region 204 is formed in the first doped region 203 in the manner Figure 2A shown, so that the first doped region 203 is partially located below the second doped region 204 and partially extends adjacent to the main surface 41 of the drift layer 40.

[0039] When viewed from above, each of the source portions 2041 is located at the center position of one of the unit cells 20a. Similar to the layout of the first doped region 203, the source portions 2041 and the second connection portions 2043 extend along the first horizontal direction X and are alternately arranged between any two second extension portions 2042. In one embodiment, some of the source portions 2041 and the second connection portions 2043 extend along the first horizontal direction X to form a plurality of two-dimensionally connected H-shaped structures.

[0040] Each of the third doped regions 205 is formed at the center position of one of the unit cells 20a, and the center position is adjacent to the source portions 2041 of the second doped region 204 and contacts the first doped region 203.

[0041] Refer back to Figure 1B 、 Figure 1C 、 Figure 2A and Figure 2D , in the present invention, two adjacent gate electrode openings 201 are spaced apart by a minimum gate width (W g ), and the minimum width (W g ) follows (or satisfies) the following formula:

[0042] W g >W jfet +2×L ch +2×L x

[0043] L ch is a channel length of the channel regions 207, W jfet is a minimum width of the JFET regions 206, and L x is a minimum overlap length of the gate electrode layer 51 and the second doped region 204. Since the minimum gate width in the present invention is greater than the minimum gate width of the conventional structure (equivalent to W jfet +2×L ch +2×L x), so a relatively low internal gate resistance can be achieved. For example, the silicon carbide MOS-gated semiconductor device of the present invention can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the internal gate resistance of the MOSFET is 5 ohms, while the internal gate resistance of a silicon carbide MOSFET with a conventional structure is 26 ohms under the same wafer size. The silicon carbide MOSFET according to another embodiment of the present invention has a size only about half of that of the conventional structure, and the internal gate resistance is 10 ohms, which is still significantly lower than the internal gate resistance of the silicon carbide MOSFET with the conventional structure. Therefore, the silicon carbide MOS-gated semiconductor device of the present invention has the advantages of reducing switching loss and increasing switching speed. The silicon carbide MOS-gated semiconductor device of the present invention can also be an Insulated Gate Bipolar Transistor (IGBT).

[0044] According to an embodiment of the present invention, the gate bus region 10 only includes one gate pad region, and the gate resistance of the silicon carbide MOS-gated semiconductor device can be adjusted based on the position of the gate pad region relative to the active region 20.

[0045] In Figure 1A the illustrated embodiment, the gate pad region is surrounded by the active region 20, and the four sides 10a, 10b, 10c, 10d of the gate pad region are connected to the active region 20. Figures 3 to 9 are different embodiments of the silicon carbide MOS-gated semiconductor device of the present invention. In Figure 3 the illustrated embodiment, the gate pad region 10' is disposed along an edge 22, and three sides 10a, 10b, 10d of the gate pad region 10' are connected to the active region 20. In Figure 4 the illustrated embodiment, the gate pad region 10' is disposed along a corner 23, and two sides 10a, 10d of the gate pad region 10' are connected to the active region 20. In Figure 1A , Figure 3 and Figure 4 the silicon carbide MOS-gated semiconductor devices in have a first gate resistance, a second gate resistance, and a third gate resistance respectively. The first gate resistance is lower than the second gate resistance, and the second gate resistance is lower than the third gate resistance. For example, the gate resistance of a silicon carbide MOSFET having the gate pad region 10' arranged as shown in Figure 1A is 5 ohms, and a silicon carbide MOSFET having the gate pad region 10' arranged as shown in Figure 4The gate resistance of the silicon carbide MOSFET with the gate pad region 10' set as shown is 15 ohms. However, the areas of the active regions 20 of the above two silicon carbide MOSFETs are exactly the same.

[0046] In Figure 5 Another embodiment as shown, the gate bus region 10 is disposed in the central region 21 of the active region 20, and the gate bus region 10 includes a gate pad region 10' and a gate runner region 11. The gate runner region 11 extends from the gate pad region 10' along the first horizontal direction X. The gate runner region 11 is used to further reduce the gate resistance, but it requires a larger wafer area and more cost. In Figure 6 Another embodiment as shown, the gate bus region 10 is disposed in the central region 21 of the active region 20, and the gate bus region 10 includes a gate pad region 10' and four gate runner regions 11a, 11b, 11c, 11d. In Figure 7 Another embodiment as shown, the gate bus region 10 is disposed in the central region 21 of the active region 20, and the gate bus region 10 includes a gate pad region 10' and a gate runner region 11. The gate runner region 11 extends from the gate pad region 10' along the second horizontal direction Y. In Figure 8 Another embodiment as shown, the gate bus region 10 is disposed in the central region 21 of the active region 20, and the gate bus region 10 includes a gate pad region 10' and a gate runner region 11. The gate runner region 11 is disposed around the active region 20. The gate runner region 11 can be disposed in a peripheral region of the silicon carbide MOS-gated semiconductor device. The peripheral region corresponds to the terminal region of the silicon carbide MOS-gated semiconductor device and is outside the active region 20. Thus, the active region 20 does not need to sacrifice its area to dispose the gate runner region 11, thereby minimizing the impact of disposing the gate runner region 11 on the total size of the crystal plane area and cost. In Figure 9 Another embodiment as shown, the gate bus region 10 includes more than one gate pad region 10', and three gate pad regions 101, 102, 103 are distributed in the central region 21 of the active region 20.

[0047] Figure 10 This is the silicon carbide MOS-gated semiconductor device according to an embodiment of the present invention. In an alternative embodiment, the repeated unit cells 20a can be arranged in repetition along the second horizontal direction Y to form multiple columns (C1 to C11 in the figure), and adjacent columns are staggered with each other, wherein any two adjacent unit cells 20a are arranged with a displacement in an alternating and misaligned manner.

Claims

1. A silicon carbide metal oxide semiconductor gate type semiconductor device, characterized in that, Comprising: A silicon carbide substrate; A drift layer disposed on the silicon carbide substrate, the drift layer having a first conductivity type and including a main surface; A first doped region disposed in the drift layer, the first doped region having a second conductivity type opposite to the first conductivity type. Wherein, the first doped region and the drift layer form a plurality of first p-n junctions and a plurality of junction field effect transistor regions. The first doped region includes a plurality of base portions, a plurality of first extension portions, and a plurality of first connection portions. These first extension portions extend in a second horizontal direction and are arranged side by side and spaced apart from each other. These base portions and these first connection portions extend in a first horizontal direction and are alternately arranged between these first extension portions; A second doped region disposed in the first doped region, the second doped region having the first conductivity type, and the second doped region and the first doped region form a plurality of second p-n junctions. Wherein, a plurality of channel regions are defined between the second doped region and the first doped region along the main surface; A plurality of third doped regions disposed in these base portions of the first doped region, these third doped regions having the second conductivity type, and these third doped regions are surrounded by the second doped region; A gate insulating layer formed on the main surface; The gate electrode, formed on the gate insulating layer, includes a gate bus region and an active region. Wherein, the active region of the gate electrode includes a plurality of gate electrode openings, and the minimum gate width W between two adjacent gate electrode openings g Satisfies the following formula: W g >W jfet +2×L ch +2×L x Among them, L ch is the channel length of these channel regions, and W jfet is the minimum width of these junction field effect transistor regions, and L x is the minimum overlap length between the gate electrode and the second doped region; An interlayer dielectric layer formed on the gate electrode: and A metal layer formed on the interlayer dielectric layer, including a first part and a second part that are electrically isolated from each other. The first part is disposed above the active region of the gate electrode, and the second part is disposed above the gate bus region of the gate electrode. Wherein, the first part is electrically coupled to the third doped region and the second doped region through a plurality of source contacts formed by penetrating these gate electrode openings, and the second part is electrically coupled to the gate electrode through a gate contact.

2. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 1, wherein The active region is divided into a plurality of repeating unit cells on the main surface, and each of the unit cells includes at least one gate electrode opening.

3. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 2, wherein These unit cells are repeatedly arranged in the first horizontal direction to form a plurality of rows, adjacent rows are staggered, and the unit cells of adjacent rows are alternately displaced.

4. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 2, characterized in that, These unit cells are repeatedly arranged in the second horizontal direction to form a plurality of columns, adjacent columns are staggered, and the unit cells of adjacent columns are alternately displaced.

5. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 1, characterized in that, The gate bus region of the gate electrode includes a gate pad region, and the gate resistance of the silicon carbide metal oxide semiconductor gate type semiconductor device is adjusted based on the position of the gate pad region relative to the active region.

6. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 1, characterized in that, The gate bus region of the gate electrode includes a plurality of gate pad regions, and the gate resistance of the silicon carbide metal oxide semiconductor gate type semiconductor device is adjusted based on the number of these gate pad regions and their positions relative to the active region.

7. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 6, wherein, The second part of the metal layer disposed above these gate pad regions is a rounded rectangle or a circle.

8. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 1, wherein The gate bus region of the gate electrode includes a gate pad region and a plurality of gate runner regions extending from the gate pad region.

9. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 8, wherein, The active region is completely surrounded by the gate pad region and these gate runner regions.

10. The silicon carbide metal oxide semiconductor gate type semiconductor device according to claim 1, wherein The silicon carbide metal oxide semiconductor gate type semiconductor device is a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

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