Cutting of silicon carbide semiconductor wafers

Abstract

The present invention relates to dicing of silicon carbide semiconductor wafers. A method of dicing a silicon carbide (SiC) semiconductor wafer can include defining a kerf within the silicon carbide (SiC) semiconductor wafer by performing a partial scribe operation, where the SiC semiconductor wafer is aligned along a plane and the kerf has a depth that is less than a first thickness of the SiC semiconductor wafer. The kerf is aligned along a vertical direction that is orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the kerf and an outer surface of the SiC semiconductor wafer. The method can also include defining a split by performing a cleave operation through the portion of the SiC semiconductor wafer having the second thickness. The split can be aligned with the kerf and extend to the outer surface of the SiC semiconductor wafer.

Description

[0001] This divisional application is a divisional application based on the Chinese patent application with application number 201910381948.9, application date May 9, 2019, and invention name “Cutting of Silicon Carbide Semiconductor Wafers”. Technical Field

[0002] This description relates to the dicing of dies from silicon carbide (SiC) semiconductor wafers. Background Art

[0003] Dicing is the process of reducing a semiconductor wafer containing multiple integrated circuit dies to form individual semiconductor chips. For example, dicing semiconductor dies from a silicon wafer can be performed using a water-cooled saw with diamond teeth. Alternatively, dicing can be performed using a laser ablation tool. Summary of the Invention

[0004] In one general aspect, a method for cutting a silicon carbide (SiC) semiconductor wafer may include defining a kerf within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation, wherein the SiC semiconductor wafer is aligned along a plane and the kerf has a depth less than a first thickness of the SiC semiconductor wafer. The kerf is aligned along a vertical direction orthogonal to the plane so that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the kerf and an outer surface of the SiC semiconductor wafer. The method may also include performing a cleaving operation through the portion of the SiC semiconductor wafer having the second thickness to define a cleave. The cleave may be aligned with the kerf and extend to the outer surface of the SiC semiconductor wafer.

[0005] In another general aspect, a system may include a wafer chuck configured to receive a SiC semiconductor wafer thinned to a first thickness, the thinned SiC semiconductor wafer having a surface aligned along a plane. The system may also include a dicing device configured to perform a partial dicing operation on the SiC semiconductor wafer to define a kerf in the SiC semiconductor wafer, the kerf having a depth less than the first thickness of the SiC semiconductor wafer, the kerf aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the kerf and an outer surface of the SiC semiconductor wafer. The system may also include a cracking device configured to perform a cleaving operation along a vertical direction through the portion of the SiC semiconductor wafer having the second thickness to define a rift aligned with the kerf and extending to the outer surface of the SiC semiconductor wafer.

[0006] In another general aspect, a method may include thinning a silicon carbide (SiC) semiconductor wafer to a thickness, the thinned SiC semiconductor wafer having a surface aligned along a plane. The method may also include performing a partial scribing operation on the SiC semiconductor wafer to define a cut in the SiC semiconductor wafer through a first portion of the thickness of the SiC semiconductor wafer, the cut aligned along a vertical direction orthogonal to the plane, such that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the cut and an outer surface of the SiC semiconductor wafer, the cut also having a first width in a direction parallel to the plane. The method may also include performing a cleaving operation to define a rift having a second width less than the first width, the rift aligned with the vertical rift and passing through the second portion of the thickness of the SiC semiconductor wafer.

[0007] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic diagram illustrating an exemplary method for dicing a silicon carbide (SiC) semiconductor wafer into dies.

[0009] Figure 1B and Figure 1C is shown with Figure 1A Schematic diagram of a portion of a SiC semiconductor wafer corresponding to the illustrated method.

[0010] Figure 2A is a schematic diagram illustrating a cross-sectional view of an exemplary SiC semiconductor wafer after being thinned to a target thickness for dicing.

[0011] Figure 2B is a schematic diagram showing a cross-sectional view of a SiC semiconductor wafer after back metal deposition.

[0012] Figure 2C is a schematic diagram showing a cross-sectional view of a SiC semiconductor wafer after a partial dicing operation.

[0013] Figure 2D is a schematic diagram showing a cross-sectional view of a SiC semiconductor wafer after a cleaving operation.

[0014] Figure 2E is a schematic diagram illustrating a cross-sectional view of a portion of an exemplary die of a SiC semiconductor wafer after a cleaving operation.

[0015] Figure 3A is a schematic diagram illustrating an exemplary cutting apparatus for cutting a SiC semiconductor wafer through a first portion of the thickness of the SiC semiconductor wafer.

[0016] Figure 3B is a schematic diagram illustrating an exemplary cleaving apparatus for cleaving a SiC semiconductor wafer through a second portion of the thickness of the SiC semiconductor wafer.

[0017] Figure 4A is a schematic diagram illustrating an exemplary sawing and cleaving of a SiC semiconductor wafer.

[0018] Figure 4B is a schematic diagram of a line drawing showing a scanning electron microscope (SEM) picture of an exemplary cut and cleaved SiC semiconductor wafer.

[0019] Figure 5 is a flow chart illustrating an exemplary method of dicing a SiC semiconductor wafer into die according to the improved techniques described herein. DETAILED DESCRIPTION

[0020] Embodiments described herein relate to methods and apparatus for slicing semiconductor die from a silicon carbide (SiC) semiconductor wafer in a desired manner. For example, the slicing apparatus and method described herein can slicing semiconductor die from a SiC semiconductor wafer with a vertical sidewall cut profile that extends through the thickness of the SiC semiconductor wafer. The SiC semiconductor wafer may be referred to as a SiC wafer.

[0021] The dicing techniques described herein may include defining a kerf in a SiC wafer using a cutting device and then cleaving the SiC wafer using a cleaving device. The kerf may be defined through only a portion of the thickness of the SiC semiconductor wafer (to a specified depth that is less than the entire thickness of the SiC semiconductor wafer), and the cleaving may be performed through the remaining thickness of the SiC semiconductor wafer.

[0022] SiC devices have some advantages over traditional Si devices. For example, the band gap of SiC is about three times that of Si, and it can withstand much higher voltages and temperatures than Si-based devices. For example, a SiC-based device with the same size as a Si-based device can withstand an electric field strength that is about 10 times that of a SiC-based device. Despite these advantages, the manufacturing technology applied to SiC wafers cannot be applied to SiC wafers in the same way because SiC wafers have different properties from Si wafers (for example, they have a different crystal structure and are a harder material). In view of the unique properties of SiC wafers, the improved methods and devices described herein relate to the processing of SiC wafers.

[0023] Figure 1A is a schematic diagram illustrating an exemplary method of cutting a SiC semiconductor wafer into dies. Figure 1B and Figure 1C is shown with Figure 1A A schematic diagram of a portion of a SiC wafer 130 corresponding to the illustrated method.

[0024] like Figure 1A As shown, at block 110, a cut is defined in the SiC semiconductor wafer through a portion of the SiC semiconductor wafer. Figure 1B As shown, the SiC semiconductor wafer 130 has a cutout C1 defined by a cutting device through a portion of the thickness A1. The depth of the portion of the thickness A1 is Figure 1B Indicated as A2. Figure 1B As shown, depth A2 is a fraction of thickness A1. Cutting a SiC wafer through the entire thickness A1 can result in undesirable wear on the cutting equipment.

[0025] Also like Figure 1A As shown in FIG, at block 120, the SiC wafer is cleaved along the cuts through the remaining thickness of the SiC wafer. Figure 1C As shown, in addition to cutting along the cut C1, the SiC semiconductor wafer 130 is also cleaved along the crack C2. The crack C2 is added to the SiC semiconductor wafer 130 using a cleaving device. The depth of the remaining portion of the thickness A1 is Figure 1C In this case, the dicing of the SiC semiconductor wafer 130 is a combination of a cutting operation to produce a cut C1 and a cleaving operation to produce a crack C2.

[0026] like Figure 1C As shown, cleavage C2 is aligned with notch C1 along a vertical axis. Notch C1 and cleavage C2 are defined so that achieving this alignment is not noticeable in the SiC semiconductor wafer. The cleaving operation performed in conjunction with the cutting operation results in undesirable vertical separation within the SiC semiconductor wafer. Methods and apparatus for achieving this alignment of notch C1 and cleavage C2 in a SiC semiconductor wafer are further shown and described below.

[0027] Advantageously, the improved techniques (cutting and cleaving) reduce wear and tear on equipment used during the dicing process. Since SiC is a hard material (harder than silicon), cutting through a portion of the thickness of a thinned (e.g., ground) wafer rather than the entire thickness can have the advantage of extending the life of the cutting equipment used in the dicing process. Extending the life of the cutting equipment can reduce the overall cost of manufacturing dies from SiC wafers.

[0028] Figures 2A to 2D is a schematic diagram illustrating a process of cutting a SiC semiconductor wafer into semiconductor dies. Figures 2A to 2D Shows the combination Figures 1A to 1C More details of the method shown and described.

[0029] Figure 2A The SiC semiconductor wafer is thinned (eg, ground) to a certain thickness. Figure 2B shows the back metal deposition, Figure 2C It is shown that cutting a SiC wafer is to cut a portion of the thickness using a cutting tool, and Figure 2D The cleavage of a SiC wafer cleavage tool is shown. Figures 2A-2D The processes shown are shown in the order in which they are performed. In some embodiments, Figures 2A-2D The processes shown may be performed in a different order. For example, in some embodiments, Figure 2B The back metal deposition operation shown can be performed at Figure 2C After the cutting operation shown but Figure 2D The indicated lysis operations were performed before.

[0030] Figure 2A is a schematic diagram illustrating an exemplary SiC semiconductor wafer 200 after the SiC semiconductor wafer 200 is ground to a specified thickness. Figure 2A 1 shows a SiC semiconductor wafer 200 as it is positioned in a coordinate system, where x represents the horizontal direction (i.e., parallel to the surface 202 of the SiC semiconductor wafer 200 ) and y represents the vertical direction (i.e., perpendicular to the surface 202 and in the direction of the thickness A1 of the wafer 200 ). Figure 2A In the illustrated embodiment, SiC semiconductor wafer 200 is disposed on chuck 206 while SiC wafer 200 is thinned. During the thinning (eg, grinding) process, at least some portion of SiC wafer 200 is removed to reduce the thickness of SiC wafer 200.

[0031] In some embodiments, the thickness A1 of the SiC semiconductor wafer 200 is several hundred micrometers (μm) (eg, 250 μm, 300 μm, 500 μm). Figure 2A The illustrated thinning process is also configured to provide a substantially flat surface 202. In some embodiments, for example, the surface 202 has a flatness within 1 μm and a surface roughness less than 0.5 nm.

[0032] Figure 2A Also shown is the die portion of the SiC semiconductor wafer 200, including die portions 204(1) and 204(2). Figure 2AAs shown, the die portions have boundaries represented by dotted lines. Each die portion represents a die after the cutting process is completed. The boundaries between the die portions have a limited width to take into account the limited width of the cut C1, and the crack C2 is used to produce separated dies. Each die portion also has a boundary area called a cutout. In some embodiments, the cutout includes, for example, a test and / or alignment pattern. In some embodiments, each of the die portions is rectangular. In some embodiments, each of the die portions has a size of approximately 10 mm × 10 mm. In some embodiments, each of the die portions has a smaller size (e.g., 5 mm × 5 mm) or a larger size (e.g., 26 mm × 32 mm).

[0033] Figure 2B is a schematic diagram illustrating an exemplary SiC semiconductor wafer 210 after a back metal deposition operation is performed to produce a back metal 214 coupled (e.g., bonded) to the back side of the wafer 210. In some embodiments, the back metal 214 deposited on the back side of the wafer 210 comprises a film stack comprising silver, nickel, and / or tin. In some embodiments, the thickness of each layer in the film stack is between 1.5 μm and 2.0 μm. In some embodiments, the layers of the stack may comprise tantalum, copper, and / or aluminum.

[0034] Figure 2C is a schematic diagram illustrating an exemplary SiC semiconductor wafer 220 after a cutting operation is performed by a cutting tool to create a cut C1 between die portions 204(1) and 204(2). Figure 2C As shown, cutout C1 is vertical (eg, substantially vertical, aligned along direction y) and has a depth A2 that is a fraction of the thickness A1 of the SiC semiconductor wafer 220 .

[0035] In some embodiments, the width of the cutout C1 can be determined by the specified width of the kerf of the die portion separated by the cutout C1. In some embodiments, the width of the cutout C1 can be several microns (e.g., 2 μm, 5 μm). In some embodiments, the width of the cutout C1 can be greater than several microns (e.g., between 20 μm and 50 μm). Figure 2C Also shown is a back metal 214 deposited on the back side of the wafer 220 .

[0036] In some embodiments, the cut C1 has a uniform cross-section through the portion A2 even though the cut C1 is still aligned with the vertical direction. In some embodiments, the cut C1 has a non-uniform cross-section (e.g., a tapered cross-section, a convex cross-section, etc.). For example, when the cutting device (see Figure 3AWhen the apparatus 310 in FIG. 3 includes a laser ablation tool, the distribution of laser irradiance (ie, energy density) through portion A2 may vary along the vertical direction because the distribution of light for a tightly focused beam varies with the direction of propagation of the light.

[0037] Figure 2D is a schematic diagram illustrating an exemplary wafer 230 after both a cutting operation and a cleaving operation have been performed. Figure 2D The cut C1 resulting from the cutting operation and the rip C2 resulting from the cleaving operation are shown, both aligned with respect to the vertical (y) axis. Figure 2D As shown, the cutout C1 is aligned with the split C2. Figure 2D As shown, cleavage C2 extends from incision C1.

[0038] like Figure 2D As shown, the slit C2 has a smaller width than the cutout C1. In some embodiments, the width of the cutout C1 can be more than 5 times the width of the cutout C2. For example, in some embodiments, the cutout C1 can have a width between 20 μm and 50 μm, and the slit C2 can have a width between 3 μm and 5 μm. Figure 2E This difference between the widths of the cutout C1 and the rip C2 is discussed in further detail.

[0039] In some embodiments, the cut C1 has a uniform cross-section (e.g., profile) along the depth A2 of the cut C1. For example, the sidewalls of the cut C1 can be vertical and parallel between the die portions 204(1) and 204(2). In some embodiments, the cut C1 has a non-uniform cross-section along the depth A2 of the cut C2 (e.g., a tapered cross-section resulting from a cleaving operation, etc.).

[0040] In some embodiments, the rift C2 has a uniform cross-section (e.g., profile) along the depth A3 of the rift C2. For example, the sidewalls between the rift C2 can be vertical and parallel between the die portions 204(1) and 204(2). In some embodiments, the rift C2 has a non-uniform cross-section along the depth A3 of the rift C2 (e.g., a tapered cross-section resulting from a cleaving operation, etc.).

[0041] Figure 2E It shows Figures 2A-2D Schematic diagram of an enlarged exemplary view of die 254(1) and 254(2) (corresponding to die portions 204(1) and 204(2)) produced by the process shown. As mentioned above, the width W1 of the cut is greater than the width W2 of the rip. Therefore, the width of gap W3 (e.g., step) is approximately equal to (W1-W2) / 2. Gap W3 creates a step in die 254(1) of width (W1-W2) / 2. Figure 2EAs shown, the sidewalls associated with the cuts are vertical (eg, substantially vertical), and the sidewalls associated with the rips are vertical (eg, substantially vertical).

[0042] Figure 2E Example cross-sectional shapes (e.g., profiles) for cuts and rips are shown, however, cuts and rips can have different cross-sectional shapes. For example, in some embodiments, the sidewalls of the cuts can be aligned in the same plane as the sidewalls of the rips (rather than aligned in the same plane as in FIG. Figure 2E offset shown).

[0043] Figure 3A and Figure 3B is a schematic diagram illustrating an exemplary system for performing dicing of dies from SiC semiconductor wafer 130. The system includes a cutting device 310 for performing a cutting operation on a portion of SiC semiconductor wafer 210. The system also includes a cleaving device 320 for performing a cleaving operation on SiC semiconductor wafer 220 after performing the cutting operation. When performed according to the improved techniques described herein, the cutting operation and the subsequent cleaving operation result in a group of SiC semiconductor dies having vertical sidewalls (e.g., substantially vertical sidewalls).

[0044] like Figure 3A As shown, the cutting device 310 is configured to perform a cutting operation between the die portions of the SiC semiconductor wafer 210 to produce a set of cuts (e.g., Figures 2A-2D Incision C1 in the Figure 3A As shown, cutting apparatus 310 includes a controller 312 configured to control a cutting tool 340 to perform a cutting operation.

[0045] The cutting tool 340 is configured to cut the SiC semiconductor wafer 210 between the die portions. In some embodiments, the cutting tool 340 includes a mechanical saw blade. In some embodiments, the saw blade is a nickel bonded dicing blade. In some embodiments, the saw blade is a hub or hubless resin blade. In some embodiments, the saw blade is a metal sintered dicing blade. In some embodiments, the saw blade is configured to produce a cutting width between approximately 15 μm and 75 μm.

[0046] In some embodiments, cutting tool 340 comprises a laser ablation tool. Such a laser ablation tool performs a scribing operation to create a cut through a portion of the thickness of SiC semiconductor wafer 210 between die portions. In some embodiments, cutting tool 340 comprises a short-pulsed laser and a focusing lens. The laser can be of any wavelength, but it is advantageous for the laser to have a short wavelength (e.g., a UV wavelength less than 400 nm). In some embodiments, the laser ablation tool can produce a cut width between 10 μm and 50 μm.

[0047] The controller 312 is configured to control the cutting tool 340 so that the cut produced by the cutting tool 340 has a specified depth through a portion of the thickness of the SiC semiconductor wafer 210 and a specified width in the gaps between the die portions. In some embodiments, the controller 312 includes electronic control components configured to move the cutting tool 340 across the SiC semiconductor wafer 210 according to a dwell schedule. In some embodiments, when the cutting tool includes a mechanical saw blade, the electronic components are configured to position the saw blade along an axis perpendicular to the surface of the SiC semiconductor wafer 210 so that the saw blade performs a cutting operation at a portion of the thickness of the SiC semiconductor wafer 210. In some embodiments, the controller 312 includes mechanical components configured to position the saw blade along an axis perpendicular to the surface of the SiC semiconductor wafer 210. In some embodiments, when the cutting tool 340 comprises a laser ablation tool, the controller 312 comprises electronic control components configured to adjust the power of the laser and / or the number of passes across the SiC semiconductor wafer 210 to produce a cut having a specified depth through the thickness and / or width of the SiC semiconductor wafer 210. In some embodiments, the electronic control components are configured to adjust the position of the focusing lens to produce a cut having a specified depth through the thickness of the SiC semiconductor wafer 210.

[0048] Once the cutting device 310 performs the cutting operation, the SiC semiconductor wafer 210 becomes a cut semiconductor wafer 220, and the cut SiC semiconductor wafer 220 is transferred to the cracking device 320. In some embodiments, the transfer of the wafer 220 from the cutting device 310 to the cracking device 320 is performed by a robotic wafer transfer device having an end effector that is magnetically attached to the wafer 210 during the transfer.

[0049] like Figure 3B As shown, the cleaving device 320 is configured to perform a cleaving operation on the SiC semiconductor wafer 220 after performing a cutting operation on the SiC semiconductor wafer 210 to generate cracks that form separated dies. Figure 3BAs described above, the cracking device 320 includes, for example, an impulse bar 360 , which is configured to crack the wafer 220 at a designated position below the cutout C1 .

[0050] The cracking operation becomes possible when the cut C1 creates a stress concentration factor in the gap separating the die portions 204 (1) and 204 (2) of the wafer 220. When a force is applied by the pulse bar 360, the cracking operation causes the pulse bar 360 to crack through a portion of the thickness of the cut SiC semiconductor wafer 220 below the cut. In some embodiments, the pressure applied by the pulse bar to the cut SiC semiconductor wafer 220 may be between 300 kPa and 350 kPA. In some embodiments, the applied pressure may be greater than 350 kPA or less than 300 kPa. In some embodiments, the pressure is applied to the SiC semiconductor wafer 220 while the distance traveled by the pulse bar 360 may be between 80 μm and 100 μm. In some embodiments, the distance traveled by the pulse bar 360 may be greater than 100 μm or less than 80 μm. In some embodiments, the cracking operation is performed by static bending, anvil method, or non-contact method using a vacuum chuck.

[0051] In some embodiments, the rips produced by the cleaving operation are aligned with the cuts produced by the cutting operation performed by the cutting device 310. Figure 4A As discussed in more detail, this alignment depends on the portion A2 of thickness Al through which the cut is made.

[0052] Figure 4A Schematic diagram showing a SiC semiconductor wafer 230 cut into dies 254 ( 1 ) and 254 ( 2 ) according to the above-mentioned improved technology. Figure 3A As shown, SiC semiconductor wafer 230 has a notch C1 and a rift C2 that produce a set of dies, such as dies 254(1) and 254(2). Notch C1 has a depth A2 that is a fraction of the thickness A1 of SiC semiconductor wafer 230, rift C2 is aligned with notch C2, and both notch C1 and rift C2 are aligned along a vertical direction (e.g., substantially vertical direction).

[0053] The cut C1 is formed (e.g., manufactured) to a depth A2 into the thickness A1 of the wafer 230 such that a subsequent rip creates a cut C2 that is aligned with (e.g., aligned in the same direction as, parallel to) the cut C1. This alignment of the cut C2 with the cut C1 occurs when the portion A2 is at least 65% of the thickness A1 of the SiC wafer 230. In some embodiments, the portion A2 is preferably between about 65% and 75% of the thickness A1 of the SiC wafer 230. In some embodiments, the ratio of the portion A2 to the portion A3 is between about 2 and 3.

[0054] As described above, when the portion A2 of the thickness A1 of the cutout C1 is about 65-75% of the thickness A1, Figure 4A The case shown is where both cutout C1 and slit C2 are aligned relative to the vertical (y) axis. If portion A1 is less than 65% of A1, the resulting slit S may not be aligned with the y-axis and cutout C1, but may be positioned at an oblique angle relative to the y-axis. This oblique angle is undesirable because the die produced in the module may not provide a properly functioning device. When the portion is greater than 75%, the wear on the cutting tool used to perform the cutting operation may be too great, making it economically unfeasible in some applications.

[0055] Figure 4B 4 is a line drawing showing the aligned cuts and rips in scanning electron microscope (SEM) images 442 and 444. SEM image 442 shows a first die (e.g., die 254(1)) and SEM image 444 shows another die (e.g., die 254(2)). As shown in SEM images 442 and 444, the cuts and rips produced as described above have vertical sidewalls.

[0056] Figure 5 is a flow chart illustrating a method 500 of performing dicing of a SiC semiconductor wafer according to the improved technique described above.

[0057] At 502, a SiC semiconductor wafer (e.g., Figure 2A The wafer 200 is thinned (eg, ground) to a first thickness (eg, thickness A1). The surface of the thinned SiC semiconductor wafer is aligned along a plane (eg, the surface 202 is aligned in the x-direction).

[0058] At 504, a cutout (eg, Figure 2C The depth of the cut is less than the first thickness to which the SiC semiconductor wafer is ground (eg, portion A2). The cut is aligned along a vertical direction orthogonal to the plane (eg, the cut C1 is aligned along a vertical direction orthogonal to the plane). Figure 2D The kerf is aligned in the y-direction of the SiC semiconductor wafer, the kerf being aligned so that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the kerf and an outer surface of the SiC semiconductor wafer.

[0059] At 506, a cleaving operation is performed by vertically passing through a portion of the SiC semiconductor wafer having a second thickness to define a rift (eg, Figure 2D The rift is aligned with the cut and extends to the outer surface of the SiC semiconductor wafer.

[0060] In one general aspect, a method may include defining a kerf in a silicon carbide (SiC) semiconductor wafer by performing a partial scribing operation, the SiC semiconductor wafer aligned along a plane, the kerf having a depth less than a first thickness of the SiC semiconductor wafer, the kerf aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the kerf and an outer surface of the SiC semiconductor wafer; and defining a rift by performing a cleaving operation through the portion of the SiC semiconductor wafer having the second thickness, the rift aligned along the vertical direction and aligned with the kerf and extending to the outer surface of the SiC semiconductor wafer.

[0061] In some embodiments, the depth of the cut is between 65% and 75% of the thickness.

[0062] In some embodiments, the cut has a first width in a direction parallel to the plane, and the rift has a second width in a direction parallel to the plane, the first width being greater than the second width; and the cut and the rift are used to define a group of SiC dies, each of the group of SiC dies having a step having a width in a direction parallel to the plane based on a difference between the first width and the second width.

[0063] In some embodiments, the method further includes performing a back metal deposition on the SiC semiconductor wafer before performing the cleaving operation.

[0064] In some embodiments, performing the cleaving operation includes applying a cleaving force to the SiC semiconductor wafer along the cut using a pulse bar.

[0065] In some embodiments, performing the partial dicing operation includes receiving the SiC semiconductor wafer by a laser ablation tool; and limiting a power of the laser ablation tool such that the laser ablation tool defines a cut having a depth.

[0066] In some embodiments, performing a partial dicing operation includes receiving the SiC semiconductor wafer by a mechanical saw tool including a saw blade; and defining a position of the saw blade to define a cut having a depth.

[0067] In another general aspect, a system may include a wafer chuck configured to receive a SiC semiconductor wafer thinned to a first thickness, a surface of the thinned SiC semiconductor wafer aligned along a plane; a dicing device configured to perform a partial dicing operation on the SiC semiconductor wafer to define a kerf in the SiC semiconductor wafer, the kerf having a depth less than the first thickness of the SiC semiconductor wafer, the kerf aligned along a vertical direction orthogonal to the plane, the kerf aligned such that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the kerf and an outer surface of the SiC semiconductor wafer; and a cleaving device configured to perform a cleaving operation along the vertical direction through the portion of the SiC semiconductor wafer having the second thickness to define a rift aligned with the kerf and extending to the outer surface of the SiC semiconductor wafer.

[0068] In some embodiments, the depth is between 65% and 75% of the first thickness of the SiC semiconductor wafer.

[0069] In some embodiments, the cut has a first width in a direction parallel to the plane, and the rift has a second width in a direction parallel to the plane, the first width is greater than the second width, and the cut and the rift are used to define a group of SiC dies, each of the group of SiC dies having a step having a width in a direction parallel to the plane based on a difference between the first width and the second width.

[0070] In some embodiments, the system further includes a back metal deposition apparatus configured to perform a back metal deposition operation on the SiC semiconductor wafer before performing the cleaving operation.

[0071] In some embodiments, performing the cleaving operation includes applying a cleaving force to the SiC semiconductor wafer along the cut using a pulse bar.

[0072] In some embodiments, the dicing apparatus includes a laser ablation tool configured to cut through the SiC semiconductor wafer at a depth.

[0073] In some embodiments, the dicing apparatus includes a mechanical saw tool configured to cut through the SiC semiconductor wafer at a depth.

[0074] In some embodiments, the system further includes an automated transfer apparatus having an end effector configured to apply a transfer force to the partially diced SiC semiconductor wafer to transfer the partially diced SiC semiconductor wafer from the dicing apparatus to the cleaving apparatus, the transfer force being depth-based.

[0075] In another general aspect, a method may include thinning a silicon carbide (SiC) semiconductor wafer to a thickness, a surface of the thinned SiC semiconductor wafer aligned along a plane; performing a partial scribing operation on the SiC semiconductor wafer to define a cut in the SiC semiconductor wafer through a first portion of the thickness of the SiC semiconductor wafer, the cut aligned along a vertical direction orthogonal to the plane, the cut aligned such that a portion of the SiC semiconductor wafer has a second thickness extending between a bottom of the cut and an outer surface of the SiC semiconductor wafer, the cut also having a first width in a direction parallel to the plane; and performing a cleaving operation to define a rift having a second width less than the first width, the rift aligned with the vertical rift and passing through the second portion of the thickness of the SiC semiconductor wafer.

[0076] In some embodiments, the cuts and rifts are used to define a group of SiC dies, each of the group of SiC dies having a step having a width in a direction parallel to the plane based on a difference between the first width and the second width.

[0077] In some embodiments, the first portion of the thickness of the SiC semiconductor wafer is between 65% and 75% of the thickness of the SiC semiconductor wafer.

[0078] In some embodiments, the partial scribing operation is performed by a laser ablation tool, and wherein performing the partial scribing operation includes adjusting at least one of a power or a pass of the laser ablation tool to enable the laser ablation tool to define a kerf through a first portion of the thickness of the SiC semiconductor wafer.

[0079] In some embodiments, the partial scribing operation is performed by a mechanical saw tool, and wherein performing the partial scribing operation includes adjusting a position of a saw blade to enable the saw tool to define a cut having a depth.

[0080] A number of embodiments have been described, but it will be understood that various modifications can be made without departing from the spirit and scope of the disclosure.

[0081] It should also be understood that when an element is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to another element, or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, there is no intermediate element. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to an element may be referred to in this manner. The claims of this application may be revised to narrate the exemplary relationships described in the specification or shown in the drawings.

[0082] The various devices and techniques described herein may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates including, but not limited to, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and the like.

[0083] It should also be understood that when an element, such as a layer, region, or substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element can be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers.

[0084] Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the detailed description, elements shown as being "directly on," "directly connected," or "directly coupled to" may be referred to in this manner. The claims of this application may be amended to recite exemplary relationships described in the specification or shown in the drawings.

[0085] As used in this specification, singular forms may include plural forms unless the context clearly indicates otherwise. Spatially relative terms (e.g., above, above, above, below, below, under, below, etc.) are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include lateral adjacent or horizontal adjacent.

[0086] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented merely by way of example, not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein can be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0087] Additionally, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desired results. Additionally, other steps can be provided, or steps can be eliminated from the depicted flows, and other components can be added to or removed from the depicted systems. Accordingly, other implementations are within the scope of the following claims.

Claims

1. A system configured to separate dies in a SiC semiconductor wafer, comprising: A cutting device comprising: a cutting tool configured to perform a cutting operation on the first surface of the SiC semiconductor wafer in the gaps between the die portions to produce a cut resulting in a cut of the SiC semiconductor wafer; and a controller configured to control the cutting tool so that the cut produced by the cutting tool has a specified depth through a portion of the thickness of the SiC semiconductor wafer and a specified width in the gap between the die portions; and a cleaving device configured to perform a cleaving operation on the cut SiC semiconductor wafer on a second surface of the SiC semiconductor wafer to produce cracks resulting in separated dies after the cutting operation has been performed on the SiC semiconductor wafer, the second surface being opposite to the first surface. 2 . The system of claim 1 , wherein the controller comprises electronic components configured to move the cutting tool over the SiC semiconductor wafer according to a dwell schedule.

3. The system of claim 1, wherein the cutting tool comprises a mechanical saw blade.

4. The system of claim 3 , wherein the controller comprises an electronic control component configured to position the mechanical saw blade along an axis perpendicular to the first surface of the SiC semiconductor wafer so that the mechanical saw blade performs the cutting operation on the first surface of the SiC semiconductor wafer at the portion of the thickness of the SiC semiconductor wafer.

5. The system of claim 1 , wherein the cutting tool comprises a laser ablation tool, and wherein the cutting operation comprises a scribing operation performed by the laser ablation tool to create the cut through a portion of the thickness of the SiC semiconductor wafer between the die portions.

6. The system of claim 5, wherein the laser ablation tool comprises a short pulse laser and a focusing lens. 7 . The system of claim 6 , wherein the controller comprises electronic control components configured to adjust the power of the short pulse laser to produce a cut having a specified depth through the thickness of the SiC semiconductor wafer. 8 . The system of claim 6 , wherein the controller comprises electronic control components configured to adjust the position of the focusing lens to produce the cut having the specified depth through the thickness of the SiC semiconductor wafer.

9. The system of claim 1 , wherein the controller includes electronic control components configured to adjust a number of passes across the SiC semiconductor wafer to produce the kerfs having the specified width in the gaps between the die portions. 10 . The system according to claim 1 , wherein the cleaving device comprises a pulse bar configured to cleave at a designated position on the second surface of the SiC semiconductor wafer to perform the cleaving operation on the SiC semiconductor wafer.

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