Erase method of nonvolatile memory and nonvolatile memory

Abstract

The present disclosure provides an erasing method of a non-volatile memory and a non-volatile memory, and relates to the technical field of semiconductors. The method comprises: performing a first erasing operation on a target erasing area and then performing a first erasing verification operation to obtain a first erasing verification result of each storage unit in the target erasing area; obtaining a first erasing verification result of the target erasing area according to the first erasing verification result of each storage unit in the target erasing area; in response to the first erasing verification result of the target erasing area being failed, performing a second erasing operation on the target erasing area and then performing a second erasing verification operation to obtain a second erasing verification result of each storage unit in the target erasing area; and determining whether to perform a third erasing operation on the target erasing area according to the number of storage units in the target erasing area whose first erasing verification result and second erasing verification result are both failed. The method narrows the threshold voltage distribution range of the storage unit after the erasing operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to an erase method of non-volatile memory and non-volatile memory. BACKGROUND

[0002] Non-volatile memory can retain data after power off, and Flash memory is a key non-volatile memory. Flash memory includes NAND Flash and NOR Flash. Taking NAND Flash as an example, it stores data by programming and erasing memory cells, has the advantages of low cost, fast reading and writing, large capacity, and is widely used in various electronic products. With the large use of NAND Flash, the requirement for its performance is also increasing.

[0003] The distribution of threshold voltage Vt of memory cells in NAND Flash is an important performance, and the size of the distribution range of Vt will affect the programming time and the size of the programming voltage of the flash memory, and then affect its performance parameters such as power consumption and area. How to reduce the threshold voltage Vt distribution range of the memory cell becomes a problem to be solved.

[0004] The above information disclosed in the background section is only intended to strengthen the understanding of the background of the present disclosure, and therefore it can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide an erase method of non-volatile memory and non-volatile memory, which at least reduces the threshold voltage distribution range of the memory cell after the erase operation.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned partly through practice of the present disclosure.

[0007] According to an aspect of the present disclosure, a method for erasing a non-volatile memory is provided, comprising: performing a first erasing operation on a target erasing area; performing a first erasing verification operation on the target erasing area to obtain a first erasing verification result of each memory cell in the target erasing area; obtaining a first erasing verification result of the target erasing area according to the first erasing verification result of each memory cell in the target erasing area; performing a second erasing operation on the target erasing area in response to the first erasing verification result of the target erasing area being failed; performing a second erasing verification operation on the target erasing area to obtain a second erasing verification result of each memory cell in the target erasing area; and determining whether to perform a third erasing operation on the target erasing area according to a number of memory cells in the target erasing area whose first erasing verification result and second erasing verification result are both failed.

[0008] According to an embodiment of the present disclosure, the determining whether to perform the third erasing operation on the target erasing area according to the number of memory cells in the target erasing area whose first erasing verification result and second erasing verification result are both failed comprises: determining that the target erasing area is successfully erased and not performing the third erasing operation on the target erasing area in a case that the number of memory cells in the target erasing area whose first erasing verification result and second erasing verification result are both failed is less than or equal to a first preset number threshold.

[0009] According to an embodiment of the present disclosure, the method further comprises: performing an or operation on the first erasing verification result and the second erasing verification result of each memory cell in the target erasing area to obtain the number of memory cells in the target erasing area whose first erasing verification result and second erasing verification result are both failed.

[0010] According to an embodiment of the present disclosure, the method further comprises: obtaining that the first erasing verification result of the target erasing area is failed in a case that the number of memory cells in the target erasing area whose first erasing verification result is failed is greater than a first preset number threshold.

[0011] According to another aspect of the present disclosure, a non-volatile memory is provided, comprising: a memory cell array including a target erase area; a controller configured to perform: a first erase operation on the target erase area; a first erase verification operation on the target erase area, obtain a first erase verification result of each memory cell in the target erase area, and store the first erase verification result of each memory cell in the target erase area to a first latch; obtain a first erase verification result of the target erase area according to the first erase verification result of each memory cell in the target erase area; in response to the first erase verification result of the target erase area being failed, perform a second erase operation on the target erase area; a second erase verification operation on the target erase area, obtain a second erase verification result of each memory cell in the target erase area, and store the second erase verification result of each memory cell in the target erase area to a second latch; obtain a number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed; and determine whether to perform a third erase operation on the target erase area according to the number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed.

[0012] According to an embodiment of the present disclosure, the controller is further configured to correspond or operate the first erase verification result of each memory cell in the target erase area with the second erase verification result to obtain the number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed.

[0013] According to an embodiment of the present disclosure, the controller is further configured to store the result of the or operation of the first erase verification result of each memory cell in the target erase area with the second erase verification result to the first latch.

[0014] According to an embodiment of the present disclosure, the controller is further configured to determine that the target erase area is successfully erased and not perform the third erase operation on the target erase area when the number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed is less than or equal to a first preset number threshold.

[0015] According to an embodiment of the present disclosure, the controller is further configured to obtain that the first erase verification result of the target erase area is failed when the number of memory cells in the target erase area whose first erase verification result is failed is greater than the first preset number threshold.

[0016] According to an embodiment of the present disclosure, the non-volatile memory is a NAND Flash.

[0017] The erasing method of the non-volatile memory provided by the embodiments of the present disclosure comprises: performing a first erasing operation on a target erasing area, performing a first erasing verification operation after the first erasing operation, obtaining a first erasing verification result of each memory cell in the target erasing area, obtaining a first erasing verification result of the target erasing area according to the first erasing verification result of each memory cell in the target erasing area, and then performing a second erasing operation on the target erasing area in response to the first erasing verification result of the target erasing area being failed, performing a second erasing verification operation after the second erasing operation, obtaining a second erasing verification result of each memory cell in the target erasing area, and then judging whether to perform a third erasing operation on the target erasing area according to the number of memory cells whose first erasing verification result and second erasing verification result are both failed. The above method realizes the judgment of whether the memory cell is successfully erased according to twice erasing verification results, thereby avoiding the expansion of the distribution range of the threshold voltage of the memory cell caused by the third erasing operation directly according to the second erasing verification result of each memory cell, and reducing the distribution range of the threshold voltage of the memory cell after the erasing operation to a certain extent.

[0018] It should be understood that the general description above and the following detailed description are only exemplary and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

[0020] Figure 1 A structure schematic diagram of a non-volatile memory in embodiments of the present disclosure is shown.

[0021] Figure 2 A NAND Flash memory cell array schematic diagram in embodiments of the present disclosure is shown.

[0022] Figure 3 A memory cell structure schematic diagram in embodiments of the present disclosure is shown.

[0023] Figure 4 A threshold voltage distribution change schematic diagram of a memory cell in embodiments of the present disclosure is shown.

[0024] Figure 5 A flow chart of an erasing method of a non-volatile memory in embodiments of the present disclosure is shown.

[0025] Figure 6 A basic structure schematic diagram of a circuit for storing erasing verification results in embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0027] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0028] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0029] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0030] Figure 1 A schematic diagram of the structure of a non-volatile memory to which this disclosure can be applied is shown. For example... Figure 1 As shown, the non-volatile memory 102 is electrically coupled to the host 104. The non-volatile memory 102 can communicate bidirectionally with the host through the controller 1024 to transmit commands, addresses, data, etc. The non-volatile memory 102 is, for example, a USB flash drive, a portable hard drive, a memory card, or a flash memory. The host 104 is the user's device, which can be various electronic devices with a display screen and supporting input and output, such as mobile phones, tablets, laptops, cameras, etc.

[0031] The non-volatile memory 102 can include a memory cell array 1022, a controller 1024, a row decoder 1026, sensing circuitry 1028, a column decoder 10210, a first latch 10212, a second latch 10214, and the like. The memory cell array 1022 can include a plurality of memory cells addressed by word lines and bit lines. An implementation of a memory cell array that can be applied to a NAND Flash can refer to Figure 2 The controller 1024 can be configured to receive commands, addresses, and the like, and provide control signals to other circuits such as the row decoder 1026, the sensing circuitry 1028, the column decoder 10210, and the like, based on the received commands and addresses. The row decoder 1026 can be configured to select a word line (WL) based on a row address. The column decoder 10210 can be configured to select a bit line (BL), i.e., perform a selection operation on a plurality of bit lines, based on a column address. The sensing circuitry 1028 can include a plurality of sense amplifiers (SAs) configured to read out data stored in the memory cells. The first latch 10212 and the second latch 10214 coupled to the BLs of the memory cell array 1022 through the column decoder 10210 can be configured to buffer data in read and write operations.

[0032] The flash implementation can be divided into a NAND (not-and) scheme and a NOR (or-not) scheme. The following describes a NAND Flash as an example.

[0033] Figure 2 A schematic diagram of a memory cell array of a NAND Flash to which the present disclosure can be applied is shown. As Figure 2 indicated, Figure 2 the memory cell array of the NAND Flash in Figure 3 includes a plurality of memory cells on the same substrate. An exemplary structure of the memory cell 202 can refer to Figure 2The diagram illustrates a memory cell array with 64 word lines, designated WL0, WL1, WL2...WL63. The memory cells in each column are connected in series; the source of the first cell in each column (connected to WL0) is connected to the drain of the column's ground selection transistor (GST), and the drain of the last cell in each column (e.g., connected to WL63) is connected to the source of the column's string selection transistor (SST). The gate of each column's GST is connected to the ground selection line (GSL), and the source of each column's GST is connected to the common source line (CSL). The gate of each column's SST is connected to the string selection line (SSL), and the drain of each column's SST is connected to the corresponding bit line BL to couple to the corresponding column's sense amplifier SA. Figure 2 The diagram illustrates that this memory cell array has N bit lines, BL0, BL1, BL2...BL... N-1 (N is a positive integer), and the corresponding sensing amplifiers are SA0, SA1, SA2...SA N-1 .

[0034] Figure 3 A schematic diagram of a memory cell structure to which this disclosure can be applied is shown. For example... Figure 3 As shown, a memory cell may include a source 310, a drain 312, and a semiconductor substrate 314. A tunneling oxide layer 308, a floating gate 306, a barrier insulating layer 304, and a control gate 302 may be sequentially stacked on the substrate 314. The control gate 302 may be connected to a word line. Injecting electrons into the floating gate 306 constitutes a programming operation on the memory cell. When there are trapped electrons, the corresponding memory cell is in a programming state of logic "0"; when there are no trapped electrons in the floating gate 306, the corresponding memory cell is in an erase state of logic "1".

[0035] In the erase operation of the NAND Flash chip, an erase voltage is usually applied on the substrate 314 to form an electric field perpendicular to the substrate direction, so that the electrons in the floating gate 306 return to the substrate 314. After performing an erase operation on the target erase area once, an erase verify operation is performed on the memory cells in the target erase area, i.e. an erase verify voltage (VFY) is applied to the control gate of the memory cells, and it is detected whether the memory cells are turned on (whether the threshold voltage of the memory cells is less than VFY) to determine whether the erase operation is successful or not, and whether the next erase operation is performed. For example, in the first erase verify operation, if the number of memory cells with a failed erase verify result (i.e. the erase operation is not successful) is greater than a preset number threshold, a second erase operation is performed, and then a second erase verify operation is performed. However, the memory cells passing the first erase verify operation may fail the second erase verify operation due to the bit line jitter and other interference factors, and then a third erase verify operation is performed, so that the threshold voltage distribution of all the memory cells is widened, and the performance of the chip is reduced. Figure 4 A threshold voltage distribution change diagram of a memory cell is shown. As shown in Figure 4 , Figure 4 The horizontal coordinate Vt represents the voltage, and the vertical coordinate represents the number of memory cells. The rightmost vertical solid line represents the erase verify voltage VFY. The dashed curve represents the threshold voltage distribution of the memory cells after the second erase operation, and the solid curve represents the threshold voltage distribution of the memory cells after the third erase operation. As shown in Figure 4 the shaded part A near VFY, the memory cells in the shaded part A fail the second erase verify operation (they pass the first erase verify operation), and if the next (third) erase operation is determined according to the second erase verify result of each memory cell (for example, the number of memory cells failing the second erase verify operation), the threshold voltage of the memory cells in the shaded part B will be moved to the left to the left shaded part C in the third erase verify operation, which makes the threshold voltage distribution of the memory cells wider.

[0036] Therefore, the present disclosure provides an erase method of a non-volatile memory. Whether to perform a third erase operation on a target erase area is determined according to the number of memory cells failing both the first erase verify operation and the second erase verify operation in the target erase area, so that the success of the erase operation of the memory cells is determined according to the two erase verify results, thereby avoiding the expansion of the threshold voltage distribution range of the memory cells caused by directly determining the third erase operation according to the second erase verify result of each memory cell, and the threshold voltage distribution range of the memory cells after the erase operation is reduced to a certain extent.

[0037] Figure 5 A flowchart of an erase method of a non-volatile memory according to an exemplary embodiment is shown. As shown in Figure 5The illustrated method can be applied, for example, to the controller 1024 of the nonvolatile memory 102 described above.

[0038] With reference to Figure 5 The method 50 provided by the embodiments of the present disclosure can include the following steps.

[0039] In step S502, a first erase operation is performed on the target erase area.

[0040] In some embodiments, the target erase area can be one block of the memory cell array, for example, can be a block of the memory cell array in the nonvolatile memory 102 described above. Figure 2 The memory cell array in the nonvolatile memory 102 described above includes a plurality of rows (pages) of memory cells, each row of memory cells being connected to the same word line.

[0041] In some embodiments, the erase operation of the NAND Flash can be: applying a positive erase voltage to the substrate in the target erase area, and applying a 0V voltage to the word line; the erase operation of the NOR Flash can be: applying a positive erase voltage to the substrate in the target erase area, and applying a negative voltage to the word line. Wherein, the electric field generated by the erase voltage and the word line voltage causes the electrons in the floating gate of the memory cell in the target erase area to enter the substrate through the FN tunneling effect.

[0042] In some embodiments, the first erase operation can be the first erase operation, or can be one of the multiple erase operations, for example, can be the third erase operation; the second erase operation represents the next erase operation of the first erase operation, and is not necessarily the second erase operation, for example, can be the fourth erase operation after the third erase operation.

[0043] In step S504, a first erase verification operation is performed on the target erase area, and a first erase verification result of each memory cell in the target erase area is obtained.

[0044] In some embodiments, the erase verification operation can be a kind of read operation, which is performed on the memory cells in the target erase area row by row, in order to obtain the first erase verification result of each memory cell in the target erase area. Figure 2For example, when performing the erase verify on the page connected to the word line WL1, an erase verify voltage is applied to the word line WL1, and the conduction of the row of memory cells is determined based on the current on the bit line. If there is a large current on the bit line, it indicates that the memory cell is conducting, and its threshold voltage is less than the erase verify voltage. Therefore, the first erase verify result of the memory cell is pass. When performing the erase verify operation on the row of memory cells connected to the word line WL1, the other word lines WL2, WL3, …, WL63 can all be applied with a pass voltage Vpass to make the memory cells in these rows conduct. The first erase verify results of the memory cells in the target erase region are stored in the latch. For example, after the erase operation, if the memory cell is in the erased state, the erase verify result is pass, and the sense amplifier writes 1 in the latch. If the memory cell is not in the erased state, the erase verify result is fail, and the sense amplifier writes 0 in the latch.

[0045] In step S506, the first erase verify result of the target erase region is obtained according to the first erase verify results of the memory cells in the target erase region.

[0046] In some embodiments, for example, the first erase verify result of the target erase region can be obtained as fail when the number of memory cells with fail in the target erase region is greater than a first preset number threshold. For example, the number of memory cells with fail is determined according to the number of 1 in the latch. When the first erase verify result of the target erase region is fail, it is considered that the first erase operation fails, and the next erase operation is performed, which can be the second erase operation in the embodiments of the present application.

[0047] In some embodiments, for example, the first erase verify result of the target erase region can be obtained as pass when the number of memory cells with fail in the target erase region is less than or equal to the first preset number threshold.

[0048] In step S508, in response to obtaining the first erase verify result of the target erase region as fail, a second erase operation is performed on the target erase region.

[0049] In some embodiments, when the first erase verify result of the target erase region is fail, it is considered that the first erase operation fails, and the second erase operation is performed.

[0050] In some embodiments, the second erase operation is similar to the first erase operation, and the erase voltage applied in the second erase operation can be the same as or different from the erase voltage applied in the first erase operation, for example, greater than the erase voltage applied in the first erase operation.

[0051] In step S510, a second erase verification operation is performed on the target erase area to obtain second erase verification results of the memory cells in the target erase area.

[0052] In some embodiments, the method of obtaining the second erase verification results of the memory cells can be similar to the method of obtaining the first erase verification results of the memory cells, which will not be repeated here.

[0053] In step S512, it is determined whether to perform a third erase operation on the target erase area according to the number of memory cells in the target erase area whose first erase verification results and second erase verification results are both failed.

[0054] In some embodiments, when the number of memory cells in the target erase area whose first erase verification results and second erase verification results are both failed is less than or equal to the first preset number threshold, it is determined that the target erase area is successfully erased, and the third erase operation is not performed on the target erase area.

[0055] In some embodiments, when the number of memory cells in the target erase area whose first erase verification results and second erase verification results are both failed is greater than the first preset number threshold, it is determined that the target erase area is unsuccessfully erased, and the third erase operation is performed on the target erase area.

[0056] In some embodiments, the method of obtaining the number of memory cells in the target erase area whose first erase verification results and second erase verification results are both failed can be that, for each memory cell in the target erase area, the first erase verification result of the memory cell is ANDed with the second erase verification result of the memory cell.

[0057] In some embodiments, for example, the first erase verification result of each memory cell can be stored in a first latch, and the second erase verification result of each memory cell can be stored in a second latch. After the first erase verification result and the second erase verification result of each memory cell are ANDed, the result is stored in the first latch. For details, refer to Figure 1 and Figure 6 .

[0058] According to the erasing method of the non-volatile memory provided by the embodiment of the present disclosure, by judging whether to perform the third erasing operation on the target erasing area according to the number of storage units whose first erasing verification result and second erasing verification result are both failed, the erasing operation of the storage unit is considered successful as long as one of the first erasing verification result and the second erasing verification result is passed, so as to avoid that the storage unit whose threshold voltage is near the erasing verification voltage is determined to be failed due to bit line jitter in the second erasing verification, and the third erasing operation is performed, so as to expand the distribution range of the threshold voltage of the storage unit. Therefore, the distribution range of the threshold voltage of the storage unit after the erasing operation can be reduced to a certain extent.

[0059] According to still another aspect of the present disclosure, a non-volatile memory is provided, referring to Figure 1 The non-volatile memory 102 may, for example, be a NAND Flash, and may include a storage unit array 1022, a controller 1024, a first latch 10212, and a second latch 10214.

[0060] The storage unit array 1022 may include a target erasing area, and the controller 1024 may be configured to perform: a first erasing operation on the target erasing area; a first erasing verification operation on the target erasing area, to obtain a first erasing verification result of each storage unit in the target erasing area and store the first erasing verification result of each storage unit in the target erasing area to the first latch 10212; a first erasing verification result of the target erasing area according to the first erasing verification result of each storage unit in the target erasing area; a second erasing operation on the target erasing area in response to the first erasing verification result of the target erasing area being failed; a second erasing verification operation on the target erasing area, to obtain a second erasing verification result of each storage unit in the target erasing area and store the second erasing verification result of each storage unit in the target erasing area to the second latch 10214; a number of storage units whose first erasing verification result and second erasing verification result are both failed in the target erasing area; and a third erasing operation on the target erasing area according to the number of storage units whose first erasing verification result and second erasing verification result are both failed in the target erasing area.

[0061] The controller 1024 may also be configured to correspondingly perform or calculate the first erasing verification result and the second erasing verification result of each storage unit in the target erasing area, to obtain the number of storage units whose first erasing verification result and second erasing verification result are both failed in the target erasing area.

[0062] In some embodiments, the first erase verification results of the memory cells in the target erase region in the second latch 10214 are stored to the first latch 10212 as a result of an OR operation with the second erase verification results in the first latch 10212. The specific implementation of the first latch 10212, the second latch 10214, and the sensing circuit 1028 can refer to Figure 6 .

[0063] The controller 1024 can also be configured to determine that the target erase region is successfully erased without performing a third erase operation on the target erase region, if the number of memory cells in the target erase region that have failed the first erase verification and the second erase verification is less than or equal to a first preset number threshold.

[0064] The controller 1024 can also be configured to obtain that the first erase verification results of the target erase region have failed, if the number of memory cells in the target erase region that have failed the first erase verification is greater than the first preset number threshold.

[0065] The specific implementation of the controller 1024 performing the above operations can refer to Figure 5 , which will not be repeated here.

[0066] Figure 6 A basic structure of a circuit for storing erase verification results is shown. The first latch 10212 and the second latch 10214 can be, for example, static random-access memory (SRAM) cells. The first latch 10212 and the second latch 10214 each include a plurality of latch cells, and each BL in the memory cell array can be connected to a sense amplifier SA through the latch cell. Figure 6 The latch cells of the first latch 10212 and the second latch 10214 are shown. The first erase verification results of the memory cells in the target erase region obtained by the sensing circuit 1028 are first stored in the second latch 10214, and then moved from the second latch 10214 to the first latch 10212 to release the second latch 10214. The second erase verification results of the memory cells in the target erase region obtained by the sensing circuit 1028 are stored in the second latch 10214, and the second erase verification results in the second latch 10214 and the first erase verification results in the first latch 10212 are stored in the first latch 10212 after an OR operation.

[0067] The sense circuit SA includes a capacitor C. When performing the erase verify operation, the capacitor C is first charged to bring the voltage of the node SO to the high level VDD. If the target memory cell is successfully erased and is in the erased state, the node SO remains at the high level VDD. If the target memory cell is not successfully erased and is not in the erased state, the capacitor C is discharged and the voltage of the node SO is lowered.

[0068] The first latch 10212 includes cross-coupled inverters INV1 and INV2, and transistors MN1 and MN2. The first latch 10212 has two complementary nodes OUT1 and OUT1B, the node OUT1B connecting the drain of the transistor MN5 via the transistor MN1, and the node OUT1 connecting the drain of the transistor MN5 via the transistor MN2, the source of the transistor MN5 being grounded, and the gate of the transistor MN5 connecting the node SO.

[0069] Similarly, the second latch 10214 includes cross-coupled inverters INV3 and INV4, and transistors MN3 and MN4. The second latch 10214 has two complementary nodes OUT2 and OUT2B, the node OUT2B connecting the drain of the transistor MN6 via the transistor MN3, and the node OUT2 connecting the drain of the transistor MN6 via the transistor MN4, the source of the transistor MN6 being grounded, and the gate of the transistor MN6 connecting the node SO.

[0070] The procedure of storing the erase verify result of the memory cell into the second latch 10214 is as follows. The node SO is brought to the high level by charging, the RST2 signal turns on the transistor MN4, the SET2 signal turns off the transistor MN3, the node OUT2 is at the low level (logic 0), and the node OUT2B is at the high level (logic 1). The erase verify operation of the memory cell is performed. If the memory cell is successfully erased, the voltage of the node SO remains high. If the memory cell is not successfully erased, the capacitor C is discharged and the voltage of the node SO is lowered. The SET2 signal turns on the transistor MN3. If the node SO remains high, the node OUT2B is lowered to the low level, and the node OUT2 is brought to the high level. If the node SO is lowered to the low level, the node OUT2 remains at the low level, and the node OUT2B remains at the high level. In this way, the erase verify result of the memory cell is stored into the second latch 10214. The node OUT2 is at the logic 0, indicating that the erase verify result of the memory cell is failed. The node OUT2 is at the logic 1, indicating that the erase verify result of the memory cell is passed.

[0071] The process of passing the erase verify result of the memory cell from the second latch 10214 to the first latch 10212 is as follows. First, the SO is charged to high level by the charging, the RST1 signal makes the transistor MN2 conductive, the node OUT1 is set to low level, and the node OUT1B is set to high level. Then, the VTF signal makes the transistor MN7 conductive, and the node SO is connected to the node OUT2. If the node OUT2 of the second latch 10214 is high level, the node SO remains high level, and if the node OUT2 of the second latch 10214 is low level, the capacitor C is discharged, and the node SO becomes low level. Then, the SET1 signal makes the transistor MN1 conductive, and if the node SO is high level, the transistor MN5 is conductive, the node OUT1B of the first latch 10212 is set to low level, and the node OUT1 is set to high level; if the node SO is low level, the transistor MN5 is cut off, the node OUT1B of the first latch 10212 remains high level, and the node OUT1 remains low level, achieving OUT1 = OUT2.

[0072] The process of performing or operation of the second erase verify result in the second latch 10214 and the first erase verify result in the first latch 10212 and storing to the first latch 10212 is as follows. For example, the first erase verify result of the memory cell to be verified is failed, and the second erase verify result is passed, so the node OUT1 is low level, and the node OUT2 is high level. First, the node SO is charged to high level. The VTF signal opens the MN7 to connect the node SO and the node OUT2, the node SO remains high level, the SET1 signal makes the transistor MN1 conductive, the node OUT1B becomes low level, and the node OUT1 becomes high level, thereby achieving or operation of the first erase verify result and the second erase verify result and storing in the first latch 10212.

[0073] For another example, the first erase verify result of the memory cell to be verified is passed, and the second erase verify result is failed, so the node OUT1 is high level, and the node OUT2 is low level. First, the node SO is charged to high level. The VTF signal opens the MN7 to connect the node SO and the node OUT2, the node SO becomes low level, the SET1 signal makes the transistor MN1 conductive, and since the transistor MN5 is cut off, the node OUT1B remains low level, and the node OUT1 remains high level, thereby achieving or operation of the first erase verify result and the second erase verify result and storing in the first latch 10212.

[0074] For another example, if the first erase verification result and the second erase verification result of the verified storage unit are both failed, the node OUT1 is low and the node OUT2 is low. The node SO is first charged to high. The VTF signal opens the MN7 to connect the node SO and the node OUT2, the node SO becomes low, the transistor MN5 is disconnected, the SET1 signal makes the MN1 conductive, the node OUT1B keeps high, the node OUT1 keeps low, thus realizing the OR operation of the first erase verification result and the second erase verification result and storing in the first latch 10212.

[0075] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structure, arrangement or implementation method described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended claims.

Claims

1. An erasing method of a nonvolatile memory, characterized by, The method comprises: performing a first erase operation on a target erase area; performing a first erase verification operation on the target erase area to obtain first erase verification results of each memory cell in the target erase area; obtaining a first erase verification result of the target erase area according to the first erase verification results of each memory cell in the target erase area; performing a second erase operation on the target erase area in response to obtaining the first erase verification result of the target erase area as failed; performing a second erase verification operation on the target erase area to obtain second erase verification results of each memory cell in the target erase area; performing an or operation on the first erase verification results and the second erase verification results of each memory cell in the target erase area to obtain a number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed; determining that the target erase area is successfully erased without performing a third erase operation on the target erase area in a case where the number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed is less than or equal to a first preset number threshold.

2. The method of claim 1, wherein, The method further comprises: obtaining that the first erase verification result of the target erase area is failed in a case where the number of memory cells in the target erase area whose first erase verification result is failed is greater than the first preset number threshold.

3. A nonvolatile memory, comprising: The method comprises: a memory cell array, a controller, a first latch and a second latch, the memory cell array comprising a target erase area, the controller being configured to perform: performing a first erase operation on the target erase area; performing a first erase verification operation on the target erase area to obtain first erase verification results of each memory cell in the target erase area and storing the first erase verification results of each memory cell in the target erase area to the first latch; obtaining a first erase verification result of the target erase area according to the first erase verification results of each memory cell in the target erase area; performing a second erase operation on the target erase area in response to obtaining the first erase verification result of the target erase area as failed; performing a second erase verification operation on the target erase area to obtain second erase verification results of each memory cell in the target erase area and storing the second erase verification results of each memory cell in the target erase area to the second latch; performing an or operation on the first erase verification results and the second erase verification results of each memory cell in the target erase area to obtain a number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed; determining that the target erase area is successfully erased without performing a third erase operation on the target erase area in a case where the number of memory cells in the target erase area whose first erase verification result and second erase verification result are both failed is less than or equal to a first preset number threshold.

4. The nonvolatile memory of claim 3, wherein, The controller is further configured to store a result of an OR operation of the first erase verification result and the second erase verification result of each memory cell in the target erase area into the first latch.

5. The nonvolatile memory of claim 3, wherein, The controller is further configured to obtain that the first erase verification result of the target erase area is failed in a case that a number of memory cells with the failed first erase verification result in the target erase area is greater than a first preset number threshold.

6. The nonvolatile memory of claim 3, wherein, The non-volatile memory is a NAND Flash.

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