Method for manufacturing sigma trench structure and method for manufacturing semiconductor device

Abstract

The application provides a manufacturing method of a sigma trench structure and a manufacturing method of a semiconductor device, wherein a heat oxidation method is used to form an extremely thin oxide layer between gate structures, and the oxide layer forms a thickening layer in a silicon substrate; the oxide layer is etched to remove the oxide layer and form a groove in the silicon substrate; the depth of the groove is extremely shallow due to the extremely thin thickness of the oxide layer; the depth of a sigma trench obtained by wet etching of the groove is also extremely shallow; the thickness of a subsequently formed germanium-silicon epitaxial layer is thin, which is beneficial to further improve the response speed of the semiconductor device; in addition, a high selectivity etching is selected in the process of etching to remove the oxide layer, so that the etching process is stopped on the surface of the silicon substrate; compared with the prior art which usually controls the etching time to end the etching process, the etching method can obtain multiple sigma trenches with uniform depth in one device, thereby improving the reliability and yield of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, specifically to a method for manufacturing a sigma trench structure and a method for manufacturing semiconductor devices. Background Technology

[0002] With the miniaturization of CMOS technology, a larger drive current is needed to improve device response speed. To increase the drive current, germanium-silicon epitaxy technology is widely used in the semiconductor device manufacturing field. In germanium-silicon epitaxy technology, the size of the Σ(sigma) trench structure is a key factor affecting device performance (such as drive current).

[0003] In existing technologies, such as Figures 1a-1b As shown, the formation of sigma trench structures typically begins with dry etching to initially obtain a U-shaped trench 100, followed by wet etching to obtain a Σ-shaped trench 200. Therefore, the depth of the Σ-shaped trench 200 largely depends on the depth of the U-shaped trench 100 obtained by dry etching. However, the depth of the U-shaped trench 100 obtained by dry etching usually depends on the etching time, making it difficult to achieve uniform depth across multiple sigma trenches in a single device. Furthermore, because the etching rate and etching depth are related in dry etching processes, it is difficult to accurately control the etching depth through etching time. The depth of sigma trenches obtained by existing dry etching processes is typically... to It is difficult to obtain shallow sigma trenches, but shallow sigma trenches can help improve the overall response speed of the device. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention proposes a method for manufacturing a sigma trench structure and a method for manufacturing a semiconductor device.

[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a sigma trench structure, the method specifically comprising the following steps:

[0006] A silicon substrate is provided, on which a gate structure is disposed;

[0007] An oxide layer is formed between the gate structures by thermal oxidation. The oxide layer includes an initial layer and a thickening layer located at the bottom of the initial layer. The thickening layer is formed in the silicon substrate and its upper surface is flush with the surface of the silicon substrate.

[0008] The oxide layer is removed by high-selectivity etching to form a groove in the silicon substrate;

[0009] The grooves are formed by wet etching, thereby obtaining the preset depth of the sigma trenches by controlling the thickness of the oxide layer.

[0010] Optionally, it further includes: forming a first hard mask layer on top of the gate structure, forming first sidewalls on both sides of the gate structure; forming a second hard mask layer, the second hard mask layer covering the surfaces of the first hard mask layer and the first sidewalls, as well as the surface of the silicon substrate outside the gate structure.

[0011] Optionally, before forming the oxide layer between the gate structures, the method further includes: dry etching to remove a second hard mask layer covering the surface of the silicon substrate, exposing the silicon substrate outside the gate structures.

[0012] Optionally, the gate structure includes a gate dielectric layer and polysilicon located on the surface of the gate dielectric layer.

[0013] Optionally, the material of the first hard mask layer is silicon nitride.

[0014] Optionally, the material of the first sidewall is silicon nitride.

[0015] Optionally, the second hard mask layer is formed by stacking a silicon dioxide material layer and a silicon nitride material layer.

[0016] Optionally, the dry etching further includes removing the second hard mask layer covering the surface of the first hard mask layer, while retaining the second hard mask layer covering the surface of the first sidewall to form a second sidewall.

[0017] Optionally, the thermal oxidation method is performed at a temperature of 915℃ to 950℃, a processing time of 10s to 45s, and an oxygen flow rate of 2L / min to 9.5L / min.

[0018] Optionally, the oxide layer is made of silicon dioxide.

[0019] Optionally, the solution used in the wet etching process is tetramethylammonium hydroxide solution.

[0020] Optionally, the thickness of the oxide layer is

[0021] Optionally, the depth of the sigma trench is

[0022] Optionally, the thickness ratio of the thickened layer to the initial layer is 9:11.

[0023] Optionally, the bottom surface of the sigma trench is located in the (100) crystal plane of the silicon substrate, and the other surfaces of the sigma trench are located in the (111) crystal plane of the silicon substrate. In the crystal plane.

[0024] Optionally, the etching gases used in the high selectivity etching include HF and NF3.

[0025] The present invention also provides a method for manufacturing a semiconductor device, wherein the method for manufacturing the semiconductor substrate device specifically includes the following steps:

[0026] The manufacturing method of the sigma trench structure as described in any one of claims 1-16 is adopted;

[0027] Germanium-silicon epitaxial growth is performed in the sigma trench to form a germanium-silicon epitaxial layer.

[0028] The manufacturing method of the sigma trench structure and the manufacturing method of the semiconductor device of the present invention have at least the following beneficial effects:

[0029] In the manufacturing method of the sigma trench structure provided by the present invention, a very thin oxide layer is formed between the gate structures using thermal oxidation, and the oxide layer forms a thickening layer in the silicon substrate. The oxide layer is removed by etching, and a trench is formed in the silicon substrate. The depth of the trench is the same as the thickness of the thickening layer. Since the oxide layer is extremely thin, the trench is extremely shallow. The sigma trench obtained by wet etching of the trench is also extremely shallow. The thickness of the subsequently formed germanium-silicon epitaxial layer is relatively thin, which is beneficial to further improve the response speed of the semiconductor device. In addition, a high selectivity etching process is used during the etching process to remove the oxide layer, so that the etching process stops at the surface of the silicon substrate. Compared with the prior art, which commonly ends the etching process by controlling the etching time, this etching method can obtain multiple sigma trenches with uniform depth in one device, thereby improving the reliability and yield of the semiconductor device. Attached Figure Description

[0030] Figures 1a-1b The diagram shown is a schematic of the manufacturing of sigma trench structures in the prior art.

[0031] Figure 2 The diagram shown is a manufacturing process flow chart of the sigma trench structure provided in Example 1.

[0032] Figures 3-8 The diagram shows the structure formed in steps S1 to S4 of Embodiment 1.

[0033] Figure 9 The diagram shows a schematic of the semiconductor device formed in Example 2.

[0034] Component designation explanation

[0035] 100 U-shaped trench 222 silicon nitride material layer

[0036] 200 ∑-shaped trench 31 First sidewall

[0037] 10 Silicon substrate 32 Second sidewall

[0038] 11 Gate structure 12 Oxide layer

[0039] 111 Gate dielectric layer 121 Initial layer

[0040] 112 Polycrystalline Silicon 122 Thickened Layer

[0041] 21 First hard mask layer 13 Groove

[0042] 22 Second hard mask layer 14 Sigma trench

[0043] 221 Silica material layer Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0046] Example 1

[0047] This embodiment provides a method for manufacturing a sigma trench structure, such as Figure 2 As shown, it includes the following steps:

[0048] Step S1: Provide a silicon substrate, on which a gate structure is disposed;

[0049] like Figure 3 As shown, a silicon substrate 10 is provided. The silicon substrate 10 may contain various doped regions according to design requirements known in this art. The processes for forming the doped regions can all be implemented using existing process technologies, which will not be described in detail here.

[0050] Next, a gate structure 11 is formed on the surface of the silicon substrate 10. The gate structure 11 includes a gate dielectric layer 111 and polysilicon 112 located on the surface of the gate dielectric layer 111. The gate dielectric layer 111 is a gate oxide layer or a high dielectric constant layer.

[0051] Next, silicon nitride layers are formed on the top and sides of the gate structure 11. The silicon nitride layer covering the top of the gate structure 11 is the first hard mask layer 21, and the silicon nitride layers formed on both sides of the gate structure 11 are the first sidewalls 31.

[0052] Step S2: An oxide layer is formed between the gate structures by thermal oxidation. The oxide layer includes an initial layer and a thickening layer located at the bottom of the initial layer. The thickening layer is formed in the silicon substrate and its upper surface is flush with the surface of the silicon substrate.

[0053] First, a silicon dioxide material layer 221 and a silicon nitride material layer 222 are sequentially deposited on a silicon substrate 10 using chemical vapor deposition, such as... Figure 4 As shown, a silicon dioxide material layer 221 and a silicon nitride material layer 222 are stacked to form a second hard mask layer 22. The second hard mask layer 22 covers the surfaces of the first hard mask layer 21 and the first sidewall 31, as well as the surface of the silicon substrate outside the gate structure.

[0054] Next, dry etching is performed using the silicon nitride material layer 222 as a stop layer to remove the silicon nitride material layer 222 formed on the top of the gate structure 11 and the silicon nitride material layer 222 formed on the surface of the silicon substrate 10. Since this etching is anisotropic, most of the silicon nitride material layers 222 on both sides of the gate structure 11 are retained, but their horizontal thickness is reduced to some extent. During the etching process, the silicon dioxide material layer 221 protects the first hard mask layer 21 and the first sidewall 31, preventing a reduction in the thickness of the first hard mask layer 21 and the first sidewall 31 at the apex of the gate structure 11.

[0055] Next, dry etching is performed using the silicon dioxide material layer 221 as a stop layer to remove the silicon dioxide material layer 221 formed on top of the gate structure 11 and the silicon dioxide material layer 221 formed on the surface of the silicon substrate 10. The silicon dioxide material layer 221 and the silicon nitride material layer 222 formed on both sides of the first sidewall 31 are retained and stacked to form the second sidewall 32, forming Figure 5 The structure shown.

[0056] As an example, the above-mentioned dry etching uses plasma etching, and the etching gas includes gases containing fluorocarbons, such as CF4, CHF3, etc., as well as other commonly used etching gases such as O2, N2, etc. In another optional embodiment of this example, the above-mentioned dry etching can also use ion beam etching, and the etching gas can be an inert gas such as Ar, He, etc.

[0057] Next, an oxide layer 12 is formed between the gate structures 11 by thermal oxidation. The thickness of the oxide layer 12 is related to the processing conditions. In this embodiment, the processing temperature of the thermal oxidation method is 915℃~950℃, the processing time is 10s~45s, and the oxygen flow rate is 2L / min~9.5L / min. Within this range, the higher the processing temperature, the longer the processing time, and the higher the oxygen flow rate, the thicker the oxide layer 12 is. In addition, a small amount of hydrogen is added to the oxygen as a reaction atmosphere. Under high temperature, oxygen and hydrogen react chemically to generate a large number of gaseous active free radicals, mainly atomic oxygen. Under the strong oxidizing effect of atomic oxygen, an ultra-thin oxide layer can be obtained. The thickness of the oxide layer is crucial for the formation of shallow sigma trenches in subsequent processes. During the growth of the oxide layer by thermal oxidation, by controlling the process conditions such as processing temperature, processing time, and oxygen flow rate, a stable and controllable oxide layer can be obtained. In this embodiment, the thickness of the oxide layer 12 is...

[0058] During the thermal oxidation process, oxygen atoms first react with silicon atoms on the surface of the silicon substrate 10 to form an initial layer 121. Subsequently, the initial layer 121 prevents oxygen atoms from directly contacting silicon atoms on the substrate surface. Oxygen atoms diffuse through the initial layer 121 to the interface between the initial layer 121 and the silicon substrate 10, where they continue to react with silicon atoms to form a thickening layer 122. Figure 6 As shown, as an example, the thickness ratio of the thickened layer 122 to the initial layer 121 is 9:11. The thickened layer 122 is formed in the silicon substrate 10, and its upper surface is flush with the surface of the silicon substrate 10. As an example, the material of the oxide layer 12 is silicon dioxide.

[0059] In another optional embodiment of this example, the oxide layer 12 can also be formed by natural oxidation. The oxide layer 12 generated by natural oxidation also includes an initial layer 121 and a thickening layer 122. Its formation process is the same as that of thermal oxidation. However, compared with thermal oxidation, thermal oxidation can quickly obtain an ultra-thin oxide layer in a short time. Therefore, thermal oxidation is a more preferred method in actual production.

[0060] Step S3: Remove the oxide layer by high selectivity etching to form a groove in the silicon substrate;

[0061] like Figure 7As shown, reactive ion etching is used for high-selectivity etching, with the silicon substrate 10 as the stop layer, to remove the oxide layer 12 and form a groove 13 in the silicon substrate. As an example, the etching gas used in the high-selectivity etching is mainly a mixture of HF and NF3. High-selectivity etching has a high silicon dioxide to silicon etching rate ratio, allowing the etching to stop at the surface of the silicon substrate, protecting the silicon substrate 10 from further etching. Compared with the commonly used method in the prior art of controlling the etching time to end the etching process, the etching method used in this embodiment can improve the uniformity of etching, mainly manifested in the uniform depth of multiple grooves 13 obtained in a single device.

[0062] Step S4: Wet etching is used to form sigma trenches, the depth of which is...

[0063] like Figure 8 As shown, a silicon substrate 10 is wet-etched using tetramethylammonium hydroxide solution (TMAH) to form sigma trenches 14. The etching rate of the tetramethylammonium hydroxide solution (TMAH) varies in different crystal orientations. <100> Crystal orientation and <111> The etching selectivity ratio for silicon along the crystal plane can reach 40:1 to 70:1, thus enabling wet etching of silicon to stop at the (111) crystal plane and... Sigma trench 14 is formed on the crystal surface (the side surface of sigma trench 14). For example... Figure 6 and Figure 7 As shown, the (111) crystal plane and All crystal planes are cut surfaces of the vertices of the grooves 13 formed by the second dry etching, and the (111) crystal plane and The sigma trench 14 is formed at the junction of the crystal planes. Therefore, the final depth of the sigma trench 14 largely depends on the depth of the groove 13. Since a thin oxide layer 12 is formed by thermal oxidation in step S4, the groove 13 formed in step S5 is shallower, ultimately resulting in a shallower sigma trench 14. In this embodiment, the depth of the sigma trench 14 is...

[0064] In the manufacturing method of the sigma trench structure provided in this embodiment, a very thin oxide layer is formed between the gate structures using thermal oxidation, and the oxide layer forms a thickening layer in the silicon substrate. The oxide layer is removed by etching, forming a trench in the silicon substrate. The depth of the trench is the same as the thickness of the thickening layer. Since the oxide layer is extremely thin, the trench is extremely shallow. The sigma trench obtained by wet etching of the trench is also extremely shallow, which helps to improve the overall response speed of the device. In addition, high selectivity etching is used during the etching process to remove the oxide layer, so that the etching process stops at the surface of the silicon substrate. Compared with the prior art, which commonly ends the etching process by controlling the etching time, this etching method can obtain multiple sigma trenches with uniform depth in one device, improving the uniformity of etching.

[0065] Example 2

[0066] This embodiment also provides a method for manufacturing a semiconductor device, including the following steps:

[0067] Step S101: Provide a one-sigma trench structure;

[0068] As an example, the sigma trench structure used in this embodiment is obtained by the manufacturing method of the sigma trench structure provided in Embodiment 1. Please refer to the description of Embodiment 1 for details, which will not be repeated here.

[0069] Step S102: Perform germanium-silicon epitaxial growth in the sigma trench to form a germanium-silicon epitaxial layer;

[0070] First, use a cleaning agent to remove the oxides at the bottom of the Sigma trench 14. The cleaning agent can be a diluted hydrofluoric acid solution or other suitable solution.

[0071] Next, a germanium-silicon epitaxial layer is grown in the sigma trench 14 using a selective epitaxial process. As an example, the selective epitaxial process can be ultra-high vacuum chemical vapor deposition (UHVCVD) or molecular beam epitaxy (MEB). In this embodiment, an ultra-high vacuum chemical vapor deposition process is used to form a germanium-silicon epitaxial layer 15 in the sigma trench 14. The reaction gases include SiH2Cl2, HCl, and GeH4.

[0072] like Figure 9As shown, the shape of the germanium-silicon epitaxial layer 15 matches the shape of the sigma trench 14. Since the lattice constant of germanium-silicon is greater than that of silicon, the germanium-silicon epitaxial layer 15 can generate compressive stress in the sigma trench 14, increasing the driving current of the semiconductor device and thus improving the response speed of the semiconductor device. The quality of the germanium-silicon epitaxial layer depends on the shape of the sigma trench. The fabrication of the sigma trench structure is a crucial step in the entire process. The semiconductor device fabrication method provided in this embodiment is based on the sigma trench structure fabrication method provided in Embodiment 1. Therefore, the germanium-silicon epitaxial layer in the semiconductor device obtained in this embodiment is thinner and more uniform, which is beneficial for further improving the response speed and stability of the device.

[0073] In summary, in the manufacturing method of the sigma trench structure provided by the present invention, a very thin oxide layer is formed between the gate structures using thermal oxidation, and the oxide layer forms a thickening layer in the silicon substrate. The oxide layer is removed by etching, forming a trench in the silicon substrate. The depth of the trench is the same as the thickness of the thickening layer. Because the oxide layer is extremely thin, the trench is extremely shallow. The sigma trench obtained by wet etching of the trench is also extremely shallow. The thickness of the subsequently formed germanium-silicon epitaxial layer is relatively thin, which is beneficial to further improve the response speed of the semiconductor device. In addition, a high selectivity etching process is used during the etching process to remove the oxide layer, so that the etching process stops at the surface of the silicon substrate. Compared with the prior art, which commonly ends the etching process by controlling the etching time, this etching method can obtain multiple sigma trenches with uniform depth in one device, thereby improving the reliability and yield of the semiconductor device.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a sigma trench structure, characterized in that, include: A silicon substrate is provided, on which a gate structure is disposed; An oxide layer is formed between the gate structures by thermal oxidation. The oxide layer includes an initial layer and a thickening layer located at the bottom of the initial layer. The thickening layer is formed in the silicon substrate and its upper surface is flush with the surface of the silicon substrate. The oxide layer is removed by high-selectivity etching to form a groove in the silicon substrate; The grooves are formed by wet etching to create sigma trenches, thereby controlling the thickness of the oxide layer to obtain a preset depth of sigma trenches, wherein the depth of the sigma trenches is 10 Å to 30 Å.

2. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, Also includes: A first hard mask layer is formed on top of the gate structure, and first sidewalls are formed on both sides of the gate structure. A second hard mask layer is formed, which covers the surfaces of the first hard mask layer and the first sidewall, as well as the surface of the silicon substrate outside the gate structure.

3. The method for manufacturing a sigma trench structure according to claim 2, characterized in that, The method further includes the following steps before forming the oxide layer between the gate structures: Dry etching removes the second hard mask layer covering the surface of the silicon substrate, exposing the silicon substrate outside the gate structure.

4. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The gate structure includes a gate dielectric layer and polysilicon located on the surface of the gate dielectric layer.

5. The method for manufacturing a sigma trench structure according to claim 2, characterized in that, The material of the first hard mask layer is silicon nitride.

6. The method for manufacturing a sigma trench structure according to claim 2, characterized in that, The material of the first sidewall is silicon nitride.

7. The method for manufacturing a sigma trench structure according to claim 2, characterized in that, The second hard mask layer is formed by stacking a silicon dioxide material layer and a silicon nitride material layer.

8. The method for manufacturing a sigma trench structure according to claim 3, characterized in that, The dry etching process further includes removing the second hard mask layer covering the surface of the first hard mask layer, while retaining the second hard mask layer covering the surface of the first sidewall to form the second sidewall.

9. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The thermal oxidation method has a processing temperature of 915℃~950℃, a processing time of 10s~45s, and an oxygen flow rate of 2L / min~9.5L / min.

10. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The oxide layer is made of silicon dioxide.

11. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The solution used in the wet etching process is tetramethylammonium hydroxide solution.

12. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The thickness of the oxide layer is 10 Å to 20 Å.

13. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The thickness ratio of the thickened layer to the initial layer is 9:

11.

14. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The bottom surface of the sigma trench lies in the (100) crystal plane of the silicon substrate, and the other surfaces of the sigma trench lie in the (111) and (11) crystal planes of the silicon substrate. In the crystal plane.

15. The method for manufacturing a sigma trench structure according to claim 1, characterized in that, The etching gases used in the high selectivity etching include HF and NF3.

16. A method for manufacturing a semiconductor device, characterized in that, include: The manufacturing method of the sigma trench structure as described in any one of claims 1-15 is adopted; Germanium-silicon epitaxial growth is performed in the sigma trench to form a germanium-silicon epitaxial layer.

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