Method for manufacturing a power device and power device

Abstract

The embodiment of the present application relates to a preparation method of a power device and the power device, and the method comprises the following steps: forming a first groove extending from a first surface of a semiconductor substrate to the inside of the semiconductor substrate in a first region of the first surface; forming an insulating isolation layer on the side wall and the bottom wall of the first groove; forming a filling semiconductor layer in the insulating isolation layer; forming a photoelectric conversion device on the filling semiconductor layer; forming a source electrode and a gate electrode of a transistor in a second region of the first surface, and forming a drain electrode of the transistor on a second surface; wherein the gate electrode of the transistor is used for receiving an electrical signal from the photoelectric conversion device; thus, the photoelectric conversion device and the transistor are integrated on the same substrate, the device performance is good, the overall preparation process of the device is simple, and the preparation cost is low.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a power device and the power device itself. Background Technology

[0002] Considering the safety issues of driving power devices in various situations, isolated drive circuits are typically required for power devices. Currently, power devices are generally used as discrete components, requiring additional external drive circuits in practical applications. This undoubtedly leads to a larger number of circuit components, increased circuit area and volume, and increased design complexity. In existing high-voltage applications, drive circuits generally use electrical isolation to address oscillations caused by control circuits on the gate of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and safety issues related to the application circuit. Isolation is generally achieved through three methods: optocouplers, magnetic coupling, and capacitive coupling. Currently, optocouplers are widely used; among them, photovoltaic output optocouplers use a packaged form that integrates the infrared LED chip, photovoltaic output chip, and MOSFET chip.

[0003] The fabrication of PDAs (Photo-Diode Arrays) using photovoltaic (PV) output chips typically requires high-quality substrates. Due to the need for isolation techniques, SOI (Silicon-on-Insulator) substrates are generally used. On one hand, the cost of SOI substrates is more than twice that of ordinary epitaxial wafers, undoubtedly increasing the device fabrication cost. On the other hand, due to the structural characteristics of SOI substrates, vertical power devices, such as superjunction MOSFETs, cannot be fabricated using SOI substrates in this field. This increases the technical difficulty of integrating PV output chips and MOSFET chips onto the same substrate. Although some related technologies have proposed solutions for fabricating both PV output chips and MOSFET chips on the same substrate, the processes are complex or difficult to operate, and the device performance and structural stability still need improvement. Summary of the Invention

[0004] In view of this, the present application provides a method for fabricating a power device and a power device to solve at least one problem existing in the background art.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a power device, the method comprising:

[0006] A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other;

[0007] A first trench is formed in a first region of the first surface, extending from the first surface into the interior of the semiconductor substrate;

[0008] An insulating layer is formed on the sidewalls and bottom wall of the first trench;

[0009] A semiconductor-filled layer is formed within the insulating isolation layer;

[0010] A photoelectric conversion device is formed on the filled semiconductor layer;

[0011] The source and gate of the transistor are formed in a second region of the first surface, and the drain of the transistor is formed on the second surface; wherein the gate of the transistor is electrically connected to the positive electrode of the photoelectric conversion device.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, providing the semiconductor substrate includes: providing a semiconductor substrate; and epitaxially growing an epitaxial layer on the semiconductor substrate;

[0013] The first surface is the upper surface of the epitaxial layer, and the second surface is the lower surface of the semiconductor substrate; the bottom wall of the first trench is located within the epitaxial layer.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, the semiconductor substrate is made of a single-crystal semiconductor material; and the filling semiconductor layer is made of a polycrystalline semiconductor material.

[0015] In conjunction with a first aspect of this application, in an alternative embodiment, the first trench and the drain of the transistor at least partially overlap in the thickness direction of the semiconductor substrate.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the transistor is a superjunction MOSFET; before forming the first trench, the method further includes:

[0017] A plurality of second trenches are formed in a second region of the first surface, extending from the first surface into the interior of the semiconductor substrate, the plurality of second trenches being spaced apart;

[0018] Semiconductor pillars are epitaxially grown inside and outside a plurality of second trenches, the conductivity type of the semiconductor pillars being opposite to that of the semiconductor substrate.

[0019] In conjunction with the first aspect of this application, in an optional embodiment, a photoelectric conversion device is formed on the filled semiconductor layer, comprising:

[0020] The first region on the filled semiconductor layer is doped to form a negative electrode, and the second region on the filled semiconductor layer is doped to form a positive electrode.

[0021] Secondly, embodiments of this application provide a power device, including:

[0022] A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other;

[0023] A first trench is located in a first region of the first surface and extends from the first surface into the interior of the semiconductor substrate;

[0024] An insulating layer covers the sidewalls and bottom wall of the first trench;

[0025] A semiconductor layer is filled within the insulating isolation layer;

[0026] A photoelectric conversion device is formed on the filled semiconductor layer;

[0027] A transistor includes a source, a drain, and a gate, wherein the source and the gate are located in a second region of a first surface, and the drain is located on the second surface; wherein the gate is electrically connected to the positive electrode of the photoelectric conversion device.

[0028] In conjunction with a second aspect of this application, in an optional embodiment, the semiconductor substrate includes a semiconductor substrate and an epitaxial layer located on the semiconductor substrate;

[0029] The first surface is the upper surface of the epitaxial layer, and the second surface is the lower surface of the semiconductor substrate; the bottom wall of the first trench is located within the epitaxial layer.

[0030] In conjunction with the second aspect of this application, in an optional embodiment, the semiconductor substrate is made of a single-crystal semiconductor material; and the filling semiconductor layer is made of a polycrystalline semiconductor material.

[0031] In conjunction with a second aspect of this application, in an alternative embodiment, the first trench and the drain of the transistor at least partially overlap in the thickness direction of the semiconductor substrate.

[0032] In conjunction with a second aspect of this application, in an optional embodiment, the transistor is a superjunction MOSFET; the transistor further includes:

[0033] A plurality of spaced semiconductor pillars are located in a second region of the first surface and extend from the first surface into the interior of the semiconductor substrate, wherein the conductivity type of the semiconductor pillars is opposite to that of the semiconductor substrate.

[0034] In conjunction with a second aspect of this application, in an optional embodiment, the photoelectric conversion device includes a photosensitive area, a positive electrode, and a negative electrode.

[0035] The power device fabrication method and power device provided in this application embodiment involve forming a first trench extending from the first surface to the interior of the semiconductor substrate in a first region on the first surface of the semiconductor substrate; forming an insulating isolation layer on the sidewalls and bottom wall of the first trench; forming a filled semiconductor layer within the insulating isolation layer; forming a photoelectric conversion device on the filled semiconductor layer; forming the source and gate of a transistor in a second region on the first surface; and forming the drain of a transistor on the second surface. The gate of the transistor is used to receive electrical signals from the photoelectric conversion device. Thus, the first trench for integrating the photoelectric conversion device extends to the interior of the semiconductor substrate, which can be achieved using commonly used etching processes in the art, resulting in low operational difficulty and high structural stability. The first trench and insulating isolation layer effectively prevent the transistor from affecting the photoelectric conversion device, truly achieving the integration of the photoelectric conversion device and the transistor on the same substrate, resulting in better device performance. The overall fabrication process of the device is simple and the fabrication cost is low.

[0036] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0037] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0038] Figure 1 A schematic flowchart illustrating the fabrication method of the power device provided in the embodiments of this application;

[0039] Figures 2 to 14 A cross-sectional structural diagram of the power device provided in the embodiments of this application during the fabrication process;

[0040] Figure 15 This is a layout diagram of the power device in a specific example of this application;

[0041] Figure 16 This is a top view of a power device in a specific example of this application;

[0042] Figure 17 This is a schematic diagram illustrating the application scenario of the power device in a specific example of this application;

[0043] Figure 18 This is a circuit diagram of a power device in a specific example of this application;

[0044] Figure 19 This is a circuit diagram of a PDA in a specific example of this application. Detailed Implementation

[0045] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0052] This application provides a method for fabricating a power device. Please refer to the following embodiments. Figure 1 The method includes:

[0053] Step S01, providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other;

[0054] Step S02: A first trench is formed in a first region of the first surface, extending from the first surface into the interior of the semiconductor substrate;

[0055] Step S03: An insulating layer is formed on the sidewalls and bottom wall of the first trench;

[0056] Step S04: Form a filled semiconductor layer within the insulating isolation layer;

[0057] Step S05: Form a photoelectric conversion device on the filled semiconductor layer;

[0058] Step S06: The source and gate of the transistor are formed in the second region of the first surface, and the drain of the transistor is formed on the second surface.

[0059] Step S07: Connect the gate of the transistor to the positive electrode of the photoelectric conversion device.

[0060] Understandably, in order to integrate the photoelectric conversion device, a first trench is first formed, which extends from the first surface of the semiconductor substrate to the interior of the semiconductor substrate. This can be achieved using the etching process commonly used in the art, which is relatively simple. The semiconductor substrate remains connected to the second surface and the surrounding area, resulting in high structural stability of the final device. An insulating isolation layer is formed on the sidewalls and bottom wall of the first trench. By utilizing the first trench and the insulating isolation layer, the influence of the transistor on the photoelectric conversion device is effectively avoided. This truly realizes the integration of the photoelectric conversion device and the transistor on the same substrate, resulting in better device performance. The overall fabrication process of the device is simple and the fabrication cost is low.

[0061] Below, in conjunction with Figures 2 to 14 The schematic diagram of the cross-sectional structure of the power device shown in the fabrication process provides a further detailed explanation of the technical solution of this application.

[0062] First, please refer to Figure 2 Step S01 is performed, providing a semiconductor substrate 100, which includes a first surface 101 and a second surface 102 that are opposite to each other.

[0063] In the embodiments of this application, the term "substrate" refers to a carrier on which subsequent material layers are added, which can be a growth substrate or include epitaxial layers. Ignoring the flatness of the first surface 101 and the second surface 102, the plane containing the first surface 101 and the second surface 102 of the semiconductor substrate 100, or strictly speaking, the center plane in the thickness direction of the semiconductor substrate 100, is defined as the substrate plane; the direction parallel to the substrate plane is the plane direction along the substrate. The direction perpendicular to the substrate plane is the thickness direction of the semiconductor substrate 100, or the height direction of the device, or the depth direction of each region; the thickness direction of the semiconductor substrate 100 is also the stacking direction for subsequent deposition of material layers on the semiconductor substrate 100.

[0064] To better meet the requirements for transistor formation, the semiconductor substrate 100 can be made of a single-crystal semiconductor material; specifically, for example, single-crystal silicon. Of course, this application does not exclude the use of semiconductor substrates made of materials such as single-crystal germanium.

[0065] In order to form transistors with vertical structures, SOI substrates are not used in the embodiments of this application.

[0066] According to design requirements, a first region 1011 and a second region 1012 can be defined on the first surface 101 of the semiconductor substrate 100. The first region 1011 is the region for forming a photoelectric conversion device; the second region 1012 is the region for forming a transistor. Figure 15 A layout diagram of the power device in a specific example is shown. As shown, a PDA is arranged on a first region 1011 of the first surface 101, and a superjunction MOSFET is arranged on a second region 1012 of the first surface 101.

[0067] In one specific implementation, a semiconductor substrate 100 may be provided, which may include: providing a semiconductor substrate 110; and epitaxially growing an epitaxial layer 120 on the semiconductor substrate 110. Specifically, the first surface 101 is the upper surface of the epitaxial layer 120, and the second surface 102 is the lower surface of the semiconductor substrate 110.

[0068] Taking an N-type MOSFET with a superjunction structure as an example, the semiconductor substrate 100 includes an N-type heavily doped (n+) semiconductor substrate 110 and an N-type doped epitaxial layer 120. The thickness and doping concentration of the epitaxial layer 120 are determined based on the MOSFET's breakdown voltage, trench etching depth, and desired resistance value. In a specific application, the thickness of the epitaxial layer 120 is 40 micrometers to 60 micrometers.

[0069] Next, please refer to Figures 3 to 4 This forms the superjunction portion of the superjunction MOSFET.

[0070] Super Junction MOSFET (SJMOSFET) devices are an important type of power device that has emerged in recent years. Its basic principle is the charge balance principle. By introducing a super junction structure with spaced P-pillars and N-pillars into the drift region of a conventional power MOSFET, the trade-off between the on-resistance and breakdown voltage of a conventional MOSFET is greatly improved.

[0071] It should be understood that Figures 2 to 14 Although an SJMOSFET is used as an example transistor, the power device and its fabrication method provided in this application are obviously also applicable to ordinary MOSFETs, such as VDMOSFETs (Vertical Double-diffused MOSFETs); and, not limited to MOSFETs, if the actual device has other requirements, the transistor can also be other types of transistors such as IGBTs (Insulated Gate Bipolar Transistors). This application specifically applies to vertical power devices that can use photoelectric conversion devices as driving circuits.

[0072] Please refer to the details. Figure 3 In an embodiment where the transistor is an SJMOSFET, the method further includes forming a plurality of second trenches 200 extending from the first surface 101 to the interior of the semiconductor substrate 100 in a second region 1012 of the first surface 101, the plurality of second trenches 200 being spaced apart.

[0073] For example, a second trench 200 of a certain depth is etched on the epitaxial layer 120, the depth of the second trench 200 being less than the thickness of the epitaxial layer 120. The second trench 200 extends from the first surface 101 into the interior of the epitaxial layer 120; the bottom wall of the second trench 200 is located in the epitaxial layer 120.

[0074] The second trench 200 can be formed using photolithography, a process commonly used in the art. This involves first coating, exposing, and developing a patterned photoresist layer on the first surface 101, then using the patterned photoresist layer as a mask to etch the semiconductor substrate 100, thereby forming the second trench 200. The second trench 200 is used in subsequent processes to form the superjunction portion; the etching window of the superjunction portion is determined by the width of the superjunction cell.

[0075] Next, please refer to Figure 4 Semiconductor pillars 210 are epitaxially grown inside and outside multiple second trenches 200, and the conductivity type of the semiconductor pillars 210 is opposite to that of the semiconductor substrate 100.

[0076] For example, the semiconductor substrate 100 is an N-type substrate, and the semiconductor pillars 210 are P-type doped. Therefore, the semiconductor pillars 210 can also be referred to as P-pillars, and the portion of the semiconductor substrate 100 between two adjacent P-pillars can also be referred to as N-pillars; the P-pillars and N-pillars are arranged alternately along the planar direction of the substrate. A set of P-pillars and N-pillars forms a basic SJMOSFET cell and is arranged laterally in parallel in the semiconductor substrate 100.

[0077] The semiconductor pillar 210 grows epitaxially along the crystal orientation of the sidewall of the second trench 200 and eventually fills the second trench 200, forming a superjunction structure of the SJMOSFET. It is easy to understand that when the semiconductor substrate 100 is made of a single-crystal semiconductor material, the epitaxially grown semiconductor pillar 210 is also made of a single-crystal semiconductor material.

[0078] Although Figures 3 to 4 The illustration shows that P-pillars are formed by grooving and epitaxial filling. However, this application does not exclude the possibility of forming P-pillars by first forming a thin epitaxial layer on the semiconductor substrate 100, followed by multiple epitaxial layers, implantation of P-type regions, and annealing. Both methods are conventional processes in the art and will not be described in detail here.

[0079] Next, please refer to Figure 5 In step S02, a first trench 300 is formed in a first region 1011 of the first surface 101, extending from the first surface 101 into the interior of the semiconductor substrate 100.

[0080] For example, a first trench 300 of a certain depth is etched on the epitaxial layer 120, the depth of the first trench 300 being less than the thickness of the epitaxial layer 120. The first trench 300 extends from the first surface 101 into the interior of the epitaxial layer 120; the bottom wall of the first trench 300 is located within the epitaxial layer 120.

[0081] The first trench 300 is used in subsequent processes to form the photoelectric conversion device. In specific applications, there can be multiple photoelectric conversion devices, which are isolated from each other and connected in series to form a photoelectric conversion device array. Specifically, the photoelectric conversion device can be a photodiode, and multiple photodiodes are connected in series to form a PDA. The depth of the first trench 300 can be determined by the width of each photodiode in the photodiode array; the depth of the first trench 300 can be less than or equal to the depth of the second trench 200. In specific processes, the depth of the first trench 300 is 20 micrometers to 30 micrometers.

[0082] The first trench 300 can be achieved using etching processes commonly used in the art. Compared to etching through the semiconductor substrate 100, forming only a trench extending inward from the first surface 101, the etching difficulty is greatly reduced. It is easy to understand that in conventional techniques for fabricating photoelectric conversion devices using SOI substrates, annular isolation trenches are generally used to achieve electrical isolation between internal and external devices. The bottom of the annular isolation trench is etched down to the buried oxide layer in the SOI substrate, thus the annular isolation trench acts as a sidewall, and the buried oxide layer acts as a bottom wall, forming a closed isolation region. However, in cases where an SOI substrate is not used, even if an isolation trench is formed as in conventional techniques, the bottom of the substrate remains connected, making complete electrical isolation impossible. To form a completely isolated region, one option is to etch the isolation trench all the way to the second surface of the substrate, thereby forming an island region within the annular isolation trench, and using the substrate material within the island region to fabricate the photoelectric conversion device. Given the typically thick substrates and the need to minimize the linewidth of annular isolation trenches to avoid occupying a large area, the aspect ratio of these trenches is very high, posing significant challenges to the etching process. Furthermore, the etching process becomes increasingly difficult as it progresses downwards; if some areas remain unetched near the second surface of the substrate, isolation failure will occur, reducing product yield. Moreover, even if all areas are etched through, while the electrical isolation problem is solved, the isolated islands remain completely separated from the rest of the substrate. Even after the isolation trenches are filled with an insulating dielectric material, the structural stability still faces considerable risks.

[0083] In this embodiment, the first trench 300 extends into the interior of the semiconductor substrate 100, and its formation process can employ photolithography, a process commonly used in the art. Specifically, for example, a patterned photoresist layer is first formed by coating, exposing, and developing a photoresist layer on the first surface 101, and then using the patterned photoresist layer as a mask to etch the semiconductor substrate 100, thereby forming the first trench 300. All the single-crystal material within the first trench 300 is hollowed out, thus forming a columnar-like empty trench. The location of the photoelectric conversion device will be explained in detail in the following steps.

[0084] Optionally, the first trench 300 and the second trench 200 can be formed in the same etching process. However, in order to better control the actual trench depth, this embodiment uses separate etching to form the first trench 300 and the second trench 200. Furthermore, the second trench 200 is formed before the first trench 300 is formed, and semiconductor pillars 210 are epitaxially grown inside and outside the second trench 200, which helps to save steps.

[0085] Next, please refer to Figure 6 Step S03 is performed to form an insulating layer 310 on the sidewalls and bottom wall of the first trench 300.

[0086] In the specific process, the semiconductor substrate 100 after etching the first trench 300 undergoes high-temperature annealing and field oxide layer growth. The thickness of the oxide layer needs to meet the rated voltage value of the transistor; optionally, its thickness is greater than 800 nm. Thus, a field oxide layer 400 is formed on the first surface 101, and an insulating isolation layer 310 is formed on the sidewalls and bottom wall of the first trench 300. Of course, the material of the insulating isolation layer 310 is not limited to oxides; other materials suitable for achieving electrical isolation can also be used.

[0087] It should be understood that the insulating isolation layer 310 formed in step S03 covers all inner surfaces of the first trench 300, thereby providing an electrically isolated region for the photoelectric conversion device formed in subsequent processes, preventing transistors formed on the same semiconductor substrate from affecting the photoelectric conversion device. Furthermore, in the case of a power device including a PDA composed of multiple photodiodes, the insulating isolation layer 310 formed on the sidewalls and bottom walls of each of the multiple first trenches 300 also provides an independent electrically isolated region for each photodiode, avoiding electrical interference between the photodiodes. It should also be understood that the insulating isolation layer 310 formed in step S03 does not completely fill the first trench 300, thus reserving space for the formation of the filling semiconductor layer 320 in the next process.

[0088] Next, please refer to Figure 7Step S04 is performed to form a filled semiconductor layer 320 within the insulating isolation layer 310.

[0089] The material of the filling semiconductor layer 320 is a polycrystalline semiconductor material; specifically, for example, polycrystalline silicon. The filling semiconductor layer 320 can be a doped semiconductor layer, such as a P-type semiconductor layer, specifically achieved by doping with boron ions. The concentration of the acceptor impurity is, for example, 1e⁻¹. 17 / cm 3 .

[0090] The filled semiconductor layer 320 provides a substrate for the subsequent fabrication of photoelectric conversion devices. Since the single crystal material in the first trench 300 in this embodiment is completely removed, it is impossible to use the single crystal material of the semiconductor substrate 100 itself to fabricate photoelectric conversion devices. Therefore, the inventors conceived of using a deposition process to form a filled semiconductor layer 320 in the first trench 300, and then using the filled semiconductor layer 320 as a substrate to fabricate photoelectric conversion devices.

[0091] Before proceeding to the next step, the method may further include etching away excess material filling the semiconductor layer 320 and the field oxide layer 400, thereby providing a smooth process surface for the next step. In specific fabrication, this step can be achieved using chemical mechanical polishing (CMP) or etching (ET) processes.

[0092] Next, steps S05 and S06 will be performed to complete the fabrication of the photoelectric conversion device and transistor.

[0093] This application does not impose specific limitations on the order of fabrication of the photoelectric conversion device and the transistor. It should be understood that, although... Figure 1 The steps are displayed sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; moreover, these steps are not necessarily performed sequentially. This application does not exclude the possibility that at least two steps are completed at the same time or are completed alternately. The execution order between steps should still be determined according to the specific logical relationship.

[0094] For example, please refer to the following: Figure 8 In order to form the source and gate of the transistor in the second region 1012 of the first surface 101, the excess field oxide layer 400 is first etched away, then the gate dielectric layer 221 is formed, and the gate 220 is formed on the gate dielectric layer 221.

[0095] The gate dielectric layer 221 can be a gate oxide layer, and its material is, for example, silicon oxide; the gate 220 is made of, for example, polysilicon.

[0096] The thickness of the gate dielectric layer 221 can be The thickness of the gate 220 can be approximately 400nm to 800nm.

[0097] After the gate dielectric material and the gate material are deposited sequentially on the first surface 101, the gate dielectric layer 221 and the gate 220 can be defined by an etching process; wherein, there is an opening between two adjacent gates 220 to expose the semiconductor pillar 210; the gate dielectric layer 221 is located between the gate 220 and the semiconductor substrate 100.

[0098] In addition, please continue to refer to Figure 8 In order to protect the gate 220, an insulating sidewall can be formed on the sidewall of the gate 220, and a protective layer can be formed on the upper surface of the gate 220.

[0099] It should be noted that, in an optional embodiment, the gate 220 and the filled semiconductor layer 320 can be co-deposited and formed in the same process. Specifically, please refer to... Figure 6 ,exist Figure 6 Following the steps shown, a step of depositing polysilicon material can be performed. On one hand, the polysilicon material fills the first trench 300 to form a filled semiconductor layer 320; on the other hand, the polysilicon material is deposited in the second region 1012 to form a gate 220. This saves process steps and reduces manufacturing costs.

[0100] Next, please refer to Figure 9 A body region 211 is formed in the region above the semiconductor pillar 210 within the semiconductor substrate 100.

[0101] The body region 211 can be formed by an ion implantation process. Specifically, ion implantation is performed by self-alignment, using the opening of the exposed semiconductor pillar 210 between two adjacent gates 220 as the implantation window. In a specific example where the transistor is an N-type MOSFET, a P-type impurity is implanted into the implantation window, and the lateral diffusion of the P-type impurity in the N-type region is promoted by high-temperature push junction, thereby forming the P-type body region of the MOSFET. At least a portion of the P-type body region is formed as the channel of the transistor.

[0102] Next, please refer to Figure 10 A predetermined region on the filled semiconductor layer 320 is doped to form the first electrode region 321 of the photoelectric conversion device.

[0103] Specifically, a portion of the field oxide layer 400 is removed to expose a portion of the upper surface of the filled semiconductor layer 320; ion implantation is then performed on the portion of the upper surface of the filled semiconductor layer 320 to form the first electrode region 321 of the photoelectric conversion device. The first electrode region 321 is, for example, an N-type electrode region (or cathode / negative electrode region); correspondingly, the ion implantation is N-type impurity implantation with a doping concentration of approximately 1e14 / cm³. 3 ~1e17 / cm 3 .

[0104] Next, please refer to Figure 11 The first electrode ohmic contact region 322 of the photoelectric conversion device and the source region 212 of the transistor are formed.

[0105] Specifically, a first region on the filled semiconductor layer 320 is doped to form a first electrode ohmic contact region 322. The first region is located within the first electrode region 321.

[0106] The first electrode ohmic contact region 322 and the source region 212 are specifically formed by ion implantation. In actual fabrication, the ion implantation window can be defined by photolithography. The first electrode ohmic contact region 322 and the source region 212 have the same conductivity type; therefore, they can be formed using the same ion implantation process.

[0107] For example, N+ type ion implantation is performed to form the first electrode ohmic contact region 322 and the source region 212 described above. The first electrode ohmic contact region 322 is also called the N-type ohmic contact region (or cathode / negative electrode).

[0108] Next, please refer to Figure 12 The second region on the filled semiconductor layer 320 is doped to form the second electrode ohmic contact region 323 of the photoelectric conversion device. Furthermore, a source ohmic contact region of the transistor (not shown in the figure) can also be formed.

[0109] Specifically, the second electrode ohmic contact region 323 and the source ohmic contact region of the transistor are formed by ion implantation. In actual fabrication, the ion implantation window can be defined by photolithography. The second electrode ohmic contact region 323 and the source ohmic contact region of the transistor have the same conductivity type; therefore, they can be formed using the same ion implantation process.

[0110] For example, P+ type ion implantation is performed to form the aforementioned second electrode ohmic contact region 323 and the source ohmic contact region of the transistor. The second electrode ohmic contact region 323 is also called the P-type ohmic contact region (or anode / positive electrode).

[0111] There is a gap between the second region and the first region. Specifically, there is a gap between the second region and the region where the first electrode region 321 is formed. This gap can be considered as a photosensitive region or a part of a photosensitive region, which is the region in the photoelectric conversion device that receives light irradiation and generates photogenerated carriers.

[0112] Next, please refer to Figure 13 A conductive connection layer 500 is formed.

[0113] For example, a conductive interconnect layer 500 can be formed by depositing a layer of metal material and patterning it using a photolithography process.

[0114] A portion of the circuitry in the conductive connection layer 500 enables the series connection between the photodiodes in the PDA. Specifically, a portion of the circuitry in the conductive connection layer 500 extends from the upper surface of the first electrode ohmic contact region 322 of one photodiode to the upper surface of the second electrode ohmic contact region 323 of another photodiode, thereby connecting the negative electrode of one photodiode to the positive electrode of another. This portion of the circuitry in the conductive connection layer 500 can be referenced from... Figure 16 The series circuit 503 in the photodiode. In actual fabrication, a protective layer can first be formed on the filled semiconductor layer 320 of each photodiode; part of the protective layer can be removed to form an opening that exposes the first electrode ohmic contact region 322 and the second electrode ohmic contact region 323; then a conductive connection layer 500 that makes ohmic contact with the first electrode ohmic contact region 322 and the second electrode ohmic contact region 323 can be formed in the opening; finally, the corresponding connection lines can be formed by etching.

[0115] Another portion of the circuitry in the conductive interconnect layer 500 enables the conductive lead-out of the source region 212 of the transistor (specifically, the source ohmic contact region in embodiments with a source ohmic contact region) to form the source of the transistor.

[0116] Furthermore, although not shown in the figure, it should be understood that the conductive connection layer 500 also includes some lines for conductively leading out the gate 220 of the transistor. Specifically, the gate 220 of the transistor is conductively connected to the positive terminal of the photoelectric conversion device, thereby receiving electrical signals from the photoelectric conversion device and controlling the transistor to turn on and off under the action of the received electrical signals.

[0117] Thus, two wire bonding regions corresponding to the source and gate of the transistor are formed on the first surface 101.

[0118] Figure 16 This is a top view of a power device in a specific example of this application, combined with... Figure 16As shown in this specific example, a plurality of first trenches 300 are provided in the first region 1011, thereby forming a plurality of photodiodes using the plurality of first trenches 300. The first electrode ohmic contact area 322 of each photodiode is connected to the second electrode ohmic contact area 323 of another photodiode through a series line 503. The photodiodes are arranged in an array and connected in series to form a PDA. The two photodiodes located at the beginning and end of the series line each have an electrode ohmic contact area that is not conductively connected (see Figures 504 and 505), thereby forming the positive and negative wire bonding positions of the driving circuit. In the second region 1012, the two wire bonding areas corresponding to the source and gate of the transistor can be referred to as Figures 502 and 501 respectively.

[0119] In subsequent steps, the gate of the transistor is electrically connected to the positive terminal of the photoelectric conversion device. Furthermore, the source of the transistor and the negative terminal of the photoelectric conversion device are connected to ground potential. Exemplarily, at least one of the above connections can be implemented using wire bonding. For example, one end of a wire is bonded at the positive terminal wire bonding location, and the other end of a wire is bonded in the gate wire bonding region. Optionally, the negative terminal of the photoelectric conversion device can be connected to the source of the transistor, and then grounded through the source of the transistor.

[0120] Next, please refer to Figure 14 The drain 600 of the transistor is formed on the second surface 102.

[0121] Understandably, since the first trench 300 extends from the first surface 101 into the interior of the semiconductor substrate 100 but not into the second surface 102, when the drain 600 is formed on the second surface 102, it will not be affected by the integrated optoelectronic conversion device at all.

[0122] In one specific implementation, the first trench 300 and the drain 600 of the transistor at least partially overlap in the thickness direction of the semiconductor substrate 100.

[0123] Specifically, the drain 600 can extend directly below the first region 1011 and the second region 1012. Furthermore, the drain 600 can completely cover the second surface 102.

[0124] Since the transistor drain 600 is typically connected to a high potential during device operation, a high-voltage electric field will be generated between the drain 600 and the bottom of the filling semiconductor layer 320 within the first trench 300, provided that the first trench 300 and the transistor drain 600 at least partially overlap in the thickness direction of the semiconductor substrate 100. The direction of the electric field is from the drain 600 to the bottom of the filling semiconductor layer 320. When light irradiates the space charge region of the photoelectric conversion device, it excites electron transitions, generating photogenerated carriers; that is, electron-hole pairs are generated in the space charge region. Electrons and holes enter the first electrode ohmic contact region 322 and the second electrode ohmic contact region 323, respectively, and are extracted through the conductive connection layer 500, thereby generating an electrical signal. In addition, some electrons and holes fail to enter the ohmic contact region but recombine within the filling semiconductor layer 320, and therefore cannot be extracted. In this embodiment, due to the formation of the aforementioned high-voltage electric field, some electrons are attracted to the bottom of the filled semiconductor layer 320 under the action of the high-voltage electric field, reducing the probability of recombination with holes; thus, the efficiency of the photoelectric conversion device is improved; for power devices including PDAs composed of multiple photoelectric conversion devices, the short-circuit current of the PDA array can be increased; thereby enhancing the charging of the transistor gate capacitor, achieving the effect of reducing switching time.

[0125] Finally, the method may also include a passivation step, which can be achieved using passivation processes commonly used in the field, and will not be described in detail here.

[0126] Thus, the embodiments of this application achieve circuit integration and miniaturization, avoiding the design complexity problems that discrete devices may bring. The transistors in the embodiments of this application can specifically be high-voltage power MOSFETs with a vertical structure, and generally operate in 500V to 800V application scenarios. The photoelectric conversion device can specifically form a PDA, which forms a photovoltaic output circuit, thereby serving as the driving circuit for the transistor (specifically, a light-driven circuit). The MOSFET belongs to the high-voltage section; the driving circuit belongs to the low-voltage section; using a PDA as the driving circuit achieves photoelectric isolation between the signal and response, i.e., between weak and strong currents. The MOSFET and PDA are isolated by a first trench 300 and an insulating isolation layer 310 to prevent the high voltage from affecting the low-voltage section.

[0127] The embodiments of this application enable the integration of a high-voltage MOSFET and a driving circuit onto a single chip, using only a conventional epitaxial substrate instead of an SOI substrate, thus reducing fabrication costs. The driving circuit fabrication process is compatible with existing superjunction MOSFET fabrication methods.

[0128] Figure 17 This is a schematic diagram illustrating an application scenario of a power device in a specific example. Figure 18This is a circuit diagram of a power device in a specific example. As shown, under the illumination of LED 10, PDA 21 in power device 20 generates photogenerated carriers, converting the optical signal into an electrical signal. The positive terminal of PDA 21 is conductively connected to the gate of SJMOSFET 22, transmitting the electrical signal to SJMOSFET 22, thereby controlling the operation of SJMOSFET 22. Furthermore, 23 represents parasitic resistance, 24 represents parasitic capacitance, and 25 and 26 are the drain and source terminals of SJMOSFET 22, respectively. The drain of SJMOSFET 22 is connected to a high potential through drain terminal 25, and the source of SJMOSFET 22 and the negative terminal of PDA 21 are grounded through source terminal 26.

[0129] The circuit structure of PDA 21 can be referenced. Figure 19 As shown in the figure, PDA 21 is composed of multiple photodiodes connected in series.

[0130] Based on this specific example, it can be understood that this application achieves signal and response isolation (i.e., opto-isolation), solves the gate oscillation problem, and meets the corresponding safety regulations.

[0131] Based on this, embodiments of this application also provide a power device. Combined with Figure 14 As shown, the power device includes:

[0132] Semiconductor substrate 100, the semiconductor substrate 100 includes a first surface 101 and a second surface 102 that are opposite to each other;

[0133] The first trench 300 is located in the first region 1011 of the first surface 101 and extends from the first surface 101 into the interior of the semiconductor substrate 100;

[0134] An insulating layer 310 covers the sidewalls and bottom wall of the first trench 300;

[0135] A semiconductor layer 320 is filled within an insulating isolation layer 310;

[0136] A photoelectric conversion device is formed on a filled semiconductor layer 320;

[0137] The transistor includes a source, a drain 600, and a gate 220. The source and gate are located in a second region 1012 of a first surface 101, and the drain 600 is located on a second surface 102. The gate 220 is electrically connected to the positive electrode of the photoelectric conversion device.

[0138] As an optional implementation, the semiconductor substrate 100 includes a semiconductor base 110 and an epitaxial layer 120 located on the semiconductor base 110;

[0139] The first surface 101 is the upper surface of the epitaxial layer 120, and the second surface 102 is the lower surface of the semiconductor substrate 110; the bottom wall of the first trench 300 is located within the epitaxial layer 120.

[0140] As an optional implementation, the semiconductor substrate 100 is made of a single-crystal semiconductor material; the filling semiconductor layer 320 is made of a polycrystalline semiconductor material.

[0141] As an alternative implementation, the first trench 300 and the drain 600 of the transistor at least partially overlap in the thickness direction of the semiconductor substrate 100.

[0142] As an optional implementation, the transistor is a superjunction MOSFET; the transistor also includes a plurality of spaced semiconductor pillars 210, the semiconductor pillars 210 being located in a second region 1012 of the first surface 101 and extending from the first surface 101 into the interior of the semiconductor substrate 100, the conductivity type of the semiconductor pillars 210 being opposite to the conductivity type of the semiconductor substrate 100.

[0143] As an alternative implementation, the photoelectric conversion device includes a photosensitive area, a positive electrode, and a negative electrode.

[0144] It should be noted that the power device embodiments and the power device fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0145] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method of manufacturing a power device, characterized by, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other; A first trench is formed in a first region of the first surface, extending from the first surface into the interior of the semiconductor substrate; An insulating layer is formed on the sidewalls and bottom wall of the first trench; A semiconductor-filled layer is formed within the insulating isolation layer; A photoelectric conversion device is formed on the filled semiconductor layer; The source and gate of the transistor are formed in a second region of the first surface, and the drain of the transistor is formed on the second surface; the filled semiconductor layer and the drain of the transistor at least partially overlap in the thickness direction of the semiconductor substrate; The gate of the transistor is electrically connected to the positive electrode of the photoelectric conversion device.

2. The method for fabricating the power device according to claim 1, characterized in that, The provision of the semiconductor substrate includes: providing a semiconductor substrate; and epitaxially growing an epitaxial layer on the semiconductor substrate; The first surface is the upper surface of the epitaxial layer, and the second surface is the lower surface of the semiconductor substrate; the bottom wall of the first trench is located within the epitaxial layer.

3. The method for fabricating the power device according to claim 1 or 2, characterized in that, The semiconductor substrate is made of a single-crystal semiconductor material; the filling semiconductor layer is made of a polycrystalline semiconductor material.

4. The method for fabricating a power device according to claim 1, characterized in that, The transistor is a superjunction MOSFET; Before forming the first trench, the method further includes: A plurality of second trenches are formed in a second region of the first surface, extending from the first surface into the interior of the semiconductor substrate, the plurality of second trenches being spaced apart; Semiconductor pillars are epitaxially grown inside and outside a plurality of second trenches, the conductivity type of the semiconductor pillars being opposite to that of the semiconductor substrate.

5. The method for fabricating a power device according to claim 1, characterized in that, A photoelectric conversion device is formed on the filled semiconductor layer, comprising: The first region on the filled semiconductor layer is doped to form a negative electrode, and the second region on the filled semiconductor layer is doped to form a positive electrode.

6. A power device, characterized by include: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other; A first trench is located in a first region of the first surface and extends from the first surface into the interior of the semiconductor substrate; An insulating layer covers the sidewalls and bottom wall of the first trench; A semiconductor layer is filled within the insulating isolation layer; A photoelectric conversion device is formed on the filled semiconductor layer; A transistor includes a source, a drain, and a gate, wherein the source and the gate are located in a second region of a first surface, and the drain is located on the second surface; wherein the gate is electrically connected to the positive electrode of the photoelectric conversion device; and the filled semiconductor layer and the drain at least partially overlap in the thickness direction of the semiconductor substrate.

7. The power device according to claim 6, characterized in that, The semiconductor substrate includes a semiconductor substrate and an epitaxial layer located on the semiconductor substrate; The first surface is the upper surface of the epitaxial layer, and the second surface is the lower surface of the semiconductor substrate; the bottom wall of the first trench is located within the epitaxial layer.

8. The power device according to claim 6 or 7, characterized in that, The semiconductor substrate is made of a single-crystal semiconductor material; the filling semiconductor layer is made of a polycrystalline semiconductor material.

9. The power device according to claim 6, characterized in that, The transistor is a super-junction MOSFET; the transistor further comprises: A plurality of spaced semiconductor pillars are located in the second region of the first surface and extend from the first surface to the interior of the semiconductor substrate, and the conductive type of the semiconductor pillars is opposite to the conductive type of the semiconductor substrate.

10. The power device of claim 6, wherein, The photoelectric conversion device comprises a light-sensing region, a positive electrode, and a negative electrode.

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