An ldmos device and a method of manufacturing the same

Abstract

The application provides an LDMOS device and a preparation method thereof, the LDMOS device comprises a semiconductor body, a gate structure, a first field plate, a metal silicide barrier layer, a second field plate, an interlayer dielectric layer and a third field plate, the distance from the bottom surface of the first field plate, the second field plate and the third field plate to the semiconductor body increases in turn, that is, the thickness of the dielectric layer under the field plate increases from the gate to the drain region, so that the distribution of the electric field is more uniform, and the performance of the LDMOS device is improved; in addition, the preparation method of the LDMOS device of the application utilizes the different thicknesses of the dielectric layer in the existing BCD process, and the field plates in a ladder-shaped distribution are prepared on the dielectric layers with different thicknesses, compared with the existing preparation method, any additional process step is not increased, and the manufacturing cost is saved.

Description

An LDMOS device and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and more specifically to an LDMOS device and its fabrication method. Background Technology

[0002] LDMOS (Lateral Double-Diffused MOSFET) is a lateral power device with advantages such as high voltage withstand, high input impedance, good safe operating area, and low power consumption. It is commonly used as a high-voltage power device in power integrated circuits such as motor drives, automotive electronics, industrial control, and switching power supplies.

[0003] The structural performance of LDMOS directly affects the performance of power integrated circuits. The main parameters for measuring LDMOS performance are on-resistance and breakdown voltage. In order to achieve both good voltage withstand characteristics and low on-resistance, a field plate is usually placed between the drain region and the gate of the LDMOS. In order to make the electric field distribution more uniform, the oxide layer thickness under the field plate needs to be increased sequentially from the gate to the drain region. However, manufacturing oxide layers of different thicknesses requires additional masks and additional process steps, which increases costs. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention proposes an LDMOS device and its fabrication method. The LDMOS device includes a semiconductor body, a gate structure, a first field plate, a metal silicide barrier layer, a second field plate, an interlayer dielectric layer, and a third field plate. The distance from the bottom surface of the first, second, and third field plates to the semiconductor body increases sequentially, that is, the thickness of the dielectric layer under the field plate increases sequentially from the gate to the drain region, thereby enabling a more uniform electric field distribution and improving the performance of the LDMOS device. In addition, the fabrication method of the LDMOS device of the present invention utilizes the different thicknesses of the dielectric layer in the existing BCD process to fabricate a stepped distribution of field plates on dielectric layers of different thicknesses. Compared with the existing fabrication methods, no additional process steps are added, saving manufacturing costs.

[0005] To achieve the above and other related objectives, the present invention provides an LDMOS device, the LDMOS device comprising:

[0006] Semiconductor body;

[0007] A gate structure, located on the surface of the semiconductor body, includes a gate oxide layer and a gate located on the surface of the gate oxide layer;

[0008] The first field plate is located on the surface of the gate oxide layer and is arranged side by side with the gate in the first direction;

[0009] A metal silicide barrier layer is located on the surface of the gate oxide layer and covers a portion of the first field plate;

[0010] The second field plate is located on the surface of the metal silicide barrier layer;

[0011] An interlayer dielectric layer is located on the surface of the semiconductor body and covers the gate structure, the first field plate, the second field plate, and the metal silicide barrier layer;

[0012] The third plate is located on the surface of the interlayer dielectric layer.

[0013] Optionally, the semiconductor body includes a substrate, in which a body region and a drift region are disposed adjacent to each other; a source region consisting of a first conductivity type doped region and a second conductivity type doped region is disposed in the body region; and a drain region having a second conductivity type is disposed in the drift region.

[0014] Optionally, a source metal layer and a drain metal layer are further disposed on the surface of the interlayer dielectric layer, wherein the source metal layer is located above the source, the drain metal layer is located above the drain, and the third field plate is located between the source metal layer and the drain metal layer.

[0015] Optionally, the source metal layer extends above the second field plate and partially overlaps with the second field plate, and the area of ​​the overlapping portion gradually decreases from the side where the source metal layer is located to the side where the drain metal layer is located.

[0016] Optionally, a contact hole is also formed in the interlayer dielectric layer, and the source metal layer is connected to the source through the contact hole, and the drain metal layer is connected to the drain through the contact hole.

[0017] Optionally, sidewalls are also formed on both sides of the gate and the first field plate.

[0018] Optionally, the first field plate is made of polycrystalline silicon material.

[0019] Optionally, the second field plate includes a first portion and a second portion located on the surface of the first portion, the first portion being made of an insulating material.

[0020] Optionally, the second portion surface is further provided with contact holes, the contact holes connecting the second portion to the source metal layer.

[0021] Optionally, the second part is made of a metallic material.

[0022] Optionally, the second part is made of polycrystalline silicon material.

[0023] Optionally, the second field plate is a contact hole field plate, and the end of the second field plate away from the metal silicide barrier layer is exposed between the source metal layer and the third field plate.

[0024] Optionally, the second field plate is a contact hole field plate that connects the metal silicide barrier layer and the source metal layer.

[0025] Optionally, the third field plate is made of a metallic material.

[0026] This invention also provides a method for fabricating an LDMOS device, comprising the following steps:

[0027] Provide a semiconductor body;

[0028] A gate oxide layer is deposited on the surface of the semiconductor body, and a first field plate is formed on the surface of the gate oxide layer;

[0029] A metal silicide barrier layer is formed on the surface of the gate oxide layer and a portion of the surface of the first field plate, and a second field plate is formed on the surface of the metal silicide barrier layer.

[0030] An interlayer dielectric layer is deposited on the surface of the semiconductor body, and contact holes are formed in the interlayer dielectric layer;

[0031] A source metal layer, a third field plate, and a drain metal layer are formed on the surface of the interlayer dielectric layer.

[0032] This invention also provides a method for fabricating an LDMOS device, comprising the following steps:

[0033] Provide a semiconductor body;

[0034] A gate oxide layer is deposited on the surface of the semiconductor body, and a first field plate is formed on the surface of the gate oxide layer;

[0035] A metal silicide barrier layer is formed on the surface of the gate oxide layer and on a portion of the surface of the first field plate;

[0036] An interlayer dielectric layer is deposited on the surface of the semiconductor body, and a second field plate and a contact hole are formed in the interlayer dielectric layer, wherein the second field plate is located on the surface of the metal silicide barrier layer and penetrates the interlayer dielectric layer;

[0037] A source metal layer, a third field plate, and a drain metal layer are formed on the surface of the interlayer dielectric layer.

[0038] Optionally, the first field plate is made of polycrystalline silicon material.

[0039] Optionally, forming the second field plate includes: forming a first portion on the surface of the metal silicide barrier layer, and forming a second portion on the surface of the first portion.

[0040] Optionally, the second part is made of a metallic material.

[0041] Optionally, the second part is made of polycrystalline silicon material.

[0042] Optionally, the third field plate is made of a metallic material.

[0043] The LDMOS device provided by this invention has at least the following beneficial effects:

[0044] The LDMOS device of the present invention includes a semiconductor body, a gate structure, a first field plate, a metal silicide barrier layer, a second field plate, an interlayer dielectric layer, and a third field plate. The distance from the bottom surface of the first field plate, the second field plate, and the third field plate to the semiconductor body increases sequentially, that is, the thickness of the dielectric layer under the field plate increases sequentially from the gate to the drain region, thereby enabling a more uniform distribution of the electric field and improving the performance of the LDMOS device.

[0045] In addition, the LDMOS device fabrication method of the present invention utilizes the different thicknesses of the dielectric layer in the existing BCD process to fabricate a stepped field plate on the dielectric layer of different thicknesses. Compared with the existing fabrication method, no additional process steps are added, thus saving manufacturing costs. Attached Figure Description

[0046] Figure 1 shows a schematic diagram of the LDMOS device provided in Embodiment 1.

[0047] Figures 2a and 2b show schematic diagrams of the arrangement of the second and third field plates on the surface of the semiconductor body in Embodiment 1.

[0048] Figures 3a and 3b show schematic diagrams of the arrangement of the source metal layer in Example 1.

[0049] Figure 4 shows a flowchart of the LDMOS device fabrication method provided in Example 1.

[0050] Figures 5a to 5c show schematic diagrams of the structures formed in steps S2 to S4 of Example 1.

[0051] Figure 6 shows a schematic diagram of the LDMOS device provided in Example 2.

[0052] Figure 7 shows a schematic diagram of the LDMOS device provided in Example 3.

[0053] Figure 8 shows a schematic diagram of another LDMOS device provided in Embodiment 3.

[0054] Component designation explanation

[0055] 10 Semiconductor body 31 First field plate

[0056] 11 Substrate 32 Second Field Plate

[0057] 12 Body Area 321 Second Field Board First Part

[0058] 120 Source 322 Second part of the second field plate

[0059] 121 First conductivity type doped region 33 Third field plate

[0060] 122 Second conductivity type doped region 40 Metal silicide barrier layer

[0061] 13 Drift Region 50 Interlayer Dielectric Layer

[0062] 130 Leakage Zone 60 Side Wall Structure

[0063] 20 Gate structure 70 Contact hole

[0064] 21 Gate oxide layer 81 Source metal layer

[0065] 22 Gate 82 Drain Metal Layer Detailed Implementation

[0066] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0068] Example 1

[0069] The technical solution described in this invention will be specifically explained below. In the following embodiments, the most common N-type LDMOS device will be used as an example. That is, in this embodiment, the first conductivity type is defined as P-type and the second conductivity type is defined as N-type. In other opposite embodiments, the first conductivity type can be defined as N-type and the second conductivity type as P-type, which can be directly replaced. This invention will not provide further specific explanation in this regard.

[0070] This embodiment provides an LDMOS device, as shown in FIG1. ​​The LDMOS device includes: a semiconductor body 10, a gate structure 20, a first field plate 31, a metal silicide barrier layer 40, a second field plate 32, an interlayer dielectric layer 50, and a third field plate 33.

[0071] As shown in Figure 1, the semiconductor body 10 includes a substrate 11 (i.e., a P-type substrate) having a first conductivity type. The substrate 11 has a body region 12 and a drift region 13 that are adjacent to each other. The body region 12 has a first conductivity type, and the drift region 13 has a second conductivity type. The body region 12 has a first conductivity type doped region 121 (P+ represents the doping type and concentration of the first conductivity type doped region 121 in the figure) and a second conductivity type doped region 122 (N+ represents the doping type and concentration of the second conductivity type doped region 122 in the figure), which together form the source 120. The drift region 13 has a drain region 130 having a second conductivity type, and the drain region 130 has a higher doping concentration than the drift region 13 (N+ represents the doping type and concentration of the drain region 130 in the figure).

[0072] As shown in Figure 1, the gate structure 20 is located on the surface of the semiconductor body 10, and is connected to the source 120 and spaced apart from the drain region 130. The gate structure 20 includes a gate oxide layer 21 and a gate 22, wherein the gate oxide layer 21 is located on the surface of the semiconductor body 10, and the gate 22 is located on the surface of the gate oxide layer 21. Sidewall structures 60 are also formed on both sides of the gate structure 20, and the sidewall structures 60 contain dielectric material to further isolate the gate structure 20. As an example, the gate oxide layer 21 can be silicon dioxide, and the gate 22 can be metal, polysilicon, etc. In this embodiment, the gate 22 is made of polysilicon.

[0073] Referring to Figures 1 and 2a-2b, a first field plate 31 is also formed on the gate oxide layer 21. The thickness of the dielectric layer below the first field plate 31 is the same as the thickness of the gate oxide layer 21. The first field plate 31 and the gate 22 are arranged side-by-side in a first direction (i.e., the X direction shown in Figures 2a-2b), and both sides of the first field plate 31 also have sidewall structures 60. As an example, the first field plate 31 is a rectangular structure extending in a second direction perpendicular to the first direction (i.e., the Y direction shown in Figures 2a-2b). In this embodiment, the first field plate 31 is made of polycrystalline silicon.

[0074] As shown in Figure 1, a metal silicide barrier layer 40 is also formed on the surface of the gate oxide layer 21. In this embodiment, the metal silicide barrier layer 40 covers a portion of the first field plate 31. In another optional embodiment, the metal silicide barrier layer 40 may simultaneously cover both the first field plate 31 and a portion of the gate 22. As an example, the material of the metal silicide barrier layer 40 is a dielectric material, such as silicon oxide or silicon nitride.

[0075] As shown in Figure 1, a second field plate 32 is formed on the surface of the metal silicide barrier layer 40. The second field plate includes a first portion 321 and a second portion 322 located above the first portion 321. The thickness of the dielectric layer below the second field plate 32 is the sum of the thicknesses of the gate oxide layer 21 and the metal silicide barrier layer 40, which is greater than the thickness of the dielectric layer below the first field plate 31 (the thickness of the gate oxide layer 21). As an example, the first portion 321 is made of an insulating material, and the second portion 322 is made of a metallic material. In another optional embodiment, the second portion 322 is made of polysilicon.

[0076] As shown in Figure 2a, in this embodiment, the second field plate 32 is arranged in an array, and the specific number of rows and columns can be determined according to the actual situation and needs. In another optional embodiment of this embodiment, as shown in Figure 2b, the second field plate 32 is a rectangular structure, and it extends in the second direction (i.e., the Y direction shown in Figure 2b) and is arranged in parallel in the first direction (i.e., the X direction shown in Figure 2b). The number of columns of the second field plate 32 in the second direction can be determined according to the actual situation and needs.

[0077] As shown in Figure 1, an interlayer dielectric layer 50 is formed on the surface of the semiconductor body 10. The interlayer dielectric layer 50 covers the gate structure 20, the first field plate 31, the second field plate 32, and the metal silicide barrier layer 40. As an example, the interlayer dielectric layer 50 can be an oxide. Contact holes 70 are also formed in the interlayer dielectric layer 50. In this embodiment, the contact holes 70 penetrate the interlayer dielectric layer 50. The contact holes 70 located above the source 120 connect the source 120 to the source metal layer 81, and the contact holes 70 located above the drain region 130 connect the drain region 130 to the drain region metal layer 82.

[0078] As shown in Figure 1, the third field plate 33 is located on the surface of the interlayer dielectric layer 50, specifically between the source metal layer 81 and the drain metal layer 82. The thickness of the dielectric layer below the third field plate 33 is the same as the thickness of the interlayer dielectric layer 50, which is greater than the thickness of the dielectric layer below the second field plate 32 (the sum of the thicknesses of the gate oxide layer 21 and the metal silicide barrier layer 40). The material of the third field plate 33 is the same as that of the source metal layer 81 and the drain metal layer 82. As an example, the material of the third field plate 33 can be a metal or metal-like material with low conductivity and good adhesion, such as titanium, titanium nitride, aluminum, copper, etc.

[0079] As an example, the source metal layer 81 extends above the second field plate and partially overlaps with the second field plate 32. The area of ​​the overlap near the source is larger than the area near the drain. In other words, as shown in Figures 3a and 3b, the area of ​​the overlap between the second field plate 32 and the source metal layer 81 gradually decreases from left to right. This design allows the potential of the second field plate to gradually increase, thereby ensuring that the electric field strength of the second field plate 32 and the surface of the semiconductor body 10 remains as consistent as possible, improving the reliability of the device. It should be noted that this embodiment only uses Figures 3a and 3b as examples. The second field plate can also be arranged in an array, and the source metal layer can be arranged on the surface of the interlayer dielectric layer in other ways that satisfy the above conditions.

[0080] As shown in Figure 2a, in this embodiment, the third field plate 33 is arranged in an array, and the specific number of rows and columns can be determined according to the actual situation and needs. In another optional embodiment of this embodiment, as shown in Figure 2b, the third field plate 33 is a rectangular structure, and it extends in the second direction (i.e., the Y direction shown in Figure 2b) and is arranged in parallel in the first direction (i.e., the X direction shown in Figure 2b). The number of columns of the third field plate 33 in the second direction can be determined according to the actual situation and needs.

[0081] This embodiment also provides a method for fabricating an LDMOS device, as shown in Figure 4, which includes the following steps:

[0082] Step S1: Provide a semiconductor body;

[0083] Referring to FIG1, a substrate 11 is provided, the substrate 11 having a first conductivity type. As an example, the substrate 11 may be a silicon substrate, or a silicon-on-insulator (SOI) substrate, etc. In this embodiment, the substrate 11 is a P-type silicon substrate, which can be formed by epitaxial growth.

[0084] Next, a P-well is formed as the body region 12 in the substrate 11 through a well implantation process. Then, an N-type lightly doped region is formed as the drift region 13 on the substrate 11 through an implantation process. P-type impurities are implanted into the body region 12 to form a first conductivity type doped region 121, and N-type impurities are implanted to form a second conductivity type doped region 122. The first conductivity type doped region 121 and the second conductivity type doped region 122 are laterally connected to form a source 120, and the doping concentration of the source 120 is greater than that of the body region 12. N-type impurities are implanted into the drift region 13 to form a drain region 130. The doping concentrations of the second conductivity type doped region 122 and the drain region 130 can be the same, and they can be formed simultaneously through doping.

[0085] Step S2: A gate oxide layer is deposited on the surface of the semiconductor body, and a first field plate is formed on the surface of the gate oxide layer;

[0086] Referring to FIG5a, a gate oxide layer 21 is first formed on the surface of the semiconductor body 10 by thermal oxidation, a polysilicon layer is deposited on the gate oxide layer 21, and a gate 22 and a first field plate 31 are formed by etching respectively. Then, an insulating dielectric layer is deposited on both sides of the gate 22 and the first field plate 31 and sidewalls 60 are formed by etching.

[0087] Step S3: A metal silicide barrier layer is formed on the surface of the gate oxide layer and a portion of the surface of the first field plate, and a second field plate is formed on the surface of the metal silicide barrier layer;

[0088] Referring to FIG5b, a thin layer of dielectric material such as silicon oxide or silicon nitride is coated onto a portion of the surface of the first field plate 31 to form a metal silicide barrier layer 40. In another alternative embodiment, the metal silicide barrier layer 40 may also cover both the first field plate 31 and a portion of the gate 22.

[0089] Next, insulating material and metal material are deposited sequentially, and a second field plate 32 with an array arrangement is formed by photolithography and etching processes. The first portion 321 of the second field plate is made of insulating material, and the second portion 322 located on the surface of the first portion is made of metal material. In another optional embodiment, insulating material and polycrystalline silicon material are deposited sequentially, and the second portion 322 is made of polycrystalline silicon material.

[0090] Step S4: An interlayer dielectric layer is deposited on the surface of the semiconductor body, and a contact hole is formed in the interlayer dielectric layer;

[0091] Referring to FIG5c, an interlayer dielectric layer 50 is deposited on the surface of the semiconductor body 10. After planarization by chemical mechanical polishing, through-holes are formed in the interlayer dielectric layer 50 by photolithography and reactive ion etching. The through-holes are respectively connected to the first conductivity type doped region 121, the second conductivity type doped region 122, and the drain region 130. The through-holes are filled with metal to form contact holes 70.

[0092] Step S5: Form a source metal layer, a third field plate, and a drain metal layer on the surface of the interlayer dielectric layer.

[0093] As an example, a metal layer is deposited on the surface of the interlayer dielectric layer 50. The metal layers are then spaced apart using photolithography to form a source metal layer 81, a third field plate 33, and a drain metal layer. The third field plate 33 is arranged in an array, as shown in Figures 2a and 2b. The pattern of the source metal layer 81 can be configured according to the needs of the device. The source 120 is led out through the contact hole 70 and shorted through the source metal layer 81 to form the source of the LDMOS device. The drain 130 is led out through the contact hole 70 and connected to the drain metal layer 82 to form the drain of the LDMOS device, ultimately forming the LDMOS device shown in Figure 1.

[0094] In the LDMOS device provided in this embodiment, there are a first field plate, a second field plate, and a third field plate with a stepped distribution. The distance from the bottom surface of the first field plate, the second field plate, and the third field plate to the semiconductor body increases sequentially. That is, the thickness of the dielectric layer under the field plate increases sequentially from the gate to the drain region, which greatly improves the breakdown voltage of the LDMOS and makes the electric field distribution more uniform, thereby improving the performance of the LDMOS device.

[0095] In addition, the LDMOS device fabrication method of the present invention utilizes the different thicknesses of the dielectric layer in the existing BCD process to fabricate a stepped field plate on the dielectric layer of different thicknesses. Compared with the existing fabrication method, no additional process steps are added, thus saving manufacturing costs.

[0096] Example 2

[0097] This embodiment also provides an LDMOS device. The similarities between this embodiment and the LDMOS device in Embodiment 1 will not be repeated here. The difference is that, as shown in Figure 6, a contact hole 70 is also formed on the surface of the second field plate 32. The contact hole 70 connects the second field plate 32 and the source metal layer 81. At this time, the thickness of the dielectric layer below the second field plate 32 is still the sum of the thicknesses of the gate oxide layer 21 and the metal silicide barrier layer 40, which is greater than the thickness of the dielectric layer below the first field plate 31 (the thickness of the gate oxide layer 21), and less than the thickness of the dielectric layer below the third field plate 33 (the thickness of the interlayer dielectric layer 50).

[0098] Example 3

[0099] This embodiment also provides an LDMOS device. The similarities between this embodiment and the LDMOS device in Embodiment 1 will not be repeated here. The difference lies in that, as shown in Figure 7, the second field plate 32 is a contact hole field plate, connecting the metal silicide barrier layer 40 and the source metal layer 81; in another optional embodiment of this embodiment, as shown in Figure 8, the end of the second field plate 32 away from the metal silicide barrier layer 40 is exposed between the source metal layer 81 and the third field plate 33. In the LDMOS device provided in this embodiment, the thickness of the dielectric layer below the second field plate 32 is still the sum of the thicknesses of the gate oxide layer 21 and the metal silicide barrier layer 40, which is greater than the thickness of the dielectric layer below the first field plate 31 (the thickness of the gate oxide layer 21), and less than the thickness of the dielectric layer below the third field plate 33 (the thickness of the interlayer dielectric layer 50).

[0100] This embodiment also provides a method for fabricating the above-mentioned LDMOS device, the method specifically including the following steps:

[0101] Step S101: Provide a semiconductor body;

[0102] Step S102: A gate oxide layer is deposited on the surface of the semiconductor body, and a first field plate is formed on the surface of the gate oxide layer;

[0103] Step S103: Form a metal silicide barrier layer on the surface of the gate oxide layer and on a portion of the surface of the first field plate;

[0104] Step S104: An interlayer dielectric layer is deposited on the surface of the semiconductor body, and a second field plate and a contact hole are formed in the interlayer dielectric layer, wherein the second field plate is located on the surface of the metal silicide barrier layer and penetrates the interlayer dielectric layer;

[0105] Step S105: Form a source metal layer, a third field plate, and a drain metal layer on the surface of the interlayer dielectric layer.

[0106] As an example, steps S101 to S103 and steps S105 are the same as steps S1 to S3 and steps S5 in Embodiment 1, respectively. For details, please refer to the description of steps S1 to S3 and steps S5 in Embodiment 1, which will not be repeated here.

[0107] In step S104, an interlayer dielectric layer 50 is deposited on the surface of the semiconductor body 10. After planarization by chemical mechanical polishing, through-holes are formed in the interlayer dielectric layer 50 by photolithography and reactive ion etching. The through-holes are formed not only on the surfaces of the first conductivity type doped region 121, the second conductivity type doped region 122, and the drain region 130, but also on the surface of the metal silicide barrier layer 40. The through-holes are filled with metal to form contact holes 70. The contact holes formed on the surface of the metal silicide barrier layer 40 are the second field plates 32.

[0108] In summary, the present invention provides an LDMOS device having a stepped distribution of a first field plate, a second field plate, and a third field plate. The distance from the bottom surface of the first, second, and third field plates to the semiconductor body increases sequentially, that is, the thickness of the dielectric layer under the field plates increases sequentially from the gate to the drain region. This greatly improves the breakdown voltage of the LDMOS, thereby enabling a more uniform distribution of the electric field and improving the performance of the LDMOS device.

[0109] In addition, the LDMOS device fabrication method of the present invention utilizes the different thicknesses of the dielectric layer in the existing BCD process to fabricate a stepped field plate on the dielectric layer of different thicknesses. Compared with the existing fabrication method, no additional process steps are added, thus saving manufacturing costs.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LDMOS device, characterized in that, include: Semiconductor body; A gate structure, located on the surface of the semiconductor body, includes a gate oxide layer and a gate located on the surface of the gate oxide layer; A first field plate is located on the surface of the gate oxide layer and is arranged side-by-side with the gate in a first direction. Sidewalls are also formed on both sides of the gate and the first field plate. A metal silicide barrier layer is located on the surface of the gate oxide layer and covers part of the first field plate. A second field plate is located on the surface of the metal silicide barrier layer. An interlayer dielectric layer is located on the surface of the semiconductor body and covers the gate structure, the first field plate, the second field plate, and the metal silicide barrier layer. A third field plate is located on the surface of the interlayer dielectric layer.

2. The LDMOS device according to claim 1, characterized in that, The semiconductor body includes a substrate, in which a body region and a drift region are disposed adjacent to each other; a source region consisting of a first conductivity type doped region and a second conductivity type doped region is disposed in the body region; and a drain region having a second conductivity type is disposed in the drift region.

3. The LDMOS device according to claim 2, characterized in that, The surface of the interlayer dielectric layer is further provided with a source metal layer and a drain metal layer, wherein the source metal layer is located above the source, the drain metal layer is located above the drain, and the third field plate is located between the source metal layer and the drain metal layer.

4. The LDMOS device according to claim 3, characterized in that, The source metal layer extends above the second field plate and partially overlaps with the second field plate. The area of ​​the overlapping portion gradually decreases from the side where the source metal layer is located to the side where the drain metal layer is located.

5. The LDMOS device according to claim 3, characterized in that, The interlayer dielectric layer also has contact holes, and the source metal layer is connected to the source through the contact holes, and the drain metal layer is connected to the drain through the contact holes.

6. The LDMOS device according to claim 1, characterized in that, The first field plate is made of polycrystalline silicon material.

7. The LDMOS device according to claim 4, characterized in that, The second field plate includes a first portion and a second portion located on the surface of the first portion, the first portion being made of an insulating material.

8. The LDMOS device according to claim 7, characterized in that, The second part also has a contact hole formed on its surface, the contact hole connecting the second part to the source metal layer.

9. The LDMOS device according to claim 7 or 8, characterized in that, The second part is made of metallic material.

10. The LDMOS device according to claim 7 or 8, characterized in that, The second part is made of polycrystalline silicon material.

11. The LDMOS device according to claim 3, characterized in that, The second field plate is a contact hole field plate, and the end of the second field plate away from the metal silicide barrier layer is exposed between the source metal layer and the third field plate.

12. The LDMOS device according to claim 4, characterized in that, The second field plate is a contact hole field plate that connects the metal silicide barrier layer and the source metal layer.

13. The LDMOS device according to claim 1, characterized in that, The third field plate is made of metal.

14. A method for fabricating an LDMOS device, characterized in that, The process includes the following steps: providing a semiconductor body; depositing and forming a gate oxide layer on the surface of the semiconductor body, and forming a gate and a first field plate on the surface of the gate oxide layer, forming sidewalls on both sides of the gate and the first field plate; forming a metal silicide barrier layer on the surface of the gate oxide layer and a portion of the surface of the first field plate, and forming a second field plate on the surface of the metal silicide barrier layer; depositing and forming an interlayer dielectric layer on the surface of the semiconductor body, and forming contact holes in the interlayer dielectric layer; A source metal layer, a third field plate, and a drain metal layer are formed on the surface of the interlayer dielectric layer.

15. The method for fabricating an LDMOS device according to claim 14, characterized in that, Forming the second field plate includes: forming a first portion on the surface of the metal silicide barrier layer, and forming a second portion on the surface of the first portion.

16. The method for fabricating an LDMOS device according to claim 15, characterized in that, The second part is made of metallic material.

17. The method for fabricating an LDMOS device according to claim 15, characterized in that, The second part is made of polycrystalline silicon material.

18. A method for fabricating an LDMOS device, characterized in that, The method includes the following steps: providing a semiconductor body; depositing and forming a gate oxide layer on the surface of the semiconductor body, and forming a gate and a first field plate on the surface of the gate oxide layer, and forming sidewalls on both sides of the gate and the first field plate; forming a metal silicide barrier layer on the surface of the gate oxide layer and a portion of the surface of the first field plate; depositing and forming an interlayer dielectric layer on the surface of the semiconductor body, and forming a second field plate and a contact hole in the interlayer dielectric layer, wherein the second field plate is located on the surface of the metal silicide barrier layer and penetrates the interlayer dielectric layer; and forming a source metal layer, a third field plate, and a drain metal layer on the surface of the interlayer dielectric layer.

19. The method for fabricating an LDMOS device according to claim 14 or 18, characterized in that, The first field plate is made of polycrystalline silicon material.

20. The method for fabricating an LDMOS device according to claim 14 or 18, characterized in that, The third field plate is made of metal.

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