A normally-closed gallium nitride integrated device with large threshold voltage and a preparation method thereof

Abstract

The application discloses a normally closed gallium nitride integrated device with a large threshold voltage and a preparation method thereof. The device comprises, from bottom to top, a silicon carbide substrate layer, an aluminum nitride nucleation layer, a relaxation layer A, a relaxation layer B, an aluminum gallium nitride buffer layer, a gallium nitride channel and an aluminum gallium nitride barrier layer. The aluminum gallium nitride barrier layer is provided with a source electrode and a drain electrode at both ends of the surface of the aluminum gallium nitride barrier layer, and is provided with an isolated insulating layer A and an insulating layer B on the surface of the aluminum gallium nitride barrier layer. The surface of the insulating layer B is provided with a gate layer A, and the surface of the insulating layer A and the gate layer A is provided with a graphene film electrode. The surface of the graphene film electrode is provided with an insulating layer C on the left side, and the surface of the insulating layer C is provided with a gate layer B and an aluminum electrode layer. The insulating layer A, the insulating layer C and the gate layer B form a main gate, and the insulating layer B and the gate layer A form a sub-gate, thereby forming a series-parallel hybrid double HEMT integrated structure. The threshold voltage of the normally closed gallium nitride integrated device can be increased to 3.7 V.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a normally closed gallium nitride integrated device with a large threshold voltage and its fabrication method. Background Technology

[0002] With the rapid development of semiconductor materials and devices, the first generation of semiconductor materials was represented by silicon (Si). After the 1990s, second-generation semiconductor materials with high mobility, such as gallium arsenide (GaAs) and indium phosphide (InP), gradually emerged. As second-generation semiconductor materials approached the limits of their material properties, third-generation wide-bandgap semiconductor materials emerged, with gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO), and diamond as the four main representatives. Gallium nitride (GaN), as a typical representative, possesses excellent properties such as wide bandgap, high charge density, high voltage resistance, and high electron mobility, making it the preferred material for fabricating high-power devices and a research focus in the field of semiconductor power devices in recent years. Among the many gallium nitride-based semiconductor power devices, gallium nitride high electron mobility transistors (HEMTs) are widely used due to their high-frequency characteristics. HEMTs based on AlGaN / GaN heterostructures exhibit excellent performance and are widely used in mobile phones, satellite television, and radar.

[0003] Gallium nitride (GaN) has such a wide range of applications and broad development prospects that the importance of GaN high electron mobility transistors (HEMTs) is self-evident, and the demand for better device characteristics will continue to increase. The principle of GaN HEMTs is based on a heterostructure composed of AlGaN and GaN, where an exceptionally high concentration of two-dimensional electron gas (2DEG) exists near the heterojunction interface. The efficient conduction of current by the 2DEG under an applied electric field is the foundation of GaN HEMTs. The high critical breakdown electric field of GaN material and the high mobility and electron density of the 2DEG enable GaN-based HEMTs to operate at higher voltages, currents, frequencies, and temperatures compared to similar silicon-based products. Because of the presence of 2DEG at the AlGaN / GaN heterojunction interface, HEMTs are essentially normally-on devices.

[0004] However, for safety reasons and to simplify circuits, it is essential to design a normally closed HEMT in power electronics applications. Figure 7The diagram illustrates the impact of the aluminum gallium nitride (AlGaN) barrier layer thickness and the molar fraction of aluminum on the device type. These are two crucial parameters determining the HEMT device type. Increasing the AlGaN barrier layer thickness necessitates reducing the molar fraction of aluminum in the barrier layer to ensure the HEMT device remains normally closed. Currently, various methods exist for fabricating normally closed HEMTs, among which the method based on enhancement-mode gallium nitride (p-GaN) gates is the most promising and likely to be commercially viable. The first commercially available AlGaN / GaN HEMT enhancement-mode device was achieved by growing a positively charged p-GaN layer on top of the AlGaN barrier. The fabrication of enhancement-mode gallium nitride (HEMT) devices aims to pinch off the conductive channel when the gate and source voltages are zero, and turn on when a positive voltage is applied. The built-in voltage generated by the positively charged p-GaN layer is greater than the voltage generated by the piezoelectric effect of the AlGaN / GaN heterojunction. Without an externally applied bias voltage, the AlGaN barrier layer cannot directly interact with the energy band of the metal gate. When the barrier layer contacts the channel, the conduction band in the GaN channel layer below the p-GaN capping layer is raised above the Fermi level, thus depleting the 2DEG below the gate and forming a normally closed AlGaN / GaNHEMT structure. For power devices, the threshold voltage is the voltage required to conduct current when applied to the gate and source. The threshold voltage of a normally open HEMT is less than zero, requiring a negative gate voltage to turn off the device, which undoubtedly increases the device's turn-off loss. In contrast, a normally closed HEMT has a positive threshold voltage for turning on the device. Magnesium (Mg) is a commonly used reference p-type dopant in GaN or AlGaN because it acts as an acceptor when added to the nitride lattice to replace Ga. However, the ionization energy of Mg dopant is relatively high, in the range of 150-200 meV. Therefore, it is difficult to achieve a high hole concentration in p-GaN, and the hole ionization rate at room temperature is very low. This results in the threshold voltage of p-GaN gate-structured HEMT devices generally only reaching around 1V, limiting the improvement of the threshold voltage. Other methods are needed to increase the threshold voltage of the devices. Although most manufacturers currently produce normally closed GaN HEMT devices with a threshold voltage of up to 2V, industrial applications often require GaN HEMT devices with a threshold voltage of 3V or higher, which current devices struggle to meet. Therefore, how to effectively improve the threshold voltage of gallium nitride HEMT devices is a pressing problem that needs to be solved. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide a normally closed gallium nitride integrated device with a large threshold voltage and a method for fabricating the same, so as to improve the threshold voltage of the normally closed gallium nitride integrated device and thus improve its applicability.

[0006] Technical solution: The present invention provides a normally closed gallium nitride integrated device with a large threshold voltage, the integrated device comprising, from bottom to top, a silicon carbide substrate layer, an aluminum nitride nucleation layer, a relaxation layer A, a relaxation layer B, an aluminum gallium nitride buffer layer, a gallium nitride channel, and an aluminum gallium nitride barrier layer.

[0007] The aluminum gallium nitride barrier layer has a source and a drain at both ends on its surface, and an insulating layer A and an insulating layer B are provided on the surface of the aluminum gallium nitride barrier layer between the source and the drain.

[0008] The insulating layer B has a gate layer A on its surface, and the insulating layer A and the gate layer A have graphene thin film electrodes on their surfaces; the left side of the graphene thin film electrode has an insulating layer C, and the insulating layer C has a gate layer B and an aluminum electrode layer disposed on the gate layer C.

[0009] Among them, insulating layer A, insulating layer B and insulating layer C are hexagonal boron nitride materials;

[0010] The insulating layer A, insulating layer C, and gate layer B form the main gate, and the insulating layer B and gate layer A form the sub-gate, which are connected by a graphene thin film electrode to form a series-parallel hybrid dual HEMT integrated structure; wherein, gate layer A and gate layer B are p-type gallium nitride materials.

[0011] Preferably, the relaxor layer A is Al. 0 .5 Ga 0 .5 N material, wherein the relaxation layer B is Al 0 .25 Ga 0 .75 N material.

[0012] Preferably, a silicon dioxide layer is provided between the insulating layer A and the insulating layer B.

[0013] Preferably, the main gate and the graphene film electrode are connected when the voltage applied to the aluminum electrode layer is greater than 2.5V.

[0014] Preferably, when the voltage applied to the aluminum electrode layer is greater than 3.7V, the main gate is connected to the sub-gate through the graphene thin film electrode.

[0015] This invention also discloses a method for fabricating a normally closed gallium nitride integrated device, comprising the following steps:

[0016] Step S1: Place a silicon carbide substrate with a thickness of 2-3 μm in the reaction chamber of the MOCVD system and anneal it under a protective atmosphere of H2 and NH3 at 900-1000℃.

[0017] Step S2: Using trimethylaluminum as the Al source, trimethylgallium as the Ga source, ammonia as the N source, and hydrogen and nitrogen as carrier gases, a 4-6 nm thick aluminum nitride nucleation layer and a 0.2-0.3 μm thick Al layer are formed from bottom to top on a silicon carbide substrate. 0.5 Ga 0.5 Relaxation layer A of N material, and Al layer with a thickness of 0.2-0.3 μm. 0.25 Ga 0.75 N material relaxation layer B, 1-1.5μm thick Al 0.05 Ga 0.95 The structure consists of an N-type aluminum gallium nitride buffer layer, a 0.2-0.25 μm thick gallium nitride channel, and a 10-25 nm thick Al layer. 0.12 Ga 0.88 An aluminum gallium nitride barrier layer of material N;

[0018] Step S3: Under normal pressure, 850-1000℃, and a protective atmosphere of argon and hydrogen, ammonia borane powder is loaded onto copper foil using CVD or APCVD to form hexagonal boron nitride insulating layers A, B, and C. Insulating layers A and B are then transferred to Al... 0.12 Ga 0.88 Surface of aluminum gallium nitride barrier layer of material N;

[0019] Step S4: A 1-3 μm thick SiO2 layer is deposited on the surface of insulating layer A and insulating layer B using plasma-enhanced chemical vapor deposition. Then, a 1.5-2.0 μm thick photoresist is used as a mask to dry etch part of the SiO2 layer and remove excess photoresist, forming a silicon dioxide layer between insulating layer A and insulating layer B.

[0020] Step S5: A Ti / Al / Ti / Au multilayer metal structure is deposited on the surface of the aluminum gallium nitride barrier layer using magnetron sputtering. After a lift-off process, the source and drain electrodes with ohmic contacts are formed by annealing at 800-900℃ and in a N2 atmosphere for 45-55s.

[0021] Step S6: Generate a p-type gallium nitride material with a thickness of 4.4-30 nm on the surface of insulating layer B as gate layer A, and then anneal it at a high temperature of 700-900℃;

[0022] Step S7: Extract the relative permittivity ε r Graphene ink with a density of 11 was screen-printed onto insulating layer A, silicon dioxide layer and gate layer A at a speed of 200-220 mm / s under constant pressure to form a graphene thin film electrode with uniform thickness.

[0023] Step S8: Transfer the insulating layer C obtained in step S3 to the left side of the graphene thin film electrode surface;

[0024] Step S9: Using the same process as in step S6, a p-type gallium nitride material with a thickness of 4.4-30 nm is formed on the surface of the insulating layer C as the gate layer B;

[0025] Step S 10 An aluminum metal layer is deposited on the surface of the gate layer B, and an aluminum electrode layer is formed by etching.

[0026] Preferably, the insulation layer transfer steps are as follows:

[0027] Step S 31 PMMA was coated onto the surfaces of insulating layers A, B, and C, and the metal foil was removed by etching with a chemical etchant.

[0028] Step S 32 The chemical etchant residue on the back of insulation layers A, B, and C was removed using a dilute hydrochloric acid solution.

[0029] Step S 33 The insulating layers A, B, and C containing PMMA are transferred to their respective workstations, and the residual PMMA after transfer is removed using acetone.

[0030] Step S 34 After the transfer is completed, annealing is carried out at 480-520℃ for 2.5-3.0 h to obtain insulating layer A, insulating layer B, and insulating layer C with improved crystal quality.

[0031] Preferably, the preparation steps of the aluminum electrode layer are as follows:

[0032] Step S 101 Open the evaporation chamber, bind the Al metal to the tungsten wire, and clamp the tungsten wire to the electrode post of the evaporation stage. Place the silicon carbide sample covered with the electrode mold directly above the location where the tungsten wire is bound to the metal. After closing the bell jar, evacuate the chamber pressure to 10. -3 Below Pa;

[0033] Step S 102 Turn on the evaporation switch to start Al metal evaporation. Slowly adjust the voltage knob and continue to increase the voltage until the Al metal on the tungsten wire is completely evaporated. After the Al metal evaporation is complete, adjust the voltage knob to 0. Turn on the molecular pump and mechanical pump to completely eliminate the Al vapor in the chamber.

[0034] Step S 103 Turn off the molecular pump and mechanical pump, turn on the gas filling switch, and after the gas filling is complete, raise the bell jar, take out the sample after the electrode is vapor-deposited, and perform electrode annealing to form ohmic contact; the annealing equipment is a high-temperature tube furnace, the annealing temperature is 850-900℃, the annealing time is 4-6 min, and the annealing atmosphere is hydrogen.

[0035] Step S104 A 2-3 μm thick SiO2 layer was deposited on the sample surface using plasma-enhanced chemical vapor deposition; then, the SiO2 was dry etched using a 1.8-2.0 μm thick photoresist as a mask.

[0036] Step S 105 The sample is placed in the reaction chamber and aluminum is etched using Cl2 and BCl3 to form an aluminum electrode layer, and the residual SiO2 layer and photoresist on the device surface are removed.

[0037] The working principle of the normally closed gallium nitride HEMT integrated device of the present invention is as follows:

[0038] The natural structure of crystalline GaN is a wurtzite hexagonal structure. This structure exhibits strong chemical and mechanical stability, allowing it to withstand high temperatures without decomposition. The wurtzite crystal structure endows GaN with piezoelectric properties, resulting in GaN transistors having significantly higher conductivity compared to silicon or silicon carbide. The piezoelectric effect of GaN is primarily caused by the displacement of charged ions within the crystal lattice. When the lattice is subjected to strain, the deformation causes minute movements of atoms within the lattice, generating an electric field. The stronger the strain, the larger the electric field. The structure of a normally open gallium nitride (GaN) HEMT is shown below. Figure 8 As shown, by growing an aluminum gallium nitride (AlGaN) barrier layer on a GaN crystal, strain can be generated at the interface. This strain induces a two-dimensional electron gas (2DEG). When an electric field is applied, the 2DEG can effectively conduct current, and it exhibits high conductivity. The high concentration and high mobility of electrons are the basis of gallium nitride (GaN) HEMTs. The basic structure of a normally-on GaN transistor is similar to other power transistors, including a gate (G), a source (S), and a drain (D). The source and drain form an ohmic contact with the underlying 2DEG through the top AlGaN layer, allowing current to flow between them. When the 2DEG is depleted, a semi-insulating gallium nitride buffer layer blocks the current flow. The gate is located on top of the AlGaN layer. To deplete the 2DEG, a negative voltage is applied to the gate relative to the drain and source, depleting the electrons in the 2DEG. This type of transistor is called a normally-on high electron mobility transistor (HEMT).

[0039] However, normally open (NOT) devices are inconvenient to use in power conversion applications because a negative bias voltage must be applied to the gate of the power device before the power converter can be turned on; otherwise, the device will short-circuit. NOT devices, however, are not subject to this limitation. Even with zero gate bias, NOT devices are always off until a positive voltage is applied to the gate, at which point current will form between the source and drain. NOT HEMTs do not have minority carrier conduction, so the integrated device operates similarly to a diode; when the forward bias voltage between the gate and drain is removed, the device immediately turns off. Currently, the most common method is to achieve NOT devices by growing a positively charged p-GaN gate layer on top of an aluminum gallium nitride (AlGaN) barrier layer. This invention also utilizes the p-GaN growth method to fabricate a NOT gallium nitride (GaN) HEMT device. Figure 6 This is a schematic diagram comparing the energy bands of normally open (HHEMT) and normally closed (HHEMT). The conduction process of a normally closed (HHEMT) with a p-GaN gate layer can be roughly divided into three stages: The first stage is when the applied gate voltage is less than the threshold voltage (0V < 0V). V G < V TH In the first stage, the heterojunction band begins to bend, but the conduction band bottom remains above the Fermi level, the 2DEG channel is pinched off, and the device cannot conduct; in the second stage, when the applied gate voltage is greater than the threshold voltage but less than the built-in voltage between the p-GaN gate layer and the barrier layer ( V TH < V G < V F The heterojunction band continues to bend, causing the conduction band bottom to lie below the Fermi level. 2DEG begins to recover, the channel turns on, and drain and source currents are generated after applying a drain bias voltage, but the current is relatively small at this time. In the third stage, when the applied gate voltage is greater than the built-in voltage between the p-GaN gate layer and the barrier layer ( In the p-GaN gate layer, holes accumulate in large numbers at the under-gate channel interface under the influence of the gate electric field. These holes attract a large number of electrons from the source to the under-gate channel interface. At this time, these electrons will drift directionally under the influence of the drain bias voltage, generating a large drain-source current. Since the mobility of holes is much smaller than that of electrons, the holes remain almost stationary.

[0040] Based on the above principle, this invention introduces insulating layers A, B and C of two-dimensional material hexagonal boron nitride, and grows an insulating layer C on the aluminum gallium nitride barrier layer and below the p-type gallium nitride gate layer B. When an external circuit applies a voltage to the gate, conventional HEMT integrated devices will turn on at approximately 1.8V. However, due to the presence of the insulating layer C in the integrated device structure, the main gate of the integrated device cannot be turned on when the external voltage is below 2.5V. Only when the voltage applied to the gate exceeds 2.5V does the insulating layer C tunnel through and turn on, allowing the voltage to enter the graphene film electrode below the insulating layer C. Simultaneously, because there is another insulating layer A below the graphene film electrode, the voltage does not directly enter the aluminum gallium nitride barrier layer. The voltage is then conducted along the graphene film electrode to the p-GaN gate layer A of the second HEMT structure (sub-gate). Due to the voltage division by the hexagonal boron nitride insulating layer C in the first HEMT structure (main gate), the applied voltage is insufficient to turn on the sub-gate. Therefore, the voltage applied to the gate needs to be further increased. When the voltage applied to the gate increases to 3.7V, both the main gate and the sub-gate can turn on simultaneously, at which point the integrated device can be fully turned on. The integrated device structure proposed in this invention effectively utilizes the insulating properties of hexagonal boron nitride (HNB) to achieve voltage division. Furthermore, due to the tunneling effect of HNB, the material can conduct at sufficiently high voltages, enabling the HEMT device to operate normally. Based on this, a special design connects the main gate side and the sub-gate side in a series-parallel hybrid manner to form a dual HEMT integrated structure, further increasing the threshold voltage of the integrated device to approximately 3.7V, meeting the needs of practical applications. Moreover, the hexagonal boron nitride in the proposed structure has a lattice match with graphene and a similar fabrication process, reducing the fabrication difficulty. In addition, the capacitance of an integrated device is affected by the device width. This invention features two p-type gallium nitride gate layers, A and B. The integrated device structure of this invention miniaturizes the gate layer area, increasing the device width and enabling capacitance control, thus enhancing the device's frequency characteristics. Due to the increased threshold voltage of the integrated device, the impact of voltage fluctuations when a low voltage is applied to the gate is reduced, thus enhancing the device's immunity to voltage ripple interference.

[0041] Beneficial Effects: Compared with existing technologies, this invention has the following outstanding advantages: 1. The insulating layer prepared by this invention using a two-dimensional novel material, hexagonal boron nitride, acts as a voltage divider, enhancing the gate withstand voltage capability of the normally closed gallium nitride HEMT structure and improving the threshold voltage of the integrated device. 2. By utilizing the insulating layer of hexagonal boron nitride material and connecting two HEMT structures in a series-parallel hybrid manner through graphene thin film electrodes, a dual HEMT integrated structure is formed, further increasing the threshold voltage of the normally closed gallium nitride HEMT integrated device to 3.7V. 3. Since the threshold voltage of the gallium nitride HEMT device is increased to 3.7V, when the voltage of the external circuit is lower than this threshold voltage and fluctuations occur, it will not have a serious impact on the integrated device, thus improving the anti-interference capability. 4. The dual HEMT integrated structure formed by this invention increases the width of the integrated device, which can play a role in regulating capacitance and enhancing the overall frequency characteristics of the integrated device. 5. This invention uses graphene thin film as an electrode. This material has a lattice match with hexagonal boron nitride material and has good conductivity. There is good complementarity between the two materials. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the normally closed gallium nitride HEMT integrated device of the present invention;

[0043] Figure 2 For integrated devices with an applied gate voltage of 0< V G Equivalent circuit diagram of the integrated device's on-state at <1.8V;

[0044] Figure 3 For integrated devices with an applied gate voltage of 1.8V < V G Equivalent circuit diagram of the integrated device's on-state at <2.5V;

[0045] Figure 4 For integrated devices with an applied gate voltage of 2.5V < V G Equivalent circuit diagram of the integrated device's on-state at <3.7V;

[0046] Figure 5 For integrated devices with an applied gate voltage of 3.7V < V G Equivalent circuit diagram of the on-state of integrated devices;

[0047] Figure 6 This is a schematic diagram comparing the band structures of normally open and normally closed HEMTs.

[0048] Figure 7 This is a distribution diagram showing the effect of aluminum gallium nitride barrier layer thickness and aluminum mole fraction on integrated devices;

[0049] Figure 8 This is a schematic diagram of a normally open gallium nitride HEMT device.

[0050] Figure reference numerals: 1. Silicon carbide substrate; 2. Aluminum nitride nucleation layer; 3. Relaxation layer A; 4. Relaxation layer B; 5. Aluminum gallium nitride buffer layer; 6. Gallium nitride channel; 7. Aluminum gallium nitride barrier layer; 8. Source; 9. Drain; 10. Insulating layer A; 11. Insulating layer B; 12. Silicon dioxide layer; 13. Gate layer A; 14. Graphene thin film electrode; 15. Insulating layer C; 16. Gate layer B; 17. Aluminum electrode layer. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will be described in conjunction with the accompanying drawings of the embodiments of the present invention. Figure 1-8 The technical solutions of the embodiments of the present invention will be clearly and completely described herein. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0052] like Figure 1 As shown, this invention discloses a normally closed gallium nitride integrated device with a high threshold voltage. The integrated device includes, from bottom to top, a silicon carbide substrate layer 1, an aluminum nitride nucleation layer 2, a relaxation layer A 3, a relaxation layer B 4, an aluminum gallium nitride buffer layer 5, a gallium nitride channel 6, and an aluminum gallium nitride barrier layer 7; the relaxation layer A 3 is Al 0 .5 Ga 0 .5 N material, relaxor layer B4 is Al 0 .25 Ga 0 .75 N-material; A source electrode 8 and a drain electrode 9 are provided at both ends of the surface of the aluminum gallium nitride barrier layer 7. An insulating layer A 10 and an insulating layer B 11 are provided between the source electrode 8 and the drain electrode 9 on the surface of the aluminum gallium nitride barrier layer 7. Insulating layers A 10 and B 11 are made of hexagonal boron nitride. A silicon dioxide layer 12 is provided between insulating layers A 10 and B 11, serving to isolate insulating layers A and B. A gate layer A 13 is provided on the surface of insulating layer B 11, and graphene thin film electrodes 14 are provided on the surfaces of insulating layers A 10 and A 13. An insulating layer C 15 is provided on the left side of the surface of graphene thin film electrode 14. Insulating layer C 15 is made of hexagonal boron nitride. A gate layer B 16 and an aluminum electrode layer 17 are provided on the surface of insulating layer C 15. Gate layers A 13 and B 16 are made of p-type gallium nitride. Insulating layers A 10 and C 16 are provided on the surface of insulating layer C 15. The main gate, consisting of gate layer B15 and gate layer B16, and the secondary gate, consisting of insulating layer B11 and gate layer A13, are connected by graphene thin film electrode 14 to form a series-parallel hybrid dual HEMT integrated structure.

[0053] The insulating layers A, B, and C of this invention utilize a novel material, hexagonal boron nitride (h-BN). This material not only possesses advantages such as low density, high melting point, low hardness, thermal shock resistance, and good machinability, but also exhibits excellent properties including high temperature resistance, low coefficient of thermal expansion, high thermal conductivity, low dielectric constant, and reliable electrical insulation performance. Hexagonal boron nitride is a white powdery material with a crystal structure very similar to graphite, and their physicochemical properties are also quite similar. Therefore, hexagonal boron nitride is also known as "white graphite," and it has important applications in fields such as thermal conductivity, lubrication, hydrogen storage, battery separator materials, high-temperature anti-oxidation coatings, and catalysis. This invention uses h-BN as the insulating layer material, which has good thermal and dielectric stability. An h-BN insulating layer A10, insulating layer B11, or insulating layer C15 is introduced on the surface of the aluminum gallium nitride barrier layer 7 and below the p-GaN gate layers A13 and B16. When the applied voltage to the gate layer is low, the insulating layer material cannot pass through. Only when the applied bias voltage is sufficiently high can the h-BN insulating layer undergo tunneling, at which point the insulating layer material becomes conductive, allowing the integrated device to function normally. This method can increase the threshold voltage of gallium nitride HEMT devices to a certain extent, but it is difficult to increase the threshold voltage above 3V. Further improvements to the HEMT structure are still needed to further increase the threshold voltage of the integrated device above 3V.

[0054] As is well known, theoretically, connecting two HEMT integrated devices in series can increase the applied voltage. However, this common series connection method is not feasible in gallium nitride (GaN) HEMT devices. This is because HEMT devices use two materials with different band gaps to form a heterojunction to provide a channel for charge carriers, unlike metal-oxide-semiconductor (MOSFETs) which directly use doped semiconductors instead of a junction to form the conductive channel. Furthermore, HEMT devices are three-terminal voltage-controlled devices, not typical two-terminal ones. They have three electrodes: gate, source, and drain. Therefore, the connection method between GaN HEMT device structures needs to be designed individually; otherwise, the HEMT device cannot function properly or achieve its full functionality, let alone achieve the goal of increasing the threshold voltage. This invention employs a unique dual-HEMT integrated structure. By combining a graphene thin-film electrode with an insulating layer of hexagonal gallium nitride (GaN), two insulating layers, A10 and C15, are grown beneath the gate layer B16 of a conventional p-type GaN HEMT structure. One end of a graphene thin-film electrode 14 is inserted between insulating layers C15 and A10, connecting the main and sub-gates of the p-GaN device. This achieves a unique series-parallel hybrid connection between the two HEMT devices, further increasing the threshold voltage of the GaN HEMT device to over 3V. Furthermore, the insulating layers A10 and C15, made of hexagonal boron nitride, possess similar properties to the graphene thin-film electrode 14, exhibiting complementarity between the two materials. The normally closed GaN integrated device of this invention exhibits a high threshold voltage and excellent electrical performance, effectively improving the threshold voltage of GaN HEMTs and meeting various application scenarios requiring high threshold voltage GaN HEMT devices.

[0055] The equivalent circuit diagram of the normally closed gallium nitride HEMT integrated device of the present invention is as follows: Figure 2-5 As shown, the hexagonal boron nitride insulating layer A10, insulating layer B11, and insulating layer C15 in the proposed integrated device structure can be equivalent to resistors with large resistance values, undertaking the voltage division function. Figure 2 As shown, when the gate voltage applied to the main gate by the external circuit is less than 1.8V, the gate layer B16 of the integrated device cannot conduct. Figure 3 In this circuit, when the external circuit applies a gate voltage greater than 1.8V and less than 2.5V, the gate layer B16 can be turned on. However, due to the presence of the introduced insulating layer C15, the applied voltage cannot pass through this insulating layer C15. For example... Figure 4In the process, when the external circuit applies a voltage to the main gate that is greater than 2.5V but less than 3.7V, the insulating layer C15 will tunnel through, allowing the voltage to pass through it and turn on the main gate. However, when the voltage flows through the graphene thin film electrode 14 to the gate layer A13, the voltage division effect of the p-type gallium nitride gate layer A13 and the insulating layer B11 prevents the applied voltage from turning on the sub-gate, thus the integrated device remains unconducted. Figure 5 As shown, when the external circuit applies a voltage to the main gate that is increased to more than 3.7V, the main gate side and the sub-gate side are simultaneously turned on, thereby fully turning on the integrated device and significantly improving the threshold voltage of the normally closed gallium nitride integrated device.

[0056] Example 1: A method for fabricating a normally closed gallium nitride integrated device according to the present invention includes the following steps:

[0057] Step S1: Place the 2μm thick silicon carbide substrate 1 in the reaction chamber of the MOCVD system and anneal it under a protective atmosphere of 900℃, H2 and NH3;

[0058] Step S2: Using trimethylaluminum as the Al source, trimethylgallium as the Ga source, ammonia as the N source, and hydrogen and nitrogen as carrier gases, a 5 nm thick aluminum nitride nucleation layer 2 and a 0.25 μm thick Al layer are formed from bottom to top on the silicon carbide substrate 1. 0.5 Ga 0.5 N material relaxation layer A 3, 0.25μm thick Al 0.25 Ga 0.75 N material relaxation layer B 4, 1.25μm thick Al 0.05 Ga 0.95 The structure consists of an N-type aluminum gallium nitride buffer layer (5), a 0.2 μm thick gallium nitride channel (6), and a 14 nm thick Al layer (7). 0.12 Ga 0.88 7. An aluminum gallium nitride barrier layer of N material;

[0059] Step S3: Under normal pressure, 850℃, and a protective atmosphere of argon and hydrogen, ammonia borane powder is loaded onto copper foil using CVD or APCVD to form hexagonal boron nitride insulating layers A10, B11, and C15. Insulating layers A10 and B11 are then transferred to Al... 0.12 Ga 0.88 The surface of the N-material aluminum gallium nitride barrier layer 7; the specific transfer steps of the insulating layer are as follows:

[0060] Step S 31 The surfaces of insulating layers A10, B11, and C15 are coated with PMMA (polymethyl methacrylate), and the metal foil is removed by etching with a chemical etchant.

[0061] Step S 32 The chemical etchant residue on the back of insulation layers A10, B11, and C15 was removed using a dilute hydrochloric acid solution.

[0062] Step S 33 The insulating layers A 10, B 11, and C 15 containing PMMA are transferred to their respective workstations, and the residual PMMA after transfer is removed using acetone.

[0063] Step S 34 After the transfer was completed, the layers were annealed at 480℃ for 3.0 h to obtain insulating layers A 10, B 11, and C 15 with improved crystal quality.

[0064] Step S 4： A 2 μm thick SiO2 layer was deposited on the surfaces of insulating layer A 10 and insulating layer B 11 using plasma-enhanced chemical vapor deposition. Then, using a 1.8 μm thick photoresist as a mask, part of the SiO2 layer was dry etched and excess photoresist was removed to form a silicon dioxide layer 12 between insulating layer A 10 and insulating layer B 11.

[0065] Step S5: A Ti / Al / Ti / Au multilayer metal structure is deposited on the surface of the aluminum gallium nitride barrier layer 7 using magnetron sputtering. After a stripping process, the source 8 and drain 9 with ohmic contacts are formed by annealing at 800℃ and N2 atmosphere for 55s.

[0066] Step S6: A 15 nm thick p-type gallium nitride material is formed on the surface of the insulating layer B11 as the gate layer A13, and then annealed at a high temperature of 700°C.

[0067] Step S7: Extract the relative permittivity ε r The graphene ink with a density of 11 was screen-printed on the insulating layer A10, the silicon dioxide layer 12 and the gate layer A13 at a speed of 200 mm / s under constant pressure to form a graphene thin film electrode 14 with uniform thickness.

[0068] Step S8: Transfer the insulating layer C15 obtained in step S3 to the left side of the graphene thin film electrode 14 surface;

[0069] Step S9: Using the same process as in step S6, a 15 nm thick p-type gallium nitride material is formed on the surface of the insulating layer C15 as the gate layer B16;

[0070] Step S 10 An aluminum metal layer is deposited on the surface of the gate layer B16, and an aluminum electrode layer 17 is formed by etching. The specific fabrication steps of the aluminum electrode layer 17 are as follows:

[0071] Step S 101 Open the evaporation chamber, bind the Al metal to the tungsten wire, and clamp the tungsten wire to the electrode post of the evaporation stage. Place the silicon carbide sample covered with the electrode mold directly above the location where the tungsten wire is bound to the metal. After closing the bell jar, evacuate the chamber pressure to 10. -3 Below Pa;

[0072] Step S 102 Turn on the evaporation switch to start Al metal evaporation. Slowly adjust the voltage knob and continue to increase the voltage until the Al metal on the tungsten wire is completely evaporated. After the Al metal evaporation is complete, adjust the voltage knob to 0. Turn on the molecular pump and mechanical pump to completely eliminate the Al vapor in the chamber.

[0073] Step S 103 : Turn off the molecular pump and mechanical pump, turn on the gas filling switch, raise the bell jar after the gas filling is completed, take out the sample after the electrode is vapor-deposited, and perform electrode annealing to form ohmic contact; the annealing equipment is a high-temperature tube furnace, the annealing temperature is 850℃, the annealing time is 6 min, and the annealing atmosphere is hydrogen.

[0074] Step S 104 A 2.5 μm thick SiO2 layer was deposited on the sample surface using plasma-enhanced chemical vapor deposition; then, the SiO2 was dry etched using a 1.8 μm thick photoresist as a mask.

[0075] Step S 105 The sample is placed in the reaction chamber and aluminum is etched using Cl2 and BCl3 to form an aluminum electrode layer 17, and the residual SiO2 layer and photoresist on the device surface are removed.

[0076] Example 2: A method for fabricating a normally closed gallium nitride integrated device according to the present invention includes the following steps:

[0077] Step S1: Place the 2.5 μm thick silicon carbide substrate 1 in the reaction chamber of the MOCVD system and anneal it at 1000 °C in a protective atmosphere of H2 and NH3.

[0078] Step S2: Using trimethylaluminum as the Al source, trimethylgallium as the Ga source, ammonia as the N source, and hydrogen and nitrogen as carrier gases, a 5 nm thick aluminum nitride nucleation layer 2 and a 0.25 μm thick Al layer are formed from bottom to top on the silicon carbide substrate 1. 0.5 Ga 0.5 N material relaxation layer A 3, 0.25μm thick Al 0.25 Ga 0.75 N material relaxation layer B 4, 1.25μm thick Al 0.05 Ga 0.95The structure consists of an N-type aluminum gallium nitride buffer layer (5), a 0.2 μm thick gallium nitride channel (6), and a 14 nm thick Al layer (7). 0.12 Ga 0.88 7. An aluminum gallium nitride barrier layer of N material;

[0079] Step S3: Under normal pressure, 1000℃, and a protective atmosphere of argon and hydrogen, ammonia borane powder is loaded onto copper foil using CVD or APCVD to form hexagonal boron nitride insulating layers A10, B11, and C15. Insulating layers A10 and B11 are then transferred to Al... 0.12 Ga 0.88 The surface of the N-material aluminum gallium nitride barrier layer 7; the specific transfer steps of the insulating layer are as follows:

[0080] Step S 31 The surfaces of insulating layers A10, B11, and C15 are coated with PMMA (polymethyl methacrylate), and the metal foil is removed by etching with a chemical etchant.

[0081] Step S 32 The chemical etchant residue on the back of insulation layers A10, B11, and C15 was removed using a dilute hydrochloric acid solution.

[0082] Step S 33 The insulating layers A 10, B 11, and C 15 containing PMMA are transferred to their respective workstations, and the residual PMMA after transfer is removed using acetone.

[0083] Step S 34 After the transfer was completed, the layers were annealed at 520℃ for 2.5 h to obtain insulating layers A10, B11, and C15 with improved crystal quality.

[0084] Step S 4： A 2 μm thick SiO2 layer was deposited on the surfaces of insulating layer A 10 and insulating layer B 11 using plasma-enhanced chemical vapor deposition. Then, using a 1.8 μm thick photoresist as a mask, part of the SiO2 layer was dry etched and excess photoresist was removed to form a silicon dioxide layer 12 between insulating layer A 10 and insulating layer B 11.

[0085] Step S5: A Ti / Al / Ti / Au multilayer metal structure is deposited on the surface of the aluminum gallium nitride barrier layer 7 using magnetron sputtering. After a lift-off process, the source 8 and drain 9 with ohmic contact are formed by annealing at 900℃ and N2 atmosphere for 45s.

[0086] Step S6: A 15 nm thick p-type gallium nitride material is formed on the surface of the insulating layer B11 as the gate layer A13, and then annealed at a high temperature of 900 °C.

[0087] Step S7: Extract the relative permittivity ε r The graphene ink with a density of 11 was screen-printed on the insulating layer A10, the silicon dioxide layer 12 and the gate layer A13 at a speed of 220 mm / s under constant pressure to form a graphene thin film electrode 14 with uniform thickness.

[0088] Step S8: Transfer the insulating layer C15 obtained in step S3 to the left side of the graphene thin film electrode 14 surface;

[0089] Step S9: Using the same process as in step S6, a 15 nm thick p-type gallium nitride material is formed on the surface of the insulating layer C15 as the gate layer B16;

[0090] Step S 10 An aluminum metal layer is deposited on the surface of the gate layer B16, and an aluminum electrode layer 17 is formed by etching. The specific fabrication steps of the aluminum electrode layer 17 are as follows:

[0091] Step S 101 Open the evaporation chamber, bind the Al metal to the tungsten wire, and clamp the tungsten wire to the electrode post of the evaporation stage. Place the silicon carbide sample covered with the electrode mold directly above the location where the tungsten wire is bound to the metal. After closing the bell jar, evacuate the chamber pressure to 10. -3 Below Pa;

[0092] Step S 102 Turn on the evaporation switch to start Al metal evaporation. Slowly adjust the voltage knob and continue to increase the voltage until the Al metal on the tungsten wire is completely evaporated. After the Al metal evaporation is complete, adjust the voltage knob to 0. Turn on the molecular pump and mechanical pump to completely eliminate the Al vapor in the chamber.

[0093] Step S 103 : Turn off the molecular pump and mechanical pump, turn on the gas filling switch, raise the bell jar after the gas filling is completed, take out the sample after the electrode is vapor-deposited, and perform electrode annealing to form ohmic contact; the annealing equipment is a high-temperature tube furnace, the annealing temperature is 900℃, the annealing time is 4 min, and the annealing atmosphere is hydrogen.

[0094] Step S 104 A 2.5 μm thick SiO2 layer was deposited on the sample surface using plasma-enhanced chemical vapor deposition; then, the SiO2 was dry etched using a 1.8 μm thick photoresist as a mask.

[0095] Step S 105 The sample is placed in the reaction chamber and aluminum is etched using Cl2 and BCl3 to form an aluminum electrode layer 17, and the residual SiO2 layer and photoresist on the device surface are removed.

[0096] Example 3: A method for fabricating a normally closed gallium nitride integrated device according to the present invention includes the following steps:

[0097] Step S1: Place the 2.5 μm thick silicon carbide substrate 1 in the reaction chamber of the MOCVD system and anneal it under a protective atmosphere of 950 °C, H2 and NH3;

[0098] Step S2: Using trimethylaluminum as the Al source, trimethylgallium as the Ga source, ammonia as the N source, and hydrogen and nitrogen as carrier gases, a 5 nm thick aluminum nitride nucleation layer 2 and a 0.25 μm thick Al layer are formed from bottom to top on the silicon carbide substrate 1. 0.5 Ga 0.5 N material relaxation layer A 3, 0.25μm thick Al 0.25 Ga 0.75 N material relaxation layer B 4, 1.25μm thick Al 0.05 Ga 0.95 The structure consists of an N-type aluminum gallium nitride buffer layer (5), a 0.2 μm thick gallium nitride channel (6), and a 14 nm thick Al layer (7). 0.12 Ga 0.88 7. An aluminum gallium nitride barrier layer of N material;

[0099] Step S3: Under normal pressure, 900℃, and a protective atmosphere of argon and hydrogen, ammonia borane powder is loaded onto copper foil using CVD or APCVD to form hexagonal boron nitride insulating layers A10, B11, and C15. Insulating layers A10 and B11 are then transferred to Al... 0.12 Ga 0.88 The surface of the N-material aluminum gallium nitride barrier layer 7; the specific transfer steps of the insulating layer are as follows:

[0100] Step S 31 The surfaces of insulating layers A10, B11, and C15 are coated with PMMA (polymethyl methacrylate), and the metal foil is removed by etching with a chemical etchant.

[0101] Step S 32 The chemical etchant residue on the back of insulation layers A10, B11, and C15 was removed using a dilute hydrochloric acid solution.

[0102] Step S 33 The insulating layers A 10, B 11, and C 15 containing PMMA are transferred to their respective workstations, and the residual PMMA after transfer is removed using acetone.

[0103] Step S 34After the transfer was completed, the layers were annealed at 500℃ for 2.75 h to obtain insulating layers A10, B11, and C15 with improved crystal quality.

[0104] Step S 4： A 2 μm thick SiO2 layer was deposited on the surfaces of insulating layer A 10 and insulating layer B 11 using plasma-enhanced chemical vapor deposition. Then, a 1.75 μm thick photoresist was used as a mask to dry etch part of the SiO2 layer and remove excess photoresist, forming a silicon dioxide layer 12 between insulating layer A 10 and insulating layer B 11.

[0105] Step S5: A Ti / Al / Ti / Au multilayer metal structure is deposited on the surface of the aluminum gallium nitride barrier layer 7 using magnetron sputtering. After a lift-off process, the source 8 and drain 9 with ohmic contact are formed by annealing at 850℃ and N2 atmosphere for 50s.

[0106] Step S6: A 30 nm thick p-type gallium nitride material is formed on the surface of the insulating layer B11 as the gate layer A13, and then annealed at a high temperature of 800 °C.

[0107] Step S7: Extract the relative permittivity ε r The graphene ink with a density of 11 was screen-printed on the insulating layer A10, the silicon dioxide layer 12 and the gate layer A13 at a speed of 210 mm / s under constant pressure to form a graphene thin film electrode 14 with uniform thickness.

[0108] Step S8: Transfer the insulating layer C15 obtained in step S3 to the left side of the graphene thin film electrode 14 surface;

[0109] Step S9: Using the same process as in step S6, a 4.4 nm thick p-type gallium nitride material is formed on the surface of the insulating layer C15 as the gate layer B16;

[0110] Step S 10 An aluminum metal layer is deposited on the surface of the gate layer B16, and an aluminum electrode layer 17 is formed by etching. The specific fabrication steps of the aluminum electrode layer 17 are as follows:

[0111] Step S 101 Open the evaporation chamber, bind the Al metal to the tungsten wire, and clamp the tungsten wire to the electrode post of the evaporation stage. Place the silicon carbide sample covered with the electrode mold directly above the location where the tungsten wire is bound to the metal. After closing the bell jar, evacuate the chamber pressure to 10. -3 Below Pa;

[0112] Step S 102Turn on the evaporation switch to start Al metal evaporation. Slowly adjust the voltage knob and continue to increase the voltage until the Al metal on the tungsten wire is completely evaporated. After the Al metal evaporation is complete, adjust the voltage knob to 0. Turn on the molecular pump and mechanical pump to completely eliminate the Al vapor in the chamber.

[0113] Step S 103 : Turn off the molecular pump and mechanical pump, turn on the gas filling switch, raise the bell jar after the gas filling is completed, take out the sample after the electrode is vapor-deposited, and perform electrode annealing to form ohmic contact; the annealing equipment is a high-temperature tube furnace, the annealing temperature is 875℃, the annealing time is 5 min, and the annealing atmosphere is hydrogen.

[0114] Step S 104 A 2.5 μm thick SiO2 layer was deposited on the sample surface using plasma-enhanced chemical vapor deposition; then, the SiO2 was dry etched using a 1.9 μm thick photoresist as a mask.

[0115] Step S 105 The sample is placed in the reaction chamber and aluminum is etched using Cl2 and BCl3 to form an aluminum electrode layer 17, and the residual SiO2 layer and photoresist on the device surface are removed.

[0116] The above are preferred embodiments of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A normally closed gallium nitride integrated device with a large threshold voltage, characterized in that, The integrated device comprises, from bottom to top, a silicon carbide substrate layer (1), an aluminum nitride nucleation layer (2), a relaxation layer A (3), a relaxation layer B (4), an aluminum gallium nitride buffer layer (5), a gallium nitride channel (6), and an aluminum gallium nitride barrier layer (7). The aluminum gallium nitride barrier layer (7) has a source electrode (8) and a drain electrode (9) at both ends on its surface. An insulating layer A (10) and an insulating layer B (11) are provided on the surface of the aluminum gallium nitride barrier layer (7) between the source electrode (8) and the drain electrode (9). The insulating layer B (11) has a gate layer A (13) on its surface, and the insulating layer A (10) and the gate layer A (13) have graphene thin film electrodes (14) on their surfaces; the left side of the graphene thin film electrode (14) is provided with an insulating layer C (15) above the insulating layer A (10), and the insulating layer C (15) has a gate layer B (16) and an aluminum electrode layer (17) on the gate layer C; Among them, the insulating layer A (10), insulating layer B (11) and insulating layer C (15) are hexagonal boron nitride materials; The insulating layer A (10), insulating layer C (15) and gate layer B (16) form the main gate and the insulating layer B (11) and gate layer A (13) form the sub-gate, which are connected by graphene thin film electrode (14) to form a series-parallel hybrid dual HEMT integrated structure; wherein, the gate layer A (13) and gate layer B (16) are p-type gallium nitride materials.

2. The normally closed gallium nitride integrated device with a large threshold voltage according to claim 1, characterized in that, The relaxation layer A(3) is Al 0 .5 Ga 0 .5 N material, wherein the relaxor layer B(4) is Al 0 .25 Ga 0 .75 N material.

3. The normally closed gallium nitride integrated device with a large threshold voltage according to claim 1, characterized in that, A silicon dioxide layer (12) is provided between the insulating layer A (10) and the insulating layer B (11).

4. The normally closed gallium nitride integrated device with a large threshold voltage according to claim 1, characterized in that, When the voltage applied to the aluminum electrode layer (17) is greater than 2.5V, the main gate is connected to the graphene film electrode (14).

5. The normally closed gallium nitride integrated device with a large threshold voltage according to claim 4, characterized in that, When the voltage applied to the aluminum electrode layer (17) is greater than 3.7V, the main gate is connected to the sub-gate through the graphene thin film electrode (14).

6. A method for fabricating a normally closed gallium nitride integrated device, characterized in that, A method for fabricating a normally closed gallium nitride integrated device as described in any one of claims 1-5, comprising the following steps: Step S1: Place a silicon carbide substrate layer (1) with a thickness of 2-3 μm in the reaction chamber of the MOCVD system and anneal it under a protective atmosphere of H2 and NH3 at 900-1000℃. Step S2: Using trimethylaluminum as the Al source, trimethylgallium as the Ga source, ammonia as the N source, and hydrogen and nitrogen as carrier gases, an aluminum nitride nucleation layer (2) with a thickness of 4-6 nm and an Al nucleation layer (2) with a thickness of 0.2-0.3 μm are formed from bottom to top on a silicon carbide substrate (1). 0.5 Ga 0.5 N material relaxation layer A (3), 0.2-0.3μm thick Al 0.25 Ga 0.75 N material relaxation layer B (4), 1-1.5μm thick Al 0.05 Ga 0.95 An aluminum gallium nitride buffer layer (5) of N material, a gallium nitride channel (6) with a thickness of 0.2-0.25 μm, and an Al layer with a thickness of 10-25 nm. 0.12 Ga 0.88 (7) An aluminum gallium nitride barrier layer of N material. Step S3: Under normal pressure, 850-1000℃, and a protective atmosphere of argon and hydrogen, ammonia borane powder is loaded onto copper foil using CVD or APCVD to generate hexagonal boron nitride insulating layers A (10), B (11), and C (15). Insulating layers A (10) and B (11) are then transferred to Al. 0.12 Ga 0.88 The surface of the aluminum gallium nitride barrier layer (7) of material N; Step S4: A 1-3 μm thick SiO2 layer is deposited on the surface of insulating layer A (10) and insulating layer B (11) using plasma-enhanced chemical vapor deposition. Then, a 1.5-2.0 μm thick photoresist is used as a mask to dry etch part of the SiO2 layer and remove excess photoresist to form a silicon dioxide layer (12) between insulating layer A (10) and insulating layer B (11). Step S5: A Ti / Al / Ti / Au multilayer metal structure is deposited on the surface of the aluminum gallium nitride barrier layer (7) by magnetron sputtering. After a stripping process, the source (8) and drain (9) with ohmic contact are formed by annealing at 800-900℃ and N2 atmosphere for 45-55s. Step S6: A p-type gallium nitride material with a thickness of 4.4-30 nm is formed on the surface of the insulating layer B (11) as the gate layer A (13), and then annealed at a high temperature of 700-900℃; Step S7: Extract the relative permittivity ε r The graphene ink with a density of 11 was screen-printed on the insulating layer A (10), the silicon dioxide layer (12) and the gate layer A (13) at a speed of 200-220 mm / s under constant pressure to form a graphene thin film electrode (14) with uniform thickness. Step S8: Transfer the insulating layer C (15) obtained in step S3 to the left side of the graphene thin film electrode (14); Step S9: Using the same process as step S6, a p-type gallium nitride material with a thickness of 4.4-30 nm is generated on the surface of the insulating layer C (15) as the gate layer B (16). Step S 10 An aluminum metal layer is deposited on the surface of the gate layer B (16), and an aluminum electrode layer (17) is formed by etching.

7. The method for fabricating a normally closed gallium nitride integrated device according to claim 6, characterized in that, The steps for transferring the insulating layer are as follows: Step S 31 PMMA was coated on the surfaces of insulating layer A (10), insulating layer B (11), and insulating layer C (15), and the metal foil was removed by etching with a chemical etchant. Step S 32 The chemical etchant residue on the back of insulating layer A (10), insulating layer B (11), and insulating layer C (15) was removed using a dilute hydrochloric acid solution. Step S 33 : Transfer the insulating layers A (10), B (11), and C (15) with PMMA to their respective work stations, and remove the residual PMMA after transfer using acetone; Step S 34 After the transfer is completed, the insulation layer A (10), insulation layer B (11), and insulation layer C (15) with improved crystal quality are obtained by annealing at 480-520℃ for 2.5-3.0 h.

8. The method for fabricating a normally closed gallium nitride integrated device according to claim 6, characterized in that, The preparation steps of the aluminum electrode layer (17) are as follows: Step S 101 Open the evaporation chamber, bind the Al metal to the tungsten wire, and clamp the tungsten wire to the electrode post of the evaporation stage. Place the silicon carbide sample covered with the electrode mold directly above the location where the tungsten wire is bound to the metal. After closing the bell jar, evacuate the chamber pressure to 10. -3 Below Pa; Step S 102 Turn on the evaporation switch to start Al metal evaporation. Slowly adjust the voltage knob and continue to increase the voltage until the Al metal on the tungsten wire is completely evaporated. After the Al metal evaporation is complete, adjust the voltage knob to 0. Turn on the molecular pump and mechanical pump to completely eliminate the Al vapor in the chamber. Step S 103 Turn off the molecular pump and mechanical pump, turn on the gas filling switch, and after the gas filling is complete, raise the bell jar, take out the sample after the electrode is vapor-deposited, and perform electrode annealing to form ohmic contact; the annealing equipment is a high-temperature tube furnace, the annealing temperature is 850-900℃, the annealing time is 4-6 min, and the annealing atmosphere is hydrogen. Step S 104 A 2-3 μm thick SiO2 layer was deposited on the sample surface using plasma-enhanced chemical vapor deposition; then, the SiO2 was dry etched using a 1.8-2.0 μm thick photoresist as a mask. Step S 105 The sample is placed in the reaction chamber and aluminum is etched using Cl2 and BCl3 to form an aluminum electrode layer (17), and the residual SiO2 layer and photoresist on the device surface are removed.

Images