A pixel circuit for improving the signal-to-noise ratio of high dynamic range pixel conversion nodes

Abstract

The present invention discloses a pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node, comprising a P-type substrate, a large photodiode, a No. 1 transmission gate, a No. 1 charge-voltage conversion node, a No. 2 transmission gate, a No. 2 charge-voltage conversion node, a No. 3 transmission gate, a No. 3 charge-voltage conversion node, a No. 4 transmission gate, and a small photodiode are arranged on the P-type substrate, a No. 4 charge-voltage conversion node is arranged on the left side of the large photodiode, a charge overflow prevention transistor is connected between the No. 4 charge-voltage conversion node and the large photodiode, the No. 4 charge-voltage conversion node is grounded via a No. 2 lateral overflow integrated capacitor, and a transmission gate of overflowed charge is connected between the No. 4 charge-voltage conversion node and the No. 2 charge-voltage conversion node. The present invention significantly improves the signal-to-noise ratio when the SP1L signal is switched to the SP2H signal while ensuring that the full well capacity of the high dynamic range pixel does not change significantly, and significantly optimizes the imaging quality of the high dynamic pixel.

Description

Technical Field

[0001] The present invention relates to the field of CMOS image sensor pixels, and more particularly to a pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node. Background Art

[0002] CMOS image sensors with high dynamic range are widely used in biomedicine, automobile manufacturing, aerospace, analytical instruments and other fields. Among the many methods in the past, the methods to improve the dynamic range are mainly divided into lateral overflow integrated capacitor (LOFIC), multiple exposure and logarithmic-linear pixel. Although LOFIC has the advantages of simple structure and can effectively collect more photogenerated charges, its disadvantage is that it often takes up a large pixel area; multiple exposure uses the method of alternating long and short exposure to effectively improve the dynamic range, but its ability to solve moving objects is limited and the design of subsequent readout circuits and related algorithms is often more complicated; logarithmic-linear pixels use linear readout when the light is weak and logarithmic readout when the light is strong. It increases the amount of charge that can be collected to a certain extent but introduces nonlinear problems at the same time, which is often very difficult for the design of subsequent readout circuits.

[0003] In many specific applications, high dynamic range CMOS image sensors are often required to maintain good sensitivity in weak light while having a higher dynamic range in strong light conditions. This requires such image sensors to have dual conversion gains, that is, to use high conversion gain to reduce the equivalent number of electrons of read noise in weak light, and to use low conversion gain to increase the amount of charge that can be accommodated by the charge-voltage conversion node (FD) in strong light. Therefore, a pixel structure with two sensitivity units came into being. This type of pixel structure is designed to realize two or more photodiodes (PDs) with different sensitivities, which is similar to the human retina, which has cone cells working in strong light and rod cells working in weak light. With the joint work of the two cells, people can see brighter and dimmer objects at the same time. In this pixel structure with two or more PDs, a small PD with low sensitivity works in brighter conditions, while a large PD with high sensitivity works in darker conditions.

[0004] A method of improving the dynamic range by using dual PD equivalent full well is as follows Figure 1 As shown, it combines LOFIC while constructing dual CG to achieve an expansion of the pixel dynamic range, but the signal-to-noise ratio of the conversion node where the large PD to small PD signal switches (SP1L to SP2H) decreases significantly, which will significantly affect the imaging quality. It has become a problem that cannot be ignored in pixel imaging in this way. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and propose a pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node, which significantly improves the signal-to-noise ratio when the SP1L signal switches to the SP2H signal while ensuring that the full well capacity of the high dynamic range pixel does not change significantly, thereby significantly optimizing the imaging quality of the high dynamic range pixel.

[0006] The objectives of the present invention are achieved through the following technical solutions.

[0007] The pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node of the present invention comprises a P-type substrate, on which a large photodiode, a No. 1 charge-voltage conversion node, a No. 2 charge-voltage conversion node, a No. 3 charge-voltage conversion node, and a small photodiode are sequentially arranged from left to right. The large photodiode and the No. 1 charge-voltage conversion node are connected through a No. 1 transmission gate, the No. 1 charge-voltage conversion node and the No. 2 charge-voltage conversion node are connected through a No. 2 transmission gate, the No. 2 charge-voltage conversion node and the No. 3 charge-voltage conversion node are connected through a No. 3 transmission gate, and the No. 3 charge-voltage conversion node and the small photodiode are connected through a No. 4 transmission gate. The first charge-voltage conversion node and the second charge-voltage conversion node are connected to a voltage source via a source follower and a reset transistor respectively, the source follower outputs the voltage via a selection transistor, the third charge-voltage conversion node is connected to a high voltage signal source via a first lateral overflow integrated capacitor, a fourth charge-voltage conversion node is arranged on the left side of the large photodiode, a charge overflow prevention transistor is connected between the fourth charge-voltage conversion node and the large photodiode, the fourth charge-voltage conversion node is grounded via a second lateral overflow integrated capacitor, and a transmission gate of overflowed charge is connected between the fourth charge-voltage conversion node and the second charge-voltage conversion node.

[0008] The first charge-voltage conversion node is N-type doped, the second charge-voltage conversion node is a MOS capacitor, the third charge-voltage conversion node is a MIM capacitor, and the fourth charge-voltage conversion node is a MIM capacitor.

[0009] The first transmission gate is a transmission gate of a large photodiode, the second transmission gate is a floating diffusion gate, the third transmission gate is a floating capacitor gate, and the fourth transmission gate is a transmission gate of a small photodiode.

[0010] The source follower is a MOS tube, and the transmission gate of the overflow charge is a MOS tube.

[0011] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0012] The present invention adopts a new combination method, which is improved on the basis of the previous pixel with high dynamic range realized by using double CG equivalent full well, and adds a charge overflow prevention transistor AB, a second lateral overflow integrated capacitor LOFIC2 and a transmission gate TG for controlling the overflow charge readout between the second charge-voltage conversion node FD2 and the large photodiode PD1 to form another path, wherein the charge overflow prevention transistor AB and the second lateral overflow integrated capacitor LOFIC2 are used to collect the overflowed charge, and the transmission gate TG for controlling the overflowed charge readout realizes the overflow charge readout operation. This structure increases the full well capacity FWC_PD1 of the large photodiode PD1 by collecting the overflowed charge generated by the large photodiode PD1 when the light is strong, thereby improving the signal-to-noise ratio of the signal conversion node. It should be noted that the P-type region below the charge overflow prevention transistor AB is weakly doped to reduce the potential barrier, so as to facilitate the overflow of photogenerated electrons in the large photodiode PD1 to be effectively collected. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of a pixel circuit for realizing a high dynamic range of large and small PD equivalent full wells;

[0014] Figure 2 yes Figure 1 The timing operation diagram of the pixel circuit in the figure;

[0015] Figure 3 It is a schematic diagram of a pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node according to the present invention;

[0016] Figure 4 yes Figure 3 Timing operation diagram of the pixel circuit in the figure.

[0017] Figure markings: PD1 large photodiode, PD2 small photodiode, FD1 charge-voltage conversion node No. 1, FD2 charge-voltage conversion node No. 2, FD3 charge-voltage conversion node No. 3, FD4 charge-voltage conversion node No. 4, LOFIC1 lateral overflow integrated capacitor No. 1, LOFIC2 lateral overflow integrated capacitor No. 2, TG transmission gate for overflow charge, AB charge overflow prevention transistor, TGL transmission gate No. 1, FDG transmission gate No. 2, FCG transmission gate No. 3, TGS transmission gate No. 4, SEL selection transistor, SF source follower, RST reset transistor, VSS ground, VDD voltage source, FCVDD high voltage signal source. DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings.

[0019] Figure 1The schematic diagram of a pixel circuit for realizing a high dynamic range of large and small PD equivalent full wells mainly includes a P-type substrate, on which a large photodiode PD1, a first charge-voltage conversion node FD1, a second charge-voltage conversion node FD2, a third charge-voltage conversion node FD3, and a small photodiode PD2 are arranged in sequence from left to right. The large photodiode PD1 and the first charge-voltage conversion node FD1 are connected through a first transmission gate TGL, the first charge-voltage conversion node FD1 and the second charge-voltage conversion node FD2 are connected through a second transmission gate FDG, the second charge-voltage conversion node FD2 and the third charge-voltage conversion node FD3 are connected through a third transmission gate FCG, and the third charge-voltage conversion node FD3 and the small photodiode PD2 are connected through a fourth transmission gate TGS.

[0020] The first charge-voltage conversion node FD1 is connected to the voltage source VDD via the source follower SF, and the source follower SF controls the output voltage via the selection transistor SEL. The second charge-voltage conversion node FD2 is connected to the voltage source VDD via the reset transistor RST. The third charge-voltage conversion node FD3 is connected to the high voltage signal source FCVDD via the first lateral overflow integrated capacitor LOFIC1.

[0021] Among them, the first charge-voltage conversion node FD1 is N-type doped, the second charge-voltage conversion node FD2 is a MOS capacitor, and the third charge-voltage conversion node FD3 is a MIM capacitor. The first transmission gate TGL is the transmission gate of the large photodiode PD1, the second transmission gate FDG is a floating diffusion gate, the third transmission gate FCG is a floating capacitor gate, and the fourth transmission gate TGS is the transmission gate of the small photodiode PD2. The source follower SF is a MOS tube.

[0022] Both the large photodiode PD1 and the small photodiode PD2 have two operating modes: high conversion gain mode (HCG mode) and low conversion gain mode (LCG mode). When the large photodiode PD1 is in HCG mode, the signal is SP1H (S1 and R1), and when the large photodiode PD1 is in LCG mode, the signal is SP1L (S2 and R2); when the small photodiode PD2 is in HCG mode, the signal is SP2H (S3 and R4), and when the small photodiode PD2 is in LCG mode, the signal is SP2L (S4 and R4). Among them, R represents a reset signal, and S represents an optical signal.

[0023] The timing diagram of the above pixel circuit is as follows: Figure 2As shown, the signal in the large photodiode PD1 is read out by SP1H (S1 and R1) in HCG mode and SP1L (S2 and R2) in LCG mode. The accumulated charge in the small photodiode PD2 is read out by SP2H (S3 and R4), combined with the charge overflowed from the first lateral overflow integrated capacitor LOFIC1, and read out as SP2L (S4 and R4). In one exposure, four signals are read out from the two photodiodes using four reset signals and four optical signals. Finally, the signals of the large photodiode PD1 and the small photodiode PD2 are linearly combined, and the electrons in the small photodiode PD2 are multiplied by the photodiode response rate a (the ratio of the area of ​​the large photodiode PD1 to that of the small photodiode PD2) to obtain electrons equivalent to the signal of the large photodiode PD1. By continuously synthesizing the four signals SP1H, SP1L, SP2H, and SP2L, a high dynamic range synthetic image is achieved. The equivalent full well calculation formula for the final image sensor is shown in (1):

[0024] FWC_pixel=FWC@(PD2+C M )×a (1)

[0025] Among them, FWC_pixel is the equivalent full well of the pixel, FWC@(PD2+C M ) includes the full well and overflow electrons of the small photodiode PD2, C M It is the total capacitance of the first charge-voltage conversion node FD1, the second charge-voltage conversion node FD2, the third charge-voltage conversion node FD3 and the first lateral overflow integrated capacitor LOFIC1, which is composed of PN junction capacitance, gate overlap capacitance, gate capacitance, metal capacitance and LOFIC. The capacitance of the FD node depends on ion doping and layout design, C M Mainly determined by LOFIC, among which FWC@(PD2+C M ) is calculated as shown in (2):

[0026]

[0027] Where q is the charge of the electron, △V is the voltage swing, and C FD1 , C FD2 , C FD3 and C LOFIC They are the parasitic capacitances of the first charge-voltage conversion node FD1 , the second charge-voltage conversion node FD2 , the third charge-voltage conversion node FD3 and the first lateral overflow integrated capacitor LOFIC1 .

[0028] It can be seen that the equivalent full well of the structure is related to the voltage swing △V and the capacitance C MIt is related to the response rate a, where a and the full well capacity FWC_PD1 of the large photodiode PD1 are also the direct factors affecting the signal-to-noise ratio, as shown in equations (3) and (4). Under the condition of ensuring that the dynamic range does not change significantly, gradually increasing FWC_PD1 can effectively increase the signal-to-noise ratio of the conversion node, thereby improving the imaging quality of the entire pixel.

[0029] N1=FWC_PD1 / a (3)

[0030]

[0031] Where N1 is the initial number of electrons in the small photodiode PD2, SNR is the signal-to-noise ratio when the SP1L signal switches to the SP2H signal, and σ e is the shot noise, σ read is the read noise.

[0032] In the case of achieving high dynamic range by using the traditional method of using large and small PD equivalent full wells, although the larger area ratio achieves a larger dynamic range, it will also affect the serious drop in the signal-to-noise ratio when the signal from the large photodiode PD1 to the small photodiode PD2 is switched (SP1L to SP2H), which will seriously affect the imaging quality of the pixel. The main factor affecting the sharp drop in the signal-to-noise ratio of this node is that the initial number of electrons in the small photodiode PD2 is affected by the full well of the large photodiode PD1 during the switching process, and changes in direct proportion to the full well capacity of the large photodiode PD1. Therefore, the present invention proposes a pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node, such as Figure 3 As shown, on the basis of the above-mentioned existing pixel circuit, a charge overflow prevention transistor AB and a second lateral overflow integrated capacitor LOFIC2 are added to collect the overflowed charge, and an overflowed charge transfer gate TG for controlling the readout of the overflowed charge is added to realize the readout operation of the overflowed charge, thereby changing the second group of signals (SP1L) read out by the large photodiode PD1 to increase the full well capacity of the large photodiode PD1, and significantly increasing FWC_PD1 by collecting the overflowed charge in the large photodiode PD1 under high light intensity and reading it out under the SP1L signal, thereby ensuring that the full well capacity of the high dynamic range pixel does not change significantly, and significantly improving the signal-to-noise ratio when the SP1L signal switches to the SP2H signal, and significantly optimizing the imaging quality of the high dynamic pixel. The specific timing working diagram is shown in Figure 4 shown.

[0033] Specifically, a fourth charge-voltage conversion node FD4 is provided on the left side of the large photodiode PD1, a charge overflow prevention transistor AB is connected between the fourth charge-voltage conversion node FD4 and the large photodiode PD1, the fourth charge-voltage conversion node FD4 is grounded to VSS via the second lateral overflow integrated capacitor LOFIC2, and a transmission gate TG of overflowed charge is connected between the fourth charge-voltage conversion node FD4 and the second charge-voltage conversion node FD2. Among them, the fourth charge-voltage conversion node FD4 is a MIM capacitor. The transmission gate TG of the overflowed charge is a MOS tube, the drain of the MOS tube is connected to the fourth charge-voltage conversion node FD4, and the source of the MOS tube is connected to the second charge-voltage conversion node FD2.

[0034] The working process of the pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node of the present invention is as follows:

[0035] At the beginning of the exposure cycle, first, by opening the No. 1 transmission gate TGL and the transfer gate TG of the overflowing charge, the large photodiode PD1 and the No. 2 lateral overflow integrated capacitor LOFIC2 are reset to reset the photoelectrons, and the No. 4 transmission gate TGS and the No. 3 transmission gate FCG are opened to reset the small photodiode PD2 and the No. 1 lateral overflow integrated capacitor LOFIC1 to reset the photoelectrons. During this period, the No. 2 transmission gate FDG and the reset transistor RST are always open.

[0036] During exposure, the second transmission gate FDG and the reset transistor RST are always in the open state, the first charge-voltage conversion node FD1 and the second charge-voltage conversion node FD2 can be reset all the time, the transfer gate TG of the overflowing charge is closed, and when the light intensity is strong, the charge in the large photodiode PD1 overflows to the fourth charge-voltage conversion node FD4 and the second lateral overflow integrated capacitor LOFIC2 and is stored.

[0037] After the exposure is completed, the signal readout phase begins. First, the reset tube is turned off. After the No. 2 transmission gate FDG is turned off, the R1 signal in SP1H is sampled. The No. 1 transmission gate TGL is opened to transfer the electrons in the large photodiode PD1 to the No. 1 charge-voltage conversion node FD1 and the S1 signal in SP1H is sampled. At this time, the photoelectrons exceeding the capacity of the No. 1 charge-voltage conversion node FD1 remain in the large photodiode PD1. After the sampling is completed, the transmission gate TG and the No. 2 transmission gate FDG of the overflow charge are opened. After the No. 1 transmission gate TGL is opened, the remaining charge in the large photodiode PD1 is completely transferred to the No. 1 charge-voltage conversion node FD1 and the No. 2 charge-voltage conversion node FD2 and sampled and read out together with the overflow charge stored in the No. 2 lateral overflow integrated capacitor LOFIC2. The readout signal is the S2 signal in SP1L. After the sampling is completed, the reset tube is opened again for reset, and the signal at this time is recorded as the R2 signal in SP1L. In this process, SP1H can be read out by double sampling to eliminate KTC noise, while S2 and R2 of the SP1L signal are read out in the opposite order to the original scheme. It selects the incremental reset sampling (DRS) method to read the signal level. Although KTC noise cannot be eliminated by double sampling, the second lateral overflow integrated capacitor LOFIC2 with the fourth charge-voltage conversion node FD4 is large, it can effectively reduce KTC noise.

[0038] The working process of the small photodiode PD2 is basically the same as that in the original scheme. After completing the sampling of the R2 signal, the transmission gate TG of the overflowed charge is closed, and the reset tube is turned on and off once, and then the third transmission gate FCG is opened, and the R3 signal in SP2H is sampled. Then, the fourth transmission gate TGS is opened to completely transfer the photoelectrons accumulated in the small photodiode PD2 to the third charge-voltage conversion node FD3, and the signal level S3 in SP2H at this time is sampled. Therefore, the signal in SP2H can be read out by double sampling operation. After that, the DRS method is also used to read out the signal level SP2L. First, S4 in SP2L with exactly the same voltage is collected in the previous state, and then the reset tube is turned on and off to reset the photoelectrons in the first charge-voltage conversion node FD1, the second charge-voltage conversion node FD2, the third charge-voltage conversion node FD3 and the first lateral overflow integrated capacitor LOFIC1, and R4 in SP2L is sampled at this time.

[0039] Among the eight groups of signals obtained, since the sampling of the S2 signal in SP1L also includes the charge part overflowing from the large photodiode PD1, it effectively increases the full well of the large photodiode PD1, so that the initial number of electrons in the small photodiode PD2 increases significantly when SP1L switches to SP2H, effectively increasing the signal-to-noise ratio during signal switching.

[0040] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. The above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node, comprising a P-type substrate, on which a large photodiode PD1, a first charge-voltage conversion node FD1, a second charge-voltage conversion node FD2, a third charge-voltage conversion node FD3, and a small photodiode PD2 are sequentially arranged from left to right, wherein the large photodiode PD1 and the first charge-voltage conversion node FD1 are connected through a first transmission gate TGL, the first charge-voltage conversion node FD1 and the second charge-voltage conversion node FD2 are connected through a second transmission gate FDG, and the second charge-voltage conversion node FD3 is connected through a second transmission gate FDG. The point FD2 and the third charge-voltage conversion node FD3 are connected through the third transmission gate FCG, the third charge-voltage conversion node FD3 and the small photodiode PD2 are connected through the fourth transmission gate TGS, the first charge-voltage conversion node FD1 and the second charge-voltage conversion node FD2 are connected to the voltage source VDD through the source follower SF and the reset transistor RST respectively, the source follower SF outputs the voltage through the selection transistor SEL, and the third charge-voltage conversion node FD3 is connected to the high voltage signal source FCVDD through the first lateral overflow integrated capacitor LOFIC1, characterized in that: A fourth charge-voltage conversion node FD4 is arranged on the left side of the large photodiode PD1, a charge overflow prevention transistor AB is connected between the fourth charge-voltage conversion node FD4 and the large photodiode PD1, the fourth charge-voltage conversion node FD4 is grounded to VSS via the second lateral overflow integrated capacitor LOFIC2, and a transmission gate TG of overflow charge is connected between the fourth charge-voltage conversion node FD4 and the second charge-voltage conversion node FD2.

2. The pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node according to claim 1, characterized in that: The first charge-voltage conversion node FD1 is N-type doped, the second charge-voltage conversion node FD2 is a MOS capacitor, the third charge-voltage conversion node FD3 is a MIM capacitor, and the fourth charge-voltage conversion node FD4 is a MIM capacitor.

3. The pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node according to claim 1, characterized in that: The first transmission gate TGL is the transmission gate of the large photodiode PD1, the second transmission gate FDG is a floating diffusion gate, the third transmission gate FCG is a floating capacitor gate, and the fourth transmission gate TGS is the transmission gate of the small photodiode PD2.

4. The pixel circuit for improving the signal-to-noise ratio of a high dynamic range pixel conversion node according to claim 1, characterized in that: The source follower SF is a MOS tube, and the transmission gate TG of the overflowed charge is a MOS tube.

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