Circuit board and display device

Abstract

Embodiments of the present application disclose a circuit board and a display device. It adopts the same-layer setting of a first trace group and a second trace group, which means that this embodiment adopts a single-layer trace setting. Compared with the double-layer traces in the prior art, the cost of the embodiments of the present application is lower, and the binding with external components is simpler. In addition, in the embodiments of the present application, the first unit of the first trace group and the second unit of the second trace group are alternately arranged, so that the trace length of adjacent first units plus the trace length of external components is relatively uniform, and the trace length of adjacent second units plus the trace length of external components is also relatively uniform, improving the uniformity of impedance between traces.

Description

Technical Field

[0001] This application relates to the field of display technologies, and more particularly to a circuit board and a display device. Background Art

[0002] Currently, the market demand for narrow bezel models is increasing continuously. Existing narrow bezel models are implemented using a 2 in 1 double-layer flip chip film, that is, integrating a gate driver chip and a source driver chip on the same flip chip film. However, since the flip chip film has double-layer traces, the cost is high and the bonding difficulty is increased. Summary of the Invention

[0003] Embodiments of this application provide a circuit board and a display panel, which can reduce costs and bonding difficulty.

[0004] Embodiments of this application provide a circuit board, which includes:

[0005] A substrate,

[0006] A first trace group, the first trace group is disposed on the substrate, the first trace group includes a plurality of first units, and at least one first signal trace is disposed in each first unit;

[0007] A second trace group, the second trace group is disposed on the same layer as the first trace group, the second trace group includes a plurality of second units, and at least one second signal trace is disposed in each second unit; in a first direction, the first units and the second units are alternately disposed, and the first direction intersects with the extending direction of the first signal traces;

[0008] A first driving chip, the first driving chip is disposed on the substrate and is bonded to the first trace group; and

[0009] A second driving chip, the second driving chip is disposed on the substrate and is bonded to the second trace group.

[0010] Optionally, in some embodiments of this application, the first driving chip includes a first chip body and a plurality of first bonding units, the first bonding units are disposed on a side of the first chip body close to the first trace group, and a reserved space is provided between adjacent two first bonding units;

[0011] The first bonding unit includes at least one first bonding pad, the first bonding pad is bonded to the first signal trace; one of the second units is disposed corresponding to one of the reserved spaces.

[0012] Optionally, in some embodiments of this application, the second signal traces extend from the second driving chip towards the external panel, and the second signal traces pass through the reserved spaces.

[0013] Optionally, in some embodiments of the present application, a second signal trace includes a first segment and a second segment arranged at intervals. The first segment is located on the side of the first driving chip away from the second driving chip, and the second segment is located on the side of the first driving chip close to the second driving chip;

[0014] The first driving chip further includes a plurality of first reserved pads and a plurality of second reserved pads. The first reserved pads are arranged at the reserved space, and the second reserved pads are arranged on the side of the first chip body close to the second driving chip; the first reserved pads and the second reserved pads are electrically connected;

[0015] The first segment is connected to the first reserved pad by bonding, and the second segment is connected to the second reserved pad by bonding.

[0016] Optionally, in some embodiments of the present application, the first driving chip further includes a plurality of first connection lines. One end of the first connection line is connected to the first reserved pad, and the other end of the first connection line is connected to the second reserved pad;

[0017] The first connection lines are arranged inside the first chip body.

[0018] Optionally, in some embodiments of the present application, the first driving chip further includes a plurality of first connection lines. One end of the first connection line is connected to the first reserved pad, and the other end of the first connection line is connected to the second reserved pad;

[0019] The first connection lines are arranged on the outer side of the first chip body close to the substrate.

[0020] Optionally, in some embodiments of the present application, the first driving chip further includes a second bonding unit. The second bonding unit includes at least one second bonding pad, and one second bonding pad is electrically connected to the first bonding pad; a plurality of the second bonding units are located at the end side of the first chip body away from the second reserved pad;

[0021] The second bonding unit is used to access an input signal.

[0022] Optionally, in some embodiments of the present application, the first driving chip further includes a spare bonding unit. The spare bonding unit is located on the side of the plurality of second reserved pads away from the second bonding unit.

[0023] Optionally, in some embodiments of the present application, the number of the first driving chips includes at least two, and the number of the second driving chips includes at least one;

[0024] One of the second driving chips is bonded and connected to at least two groups of second wiring groups, and one of the second wiring groups corresponds to one of the first driving chips.

[0025] Correspondingly, an embodiment of the present application further provides a display device, including a panel, an adapter board, and a circuit board as described in any one of the above embodiments;

[0026] One end of the circuit board close to the first driving chip is bonded and connected to the panel, and one end of the circuit board close to the second driving chip is bonded and connected to the adapter board.

[0027] Beneficial effects:

[0028] In the circuit board of the embodiment of the present application, the first wiring group and the second wiring group are arranged on the same layer, that is to say, the single-layer wiring is adopted in this embodiment. Compared with the double-layer wiring of the prior art, the cost of the embodiment of the present application is lower, and the bonding with external components is simpler. In addition, in the embodiment of the present application, the first unit of the first wiring group and the second unit of the second wiring group are arranged alternately, so that the wiring length of adjacent first units plus the wiring length of external components is relatively uniform, and the wiring length of adjacent second units plus the wiring length of external components is also relatively uniform, improving the uniformity of impedance between wirings. Description of the drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0030] Figure 1 It is a schematic structural diagram of a circuit board provided by Embodiment 1 of the present application;

[0031] Figure 2 It is a schematic structural diagram of the first driving chip of the circuit board provided by Embodiment 1 of the present application;

[0032] Figure 3 It is a schematic structural diagram of a circuit board provided by Embodiment 2 of the present application;

[0033] Figure 4 It is a schematic structural diagram of the first driving chip of the circuit board provided by Embodiment 2 of the present application;

[0034] Figure 5 It is a schematic structural diagram of the first driving chip of the circuit board provided by Embodiment 3 of the present application;

[0035] Figure 6 It is a schematic structural diagram of a display device provided by Embodiment 4 of the present application. Detailed Embodiments

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0037] The embodiments of the present application provide a circuit board and a display device, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0038] Embodiment 1

[0039] Please refer to Figure 1 and Figure 2 The embodiments of the present application provide a circuit board 100, which includes a substrate 11, a first wiring group 12, a second wiring group 13, a first driving chip 14, and a second driving chip 15.

[0040] The first wiring group 12 is disposed on the substrate 11. The first wiring group 12 includes a plurality of first units 12a. At least one first signal trace 121 is disposed in each first unit 12a.

[0041] The second wiring group 13 is disposed on the same layer as the first wiring group 12. The second wiring group 13 includes a plurality of second units 13a. At least one second signal trace 131 is disposed in each second unit 13a. In the first direction X, the first units 12a and the second units 13a are alternately arranged, and the first direction X intersects with the extending direction of the first signal trace 121.

[0042] The first driving chip 14 is disposed on the substrate 11 and is bound to the first wiring group 12. The second driving chip 15 is disposed on the substrate 11 and is bound to the second wiring group 13.

[0043] In the embodiment of the present application, the first trace group 12 and the second trace group 13 of the circuit board 100 are arranged on the same layer. That is to say, the single-layer trace setting is adopted in this embodiment. Compared with the double-layer trace of the prior art, the cost of the embodiment of the present application is lower, and the binding with external components is simpler. In addition, in the embodiment of the present application, the first unit 12a of the first trace group 12 and the second unit 13a of the second trace group 13 are arranged alternately, so that the trace length of adjacent first units 12a plus the trace length of external components is relatively uniform, and the trace length of adjacent second units 13a plus the trace length of external components is also relatively uniform, improving the uniformity of impedance between traces.

[0044] For example, the external component is a panel, and the pixel positions in the panel are fixed. In order to ensure uniform image quality display, there are requirements for the trace length of the first trace group 12.

[0045] It can be understood that, for example, the first driving chip 14 will supply the 1st - 960th pixels. The circuit board 100 is centered and bound relative to the positions of these 960 pixels. Then the traces for the first and 960th pixels are the longest, and so on. The 480th and 481st traces are the shortest. To ensure left - right symmetry, the first trace group 12 and the second trace group 13 should be arranged alternately.

[0046] That is to say, in the direction of the first trace group 12 from the middle area to the two - side areas, the length of the first signal trace 121 decreases.

[0047] Similarly, in the direction of the second trace group 13 from the middle area to the two - side areas, the length of the second signal trace 131 decreases.

[0048] Optionally, the first driving chip 14 can be one of a gate driving chip or a source driving chip, and the second driving chip 15 is the other of a gate driving chip or a source driving chip.

[0049] Optionally, in this embodiment, the first driving chip 14 is a gate driving chip, and the second driving chip 15 is a source driving chip.

[0050] Optionally, the first unit 12a can include 1, 2, 3 or more first signal traces 121. The second unit 13a can include 1, 2, 3 or more second signal traces 131.

[0051] Wherein, the number of the first signal traces 121 and the second signal traces 131 can be determined according to the actual architecture or resolution of the panel, and no limitation is made here.

[0052] Optionally, the substrate 11 can be a rigid substrate or a flexible substrate. The material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, polyimide or polyurethane.

[0053] Optionally, each of the first signal trace 121 and the second signal trace 131 can be formed by using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), an alloy composed of any of the above metal elements, or an alloy combining any of the above metal elements, etc. In addition, the first signal trace 121 and the second signal trace 131 can have a single-layer structure or a stacked structure of two or more layers.

[0054] In some embodiments, the materials of the first signal trace 121 and the second signal trace 131 can be metal oxides, such as ITO, etc.

[0055] Optionally, please refer to Figure 2 , the first driving chip 14 includes a first chip body 141 and a plurality of first bonding units 142. The first bonding units 142 are arranged on one side of the first chip body 141 close to the first trace group 12. A reserved space 14a is provided between two adjacent first bonding units 142.

[0056] The first bonding unit 142 includes at least one first bonding pad 14a1, and the first bonding pad 14a1 is bonded and connected to the first signal trace 121. A second unit 13a is provided corresponding to a reserved space 14a.

[0057] That is to say, in this embodiment, the second signal trace 131 of the second unit 13a can pass through the reserved space 14a.

[0058] Optionally, the second signal trace 131 extends from the second driving chip 15 towards the external panel, and the second signal trace 131 passes through the reserved space 14a.

[0059] Such a setting enables the first driving chip 14 to be only bonded to the first trace group 12 on one side. This saves the design process of the first driving chip 14 and enables the first driving chip 14 to be made smaller.

[0060] Optionally, the number of the first driving chips 14 includes at least two, and the number of the second driving chips 15 includes at least one.

[0061] Optionally, the first bonding pad 14a1 is bonded and connected to the first signal trace 121 one by one.

[0062] A second driving chip 15 is bonded and connected to at least two groups of second trace groups 13. One second trace group 13 corresponds to one first driving chip 14.

[0063] That is to say, in this embodiment, two first driving chips 14 can be used to drive the same area in the panel. And one second trace group 13 correspondingly passes through the reserved space 14a of one first driving chip 14, making the in-plane display panel more uniform and further saving the manufacturing cost.

[0064] Optionally, one end of the circuit board 100 bonded to the external panel is provided with a first conductive pad 161 and a second conductive pad 162. One first conductive pad 161 is correspondingly connected to one first signal trace 121, and one second conductive pad 162 is correspondingly connected to one second signal trace 131.

[0065] Optionally, the first driving chip 14 further includes a second bonding unit 14b. The second bonding unit 14b includes at least one second bonding pad 14b1. One second bonding pad 14b1 is electrically connected to the first bonding pad 14a1. The second bonding unit 14b is located on the end side of the first chip body 141.

[0066] The second bonding unit 14b is used to access the input signal. It can be understood that the second bonding unit 14b is arranged on the end side of the first chip body 141, so that the trace connecting the second bonding unit 14b can be arranged outside the second driving chip 15, saving the wiring space and also preventing this trace from being too dense with the second signal trace 131, which affects the signal transmission.

[0067] Optionally, the first driving chip 14 further includes a spare bonding unit 14c. The spare bonding unit 14c is located on the other end side of the first chip body.

[0068] When the second bonding unit 14b is used to access the external signal line, the spare bonding unit 14c is vacant.

[0069] When the second bonding unit 14b is vacant or damaged, the spare bonding unit 14c replaces the second bonding unit 14b to access the external signal.

[0070] Therefore, since the second bonding unit 14b and the spare bonding unit 14c are located on the two end sides of the first chip body 141, there is a large space between the second bonding unit 14b and the spare bonding unit 14c to pass through the second signal trace 131.

[0071] Embodiment 2

[0072] Please refer to Figure 3 andFigure 4 , the difference between the second embodiment and the first embodiment is as follows: a second signal trace 131 includes a first segment 1311 and a second segment 1312 which are spaced apart. The first segment 1311 is located on the side of the first driving chip 14 away from the second driving chip 15, and the second segment 1312 is located on the side of the first driving chip 14 close to the second driving chip 15.

[0073] The first driving chip 14 further includes a plurality of first reserved pads 14a2 and a plurality of second reserved pads 14a3. The first reserved pads 14a2 are arranged at the reserved space 14a. The second reserved pads 14a3 are arranged on the side of the first chip body 141 close to the second driving chip 15. The first reserved pads 14a2 and the second reserved pads 14a3 are electrically connected;

[0074] The first segment 1311 is bonded and connected to the first reserved pad 14a2. The second segment 1312 is bonded and connected to the second reserved pad 14a2.

[0075] Optionally, one second signal trace 131 is correspondingly connected to a pair of first reserved pads and second reserved pads.

[0076] Optionally, the first driving chip 14 further includes a plurality of first connection lines 143. One end of the first connection line 143 is connected to the first reserved pad 14a2, and the other end of the first connection line 143 is connected to the second reserved pad 14a3.

[0077] The first connection lines 143 are arranged inside the first chip body 141.

[0078] In this embodiment, by arranging the first connection lines 143 inside the first chip body 141, the influence of the first connection lines 143 on the signals output from the first driving chip 14 to the first signal trace 121 can be reduced.

[0079] In addition, the first driving chip 14 further includes a second bonding unit 14b. The second bonding unit 14b includes at least one second bonding pad 14b1. One second bonding pad 14b1 is electrically connected to the first bonding pad 14a1. The second bonding unit 14b is located at the end side of the first chip body 141 away from the second reserved pad 14a1.

[0080] The second bonding unit 14b is used to access input signals. It can be understood that the second bonding unit 14b is arranged at the end side of the first chip body 141, so that the traces connected to the second bonding unit 14b can be arranged outside the second driving chip 15, saving the wiring space and avoiding the traces being too dense with the second signal trace 131, which affects signal transmission.

[0081] Optionally, the first driving chip 14 further includes a spare bonding unit 14c. The spare bonding unit 14c is located at the other end side of the first chip body.

[0082] When the second bonding unit 14b is used to access an external signal line, the spare bonding unit 14c is vacant.

[0083] When the second bonding unit 14b is vacant or damaged, the spare bonding unit 14c replaces the second bonding unit 14b to access an external signal.

[0084] Therefore, a relatively large space is provided between the second bonding unit 14b and the spare bonding unit 14c of the first driving chip 14 to allow the second signal trace 131 to pass through.

[0085] Embodiment III

[0086] Please refer to Figure 5 , the first driving chip 14 further includes a plurality of first connection lines 143. One end of each first connection line 143 is connected to the first reserved pad 14a2, and the other end of each first connection line 143 is connected to the second reserved pad 14a3.

[0087] The difference between this embodiment and Embodiment II is that: the first connection lines 143 are arranged on the outer side of the first chip body 141 close to the substrate 11.

[0088] That is to say, the first connection lines 143 are arranged on the back surface of the first chip body 141. Such an arrangement can save the design space of the front part of the first chip body 141 compared with Embodiment II.

[0089] Embodiment IV

[0090] Please refer to Figure 6 , correspondingly, an embodiment of the present application further provides a display device 1000, including a panel 200, an adapter board 300, and a circuit board 100 as described in any one of the above embodiments.

[0091] One end of the circuit board 100 close to the first driving chip 14 is bonded to the panel 200. One end of the circuit board 100 close to the second driving chip 15 is bonded to the adapter board 300.

[0092] It should be noted that the structure of the circuit board 100 in this embodiment is similar to or the same as the structure of the circuit board 100 in the above embodiments. For details, please refer to the description of the above embodiments.

[0093] It can be understood that since both ends of the circuit board 100 need to be bonded, a first conductive pad 161 and a second conductive pad 162 are provided at the end of the circuit board 100 bonded to the panel 200. One first conductive pad 161 is correspondingly connected to one first signal trace 121, and one second conductive pad 162 is correspondingly connected to one second signal trace 131.

[0094] One end of the circuit board 100 bound to the adapter board 300 is provided with a third conductive pad and a fourth conductive pad (not shown in the figure). The third conductive pad is dot-connected to the second binding pad, and the fourth conductive pad is electrically connected to the signal input end of the second driving chip.

[0095] Optionally, the panel 200 is divided into 4 regions. Every 6 circuit boards 100 form a group. Each scanning line is controlled by 4 first driving chips 14, improving the scanning signal quality and the charging rate.

[0096] It can be understood that in this embodiment, each scanning line is not only controlled by 4 first driving chips 14, but can also be controlled by 2 or more first driving chips 14.

[0097] In the display device 1000 according to the embodiment of the present application, the first wiring group 12 and the second wiring group 13 of the circuit board 100 are arranged on the same layer. That is to say, a single-layer wiring arrangement is adopted in this embodiment. Compared with the double-layer wiring in the prior art, the cost of the embodiment of the present application is lower, and the binding to the panel 200 and the adapter board 300 is simpler. In addition, in the embodiment of the present application, the first unit 12a of the first wiring group 12 and the second unit 13a of the second wiring group 13 are arranged alternately, so that the wiring length of adjacent first units 12a plus the wiring length of the panel 200 is relatively uniform, and the wiring length of adjacent second units 13a plus the wiring length of the panel 200 is also relatively uniform, improving the uniformity of the impedance between the wirings, and further improving the display effect of the panel.

[0098] Optionally, two adapter boards 300 are connected by a first flexible circuit board 410 to form a circuit group.

[0099] Optionally, the display device 1000 further includes a control board 500. The control board 500 is connected to each circuit group through a second flexible circuit board 420. The control board 500 is used for power supply and providing control signals.

[0100] The above has introduced in detail a circuit board and a display device provided by the embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A circuit board, comprising a bonding area configured to bond an external panel, characterized in that, Comprising: A substrate, A first trace group, the first trace group being disposed on the substrate, the first trace group including a plurality of first units, and at least one first signal trace being disposed in each first unit; A second trace group, the second trace group being disposed on the same layer as the first trace group, the second trace group including a plurality of second units, and at least one second signal trace being disposed in each second unit; within a first driving chip region, in a first direction, the first units and the second units are alternately arranged, and the first direction intersects with the extending direction of the first signal trace; A first driving chip, which is a gate driving chip, the number of the first driving chips including at least two, the first driving chips being disposed on the substrate, the first driving chip including a first chip body and a plurality of first bonding units, the first bonding units being disposed on a side of the first chip body close to the first trace group, the first bonding unit including at least one first bonding pad, and the first bonding pad being bonded and connected to the first signal trace; in the circuit board in a top-down view, the first driving chips are disposed in the extending direction of each second trace group, and A second driving chip, which is a source driving chip and is located on a side of the first driving chip away from the bonding region, the second driving chip being disposed on the substrate and being bonded and connected to the second trace group; A reserved space is provided between two adjacent first bonding units; one second unit is disposed corresponding to one reserved space; One second signal trace includes a first segment and a second segment which are spaced apart, the first segment being located on a side of the first driving chip away from the second driving chip, and the second segment being located on a side of the first driving chip close to the second driving chip; The first driving chip further includes a plurality of first reserved pads and a plurality of second reserved pads, the first reserved pads being disposed at the reserved space, and the second reserved pads being disposed on a side of the first chip body close to the second driving chip; the first reserved pads and the second reserved pads are electrically connected; The first segment is bonded and connected to the first reserved pad, and the second segment is bonded and connected to the second reserved pad.

2. The circuit board according to claim 1, wherein The first driving chip further includes a plurality of first connection lines, one end of each first connection line being connected to the first reserved pad, and the other end of each first connection line being connected to the second reserved pad; The first connection lines are disposed within the first chip body.

3. The circuit board according to claim 1, characterized in that, The first driving chip further includes a plurality of first connection lines, one end of each first connection line being connected to the first reserved pad, and the other end of each first connection line being connected to the second reserved pad; The first connection lines are disposed on an outer side of the first chip body close to the substrate.

4. The circuit board according to any one of claims 1 to 3, characterized in that The first driving chip further includes a second bonding unit, the second bonding unit including at least one second bonding pad, and one second bonding pad being electrically connected to the first bonding pad; a plurality of the second bonding units are located at an end side of the first chip body; The second bonding unit is used for accessing an input signal.

5. The circuit board according to claim 4, wherein The first driving chip further includes a spare bonding unit, and the spare bonding unit is located on the other end side of the first chip body.

6. The circuit board according to claim 1, wherein, The number of the second driving chips includes at least one; One of the second driving chips is bonded and connected to at least two groups of second wiring groups, and one second wiring group corresponds to one first driving chip.

7. A display device, characterized in that, It includes a panel, an adapter board, and a circuit board according to any one of claims 1-6; One end of the circuit board close to the first driving chip is bonded and connected to the panel, and one end of the circuit board close to the second driving chip is bonded and connected to the adapter board.

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