Ceramic spacer with optimization circuit and method of manufacturing the same

Abstract

The application discloses a ceramic cushion block with an optimization circuit, which comprises a ceramic cushion block, an optical chip arranged on the ceramic cushion block, a thin-film resistor and a thin-film inductor respectively arranged on the ceramic cushion block, and a flat-plate capacitor embedded on the ceramic cushion block; and the thin-film resistor, the thin-film inductor and the flat-plate capacitor are connected with the optical chip to form an optimization circuit. The application integrates resistors, capacitors and inductors on the ceramic cushion block, reduces the mounting of internal components of the optical device, and has the beneficial effects of improving production efficiency, improving integration level and improving product reliability.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and more specifically, to a ceramic pad with optimized circuitry and its preparation method. Background Technology

[0002] In the packaging process of high-speed optical devices, electronic components such as capacitors and resistors are used to optimize high-speed modulated electrical signals.

[0003] Existing solutions involve mounting resistors, capacitors, inductors, and other components onto ceramic pads inside the optical device and connecting them via gold wire bonding. This mounting process occupies internal space, requires multiple placement and wire bonding operations, and is complex and time-consuming during baking. The main drawbacks and shortcomings of existing technologies are as follows:

[0004] 1. Existing solutions for internally mounted capacitors and resistors are complex in process and have low production efficiency;

[0005] 2. When components are bonded with other curing adhesives, their reliability is affected by factors such as the process and the performance of the adhesive.

[0006] 3. After mounting resistors and capacitors, gold wire bonding is required to connect them, resulting in a large number of wires inside the components with complex shapes, which can easily cause mutual interference and attenuation of high-speed signals.

[0007] 4. Existing components such as resistors, capacitors, and inductors occupy a certain space on the ceramic pad, which compresses the internal space of the optical device and makes it difficult to arrange them.

[0008] Therefore, how to improve the integration of components and reduce the mounting of internal components in optical devices is a problem to be solved in this technical field. Summary of the Invention

[0009] One object of the present invention is to solve at least the above-mentioned problems and / or defects, and to provide at least the advantages described below.

[0010] To achieve these objectives and other advantages of the present invention, a ceramic pad with optimized circuitry is provided, comprising a ceramic pad and an optical chip disposed on said ceramic pad;

[0011] The ceramic pad is coated with a thin-film resistor and a thin-film inductor, respectively.

[0012] A planar capacitor is also embedded in the ceramic pad;

[0013] Furthermore, the thin-film resistor, thin-film inductor, and planar capacitor are connected to the optical chip to form an optimized circuit.

[0014] Preferably, the method by which the planar capacitor is embedded in the ceramic pad is as follows:

[0015] The ceramic pad is embedded with a first parallel plate electrode and a second parallel plate electrode, and the first parallel plate electrode and the second parallel plate electrode are arranged in parallel. The ceramic pad is also coated with an input gold layer, and the input gold layer abuts against the first parallel plate electrode. The ceramic pad is also coated with a ground gold layer, and the ground gold layer abuts against the second parallel plate electrode.

[0016] Preferably, the coating material of the thin-film resistor is nickel-chromium.

[0017] Preferably, the thin-film inductor is configured as a rectangular coil-shaped thin-film inductor.

[0018] Preferably, the coating method of the thin film resistor is any one of spraying, printing, and laser lithography, and the coating method of the thin film inductor is any one of spraying, printing, and laser lithography.

[0019] Preferably, the connection method of the optimized circuit is as follows:

[0020] One end of the thin-film resistor is grounded, and the other end of the thin-film resistor is connected to the modulator output terminal of the optical chip; one end of the thin-film inductor is connected to the power supply, and the other end of the thin-film inductor is connected to the laser emitter input terminal of the optical chip; one end of the parallel plate capacitor is connected to one end of the thin-film inductor, and the other end of the parallel plate capacitor is grounded.

[0021] A method for preparing a ceramic pad with optimized circuitry, characterized by comprising the following steps:

[0022] Step 1: Select the ceramic pad material, set the area and spacing of the first parallel plate electrode and the second parallel plate electrode, and calculate and determine the capacitance of the parallel plate capacitor. Then, embed the first parallel plate electrode and the second parallel plate electrode into the ceramic pad in parallel according to the spacing, and coat the input end gold layer along the first parallel plate electrode and the ground gold layer along the second parallel plate electrode.

[0023] Step 2: Set the resistance value, select the thin film resistor coating material, set the thin film resistor coating thickness and width, calculate the length of the thin film resistor, and coat the thin film resistor on the ceramic pad;

[0024] Step 3: Set the diameter of the rectangular coil, the width of the helix, and the spacing between the outer edges, and calculate and determine the inductance. Then, coat the rectangular coil-shaped thin film inductor onto the ceramic pad.

[0025] Step 4: Fix the optical chip on the ceramic pad, and connect the input gold layer, ground gold layer, thin film resistor, and thin film inductor to the optical chip through gold wires.

[0026] Preferably, the formula for calculating and determining the capacitance of the parallel plate capacitor is:

[0027]

[0028] Where C is the capacitance value in F; L is the effective length of the dielectric in m; W is the effective width of the dielectric in m; K is the equivalent dielectric constant in F / m; and d is the dielectric thickness in m.

[0029] Preferably, the formula for calculating the thin film resistance length is:

[0030]

[0031] Where R is resistance, in Ω; ρ is resistivity of the conductor, in Ω·m; L is length of the conductor, in m; and S is cross-sectional area of ​​the conductor, in m². 2 .

[0032] Preferably, the formula for calculating and determining the inductance is:

[0033] Inductance L = 85 * 10 -10 *D*N 5 / 3 =27*10 -10 *(D 8 / 3 / p 5 / 3 )*(1+1 / r) 5 / 3

[0034] Where r = p / q

[0035] Number of revolutions N = (D / 2) / (q+p) = D / (2p*(1+1 / r))

[0036] r is the ratio of the helix width to the helix spacing; q is the distance between the outer edges; p is the helix width; D is the coil diameter.

[0037] The present invention has at least the following beneficial effects:

[0038] Firstly, this invention integrates components such as resistors, capacitors, and inductors on a ceramic pad, reducing the need for mounting internal components in optical devices. This has the beneficial effects of improving production efficiency, increasing integration, and enhancing product reliability.

[0039] Secondly, this invention reduces the number of pads inside high-speed optical devices, improving the space utilization rate inside the optical devices; it reduces the internal processes of high-speed optical devices, improving production efficiency; it simplifies the internal structure of high-speed optical devices, improving product reliability; and through integrated design, it can optimize the distance between pads, reduce the length of gold wires or optimize the curvature of gold wires, and optimize high-speed signal parameters.

[0040] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of the present invention.

[0042] Figure 2 This is a schematic diagram of the parallel plate capacitor structure of the present invention.

[0043] Figure 3 This is a schematic diagram of the thin-film resistor structure of the present invention.

[0044] Figure 4 This is a schematic diagram of the thin-film inductor structure of the present invention.

[0045] Figure 5 This is a schematic diagram of the optimized circuit of the present invention.

[0046] Figure 6 This is a schematic diagram showing the parameter values ​​of the rectangular coil-shaped thin-film inductor of the present invention. Detailed Implementation

[0047] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description.

[0048] It should be understood that terms such as “having,” “comprising,” and “including” as used herein do not exclude the presence or addition of one or more other elements or combinations thereof.

[0049] It should be noted that in the description of this invention, the orientations or positional relationships indicated by terms are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0051] Furthermore, in this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Moreover, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0052] Figure 1 An embodiment of the present invention is shown, which includes a ceramic pad 1 and an optical chip 2 disposed on the ceramic pad 1.

[0053] The ceramic pad 1 is coated with a thin film resistor 3 and a thin film inductor 4 respectively;

[0054] A flat plate capacitor 5 is also embedded in the ceramic pad 1;

[0055] Furthermore, the thin-film resistor 3, the thin-film inductor 4, and the planar capacitor 5 are connected to the optical chip 2 to form an optimized circuit.

[0056] Working Principle: By embedding a parallel plate capacitor 5 on the ceramic pad 1, a stable connection between the parallel plate capacitor 5 and the ceramic pad 1 is ensured, while significantly reducing the space occupied by the parallel plate capacitor 5 on the ceramic pad 1. Similarly, by coating a thin-film resistor 3 on the ceramic pad 1, a stable connection between the thin-film resistor 3 and the ceramic pad 1 is ensured, while significantly reducing the space occupied by the thin-film resistor 3 on the ceramic pad 1. Likewise, by coating a thin-film inductor 4 on the ceramic pad 1, a stable connection between the thin-film inductor 4 and the ceramic pad 1 is ensured, while significantly reducing the space occupied by the thin-film inductor 4 on the ceramic pad 1. The optimized circuit formed by connecting the thin-film resistor 3, thin-film inductor 4, and parallel plate capacitor 5 to the optical chip 2 optimizes the high-speed modulation signal. In this technical solution, integrating the thin-film resistor 3, parallel plate capacitor 5, and thin-film inductor 4 on the ceramic pad 1 reduces the mounting of internal components of the optical device, resulting in improved production efficiency, increased integration, and enhanced product reliability.

[0057] In the above scheme, the method of embedding the planar capacitor 5 on the ceramic pad 1 is as follows:

[0058] The ceramic pad 1 is embedded with a first parallel plate electrode 51 and a second parallel plate electrode 52, and the first parallel plate electrode 51 and the second parallel plate electrode 52 are arranged in parallel. The ceramic pad 1 is also coated with an input gold layer 53, and the input gold layer 53 abuts against the first parallel plate electrode 51. The ceramic pad 1 is also coated with a ground gold layer 54, and the ground gold layer 54 abuts against the second parallel plate electrode 52.

[0059] Working principle: Utilizing the insulation of the ceramic pad 1 itself, a first parallel plate electrode 51 and a second parallel plate electrode 52 are embedded in the ceramic pad 1 to form a parallel plate capacitor 5. The input terminal of the parallel plate capacitor 5 is formed by the gold layer 53 abutting against the first parallel plate electrode 51, and the ground terminal of the parallel plate capacitor 5 is formed by the gold layer 54 abutting against the second parallel plate electrode 52. This facilitates the connection between the two ends of the parallel plate capacitor 5. Furthermore, when it is necessary to integrate parallel plate capacitors 5 with different capacitance values, the areas of the first parallel plate electrode 51 and the second parallel plate electrode 52, the spacing between the first parallel plate electrode 51 and the second parallel plate electrode 52, and the dielectric between the plates can be adjusted. This has the advantages of improving integration and product reliability.

[0060] As described above, the coating material for the thin-film resistor 3 is nickel-chromium. Commonly used thin-film resistor materials are divided into three types: nickel-chromium, chromium-silicon, and chromium-silicon monoxide. Nickel-chromium is a low-resistance material, while chromium-silicon and chromium-silicon monoxide are high-resistance materials. Therefore, selecting nickel-chromium as the thin-film resistor based on the resistance requirements of the optimized circuit has the advantage of ensuring the optimization effect and improving product reliability.

[0061] In the above scheme, the thin-film inductor 4 is configured as a rectangular coil-shaped thin-film inductor. By configuring the thin-film inductor 4 as a rectangular coil-shaped thin-film inductor, an equivalent inductor coil structure is achieved, which also facilitates the calculation of inductance and has the advantages of improving integration and facilitating manufacturing.

[0062] As described above, the coating method for the thin-film resistor 3 can be any one of spraying, printing, or laser lithography, and the coating method for the thin-film inductor 4 can be any one of spraying, printing, or laser lithography. By setting the coating methods for the thin-film resistor 3 and the thin-film inductor 4 to any one of spraying, printing, or laser lithography, the forming effect of the thin-film resistor 3 and the thin-film inductor 4 is ensured, thereby ensuring the optimized performance of the optical chip 2.

[0063] In the above scheme, the connection method of the optimized circuit is as follows:

[0064] One end of the thin-film resistor 3 is grounded, and the other end is connected to the modulator output of the optical chip 2. One end of the thin-film inductor 4 is connected to the power supply, and the other end is connected to the laser emitter input of the optical chip 2. One end of the parallel plate capacitor 5 is connected to one end of the thin-film inductor 4, and the other end is grounded. The high-speed modulated electrical signal flowing through the optical chip 2 is optimized using the thin-film inductor 4, thin-film resistor 3, and parallel plate capacitor 5; this is only one implementation. The number of thin-film inductors 4, thin-film resistors 3, and parallel plate capacitors 5 can be adjusted according to actual usage requirements. The connection method between the thin-film inductors 4, thin-film resistors 3, parallel plate capacitors 5 and the optical chip 2 can also be adjusted according to actual usage requirements. This approach has the advantages of ensuring optimization effects and improving product reliability.

[0065] Example:

[0066] Step 1: Select aluminum nitride as the material for ceramic pad 1, with an equivalent dielectric constant of 1×10⁻⁶. -11 (F / m), the dimensions of the first parallel plate electrode 51 and the second parallel plate electrode 52 are set to 1mm*0.2mm, and the distance between the first parallel plate electrode 51 and the second parallel plate electrode 52 is 0.02mm. Then the capacitance of the plate capacitor 5 is calculated and determined.

[0067] The formula for calculating the parallel plate capacitor 5 is:

[0068]

[0069] Where C is the capacitance value, in F;

[0070] L is the effective length of the medium, in meters;

[0071] W represents the effective width of the medium, in meters (m).

[0072] K is the equivalent dielectric constant, in F / m;

[0073] d represents the thickness of the medium, in meters (m).

[0074] The ceramic pad 1 is made of aluminum nitride, and its equivalent dielectric constant is 1×10⁻⁶. -11 (F / m), the dimensions of the first parallel plate electrode 51 and the second parallel plate electrode 52 are both 1mm*0.2mm, and the distance between the first parallel plate electrode 51 and the second parallel plate electrode 52 is 0.02mm. According to the capacitance formula 2, C = 1×10 -13(F); The first parallel plate electrode 51 and the second parallel plate electrode 52 are then embedded into the ceramic pad 1 in parallel with the spacing, and the input gold layer 53 is coated along the first parallel plate electrode 51, and the ground gold layer 54 is coated along the second parallel plate electrode 51; When integrating parallel plate capacitors 5 with different capacitance values, it is only necessary to adjust the area, spacing parameters and inter-plate dielectric of the first parallel plate electrode 51 and the second parallel plate electrode 52.

[0075] Step 2: Set the resistance value to 590Ω, select nickel-chromium alloy Cr30Ni70 as the coating material for thin film resistor 3, and set the coating thickness of thin film resistor 3 to 1μm and the width to 1mm.

[0076] The formula for calculating resistance is:

[0077]

[0078] in:

[0079] R is resistance, and the unit is Ω;

[0080] ρ is the resistivity of the conductor, with units of Ω·m;

[0081] L is the length of the conductor, in meters (m).

[0082] S is the cross-sectional area of ​​the conductor, measured in meters (m²). 2 ;

[0083] The resistivity of the nickel-chromium alloy Cr30Ni70 is ρ = 1.18 × 10⁻⁶. -6 Ω·m, which can be obtained from the formula for thin film resistance 3. Calculations show that the length of the thin film resistor 3 is L = 0.5 mm. Then, a thin film resistor 3 with a length of 0.5 mm, a width of 1 mm, and a thickness of 1 μm is coated on the ceramic pad 1 by any of the following methods: spraying, printing, or laser lithography.

[0084] Step 3: Set the diameter of rectangular coil 4 to 1mm, the spiral width to 0.1mm, and the spacing between the outer edges to 0.1mm;

[0085] The formula for calculating thin-film inductance is:

[0086] r = p / q

[0087] Thin film inductor 4 area S = D 2

[0088] Number of revolutions N = (D / 2) / (q+p) = D / (2p*(1+1 / r))

[0089] Helix length Li = 4(d / 2)N = D 2 / (p*(1+1 / r))

[0090] Inductance L = 85 * 10 -10 *D*N 5 / 3 =27*10 -10 *(D 8 / 3 / p 5 / 3 )*(1+1 / r) 5 / 3

[0091] in:

[0092] r is the ratio of the helix width to the helix spacing;

[0093] q is the distance between the outer edges;

[0094] p is the width of the helix;

[0095] D is the diameter of the coil (approximately the side length of the outermost coil of a rectangular coil);

[0096] Substituting D = 1 mm, p = 0.1 mm, and q = 0.1 mm into the inductance calculation formula, we can calculate: L = 4 × 10 -10 (H)

[0097] Subsequently, a rectangular coil-shaped thin-film inductor 4 with a diameter of 1 mm, a spiral width of 0.1 mm, and an outer edge spacing of 0.1 mm is coated on the ceramic pad 1;

[0098] Step 4: Fix the optical chip 2 on the ceramic pad 1, and connect the input gold layer 53, the ground gold layer 54, the thin film resistor 3, and the thin film inductor 4 to the optical chip 2 through the gold wire 6.

[0099] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A ceramic pad with optimized circuitry, comprising a ceramic pad and an optical chip disposed on the ceramic pad, characterized in that: The ceramic pad is coated with a thin-film resistor and a thin-film inductor, respectively. A planar capacitor is also embedded in the ceramic pad; Furthermore, the thin-film resistor, thin-film inductor, and parallel-plate capacitor are connected to the optical chip to form an optimized circuit; The thin-film inductor is configured as a rectangular coil-shaped thin-film inductor; The optimized circuit connection method is as follows: One end of the thin-film resistor is grounded, and the other end of the thin-film resistor is connected to the modulator output terminal of the optical chip; one end of the thin-film inductor is connected to the power supply, and the other end of the thin-film inductor is connected to the laser emitter input terminal of the optical chip; one end of the parallel plate capacitor is connected to one end of the thin-film inductor, and the other end of the parallel plate capacitor is grounded. The method for preparing the ceramic pad with optimized circuitry includes the following steps: Step 1: Select the ceramic pad material, set the area and spacing of the first parallel plate electrode and the second parallel plate electrode, and calculate and determine the capacitance of the parallel plate capacitor. Then, embed the first parallel plate electrode and the second parallel plate electrode into the ceramic pad in parallel according to the spacing, and coat the input end gold layer along the first parallel plate electrode and the ground gold layer along the second parallel plate electrode. Step 2: Set the resistance value, select the thin film resistor coating material, set the thin film resistor coating thickness and width, calculate the length of the thin film resistor, and coat the thin film resistor on the ceramic pad; Step 3: Set the diameter of the rectangular coil, the width of the helix, and the spacing between the outer edges, and calculate and determine the inductance. Then, coat the rectangular coil-shaped thin film inductor onto the ceramic pad. Step 4: Fix the optical chip on the ceramic pad, and connect the input gold layer, ground gold layer, thin film resistor, and thin film inductor to the optical chip through gold wires respectively; The formula for calculating and determining the inductance is: Inductance L=85*10 -10 *D*N 5 / 3 =27*10 -10 *(D) 8 / 3 / p 5 / 3 )*(1+1 / r) 5 / 3 Where r = p / q Number of laps N = (D / 2) / (q+p) = D / (2p*(1+1 / r)) r is the ratio of the helix width to the helix spacing; q is the distance between the outer edges; p is the helix width; D is the coil diameter.

2. A ceramic pad with optimized circuitry according to claim 1, characterized in that, The method for embedding the planar capacitor on the ceramic pad is as follows: The ceramic pad is embedded with a first parallel plate electrode and a second parallel plate electrode, and the first parallel plate electrode and the second parallel plate electrode are arranged in parallel. The ceramic pad is also coated with an input gold layer, and the input gold layer abuts against the first parallel plate electrode. The ceramic pad is also coated with a ground gold layer, and the ground gold layer abuts against the second parallel plate electrode.

3. A ceramic pad with optimized circuitry according to claim 1, characterized in that, The coating material for the thin-film resistor is nickel-chromium.

4. A ceramic pad with optimized circuitry according to claim 1, characterized in that, The coating method for the thin-film resistor can be either spraying or printing, and the coating method for the thin-film inductor can be either spraying or printing.

5. A ceramic pad with optimized circuitry according to claim 1, characterized in that, The formula for calculating and determining the capacitance of a parallel plate capacitor is: Where C is the capacitance value in F; L is the effective length of the dielectric in m; W is the effective width of the dielectric in m; K is the equivalent dielectric constant in F / m; and d is the dielectric thickness in m.

6. A ceramic pad with optimized circuitry according to claim 1, characterized in that, The formula for calculating the thin film resistance length is as follows: Where R is resistance, in Ω; ρ is resistivity of the conductor, in Ω·m; L is length of the conductor, in m; and S is cross-sectional area of ​​the conductor, in m². 2 .

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