Current Limiting Circuit for LDO Circuit Applicable to Wide Input Voltage Range
The LDO circuit addresses high static power consumption and reliability issues by employing a hybrid transistor design with high-voltage components, achieving reduced dropout region current and area efficiency across varying input voltages.
Patent Information
- Application Number
- CN202211719447.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-30
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2042-12-30
AI Technical Summary
The current in the existing LDO circuit is too high in the voltage drop zone, especially in the no-load state, resulting in large static power consumption, and the existing current limiting circuit has low reliability and large area in high voltage environments and high cost.
The current limiting circuit design is adopted that combines high-voltage tubes and low-voltage tubes. Through the coordination of high-voltage isolation circuits and Zener diodes, the reliability limit of current is achieved and the chip area is reduced in the high-voltage zone.
It effectively reduces the current in the LDO voltage drop zone, avoids spikes, and ensures the reliability of the circuit in the high voltage zone and reduces the chip area.
Smart Images
Figure CN115903985B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and more specifically, relates to a current limiting circuit applicable to an LDO circuit with a wide input voltage range. Background Art
[0002] When the LDO operates in the dropout region, the current in the second stage of the operational amplifier (the branch where the driving transistor is located) is very large, which causes the current in the dropout region of the LDO to be larger than that in the stable output state. Especially in the no-load state, this current is particularly prominent. And some portable products and long-term standby products have very strict requirements for static power consumption. The problem of relatively large static power consumption in the dropout region of the LDO has an inignorable impact on the circuit. Therefore, it is necessary to design a circuit to limit the current in this branch. At the same time, considering the applications of LDO in fields such as automotive electronics, medical equipment, industrial electronics, and communication base stations, this current limiting circuit must be able to work in a high-voltage environment.
[0003] Most of the existing technologies use the method of current mirroring to achieve current limiting in the dropout region, but its current limiting value is a fixed value. Although the current in the dropout region is limited, there are still spikes. At the same time, designed with a low-voltage process, the circuit has a risk of being broken down and has low reliability. While using high-voltage-resistant devices for design, the general performance of high-voltage-resistant devices is not as good as that of low-voltage devices, and they often require a larger area. Therefore, it is necessary to be able to reduce the area of the LDO well, save costs, and give play to the advantages of the process on the premise of meeting reliability by only partially using high-voltage transistors in the current limiting circuit. Summary of the Invention
[0004] In order to solve the problems existing in the prior art, the present invention provides a current limiting circuit applicable to an LDO circuit with a wide input voltage range, which can effectively reduce the current in the dropout region of the LDO, can work in the high-voltage region, and reduces the chip area on the premise of ensuring reliability by using a combination of high-voltage transistors and low-voltage transistors.
[0005] In order to solve at least one of the above technical problems, according to one aspect of the present invention, there is provided a current limiting circuit applicable to an LDO circuit with a wide input voltage range, including: an LDO feedback control loop with a wide input voltage range and a high-voltage-resistant current limiting circuit.
[0006] The LDO feedback control loop with a wide input voltage range includes an error amplifier, a driving transistor N1, a high-low voltage isolation transistor HN1, a current sampling transistor HP1, a power transistor of the LDO, and feedback resistors R1 and R2.
[0007] The non-inverting input terminal of the error amplifier is connected to the reference voltage VREF. One end of the feedback resistors R1 and R2 is connected to the inverting input terminal of the error amplifier. The output terminal of the error amplifier is connected to the gate of the driving transistor. The drain of the driving transistor is connected to the source of the high-voltage isolation transistor. The drain of the high-voltage isolation transistor is connected to the gate, drain, and the gate of the LDO power transistor of the current sampling transistor. The drain of the LDO power transistor is connected to the other end of the feedback resistor R2. The other end of the feedback resistor R1 is connected to the ground terminal.
[0008] The high-voltage resistant current limiting circuit includes a sampling resistor R3, a current comparator, a bias circuit, a high-voltage isolation circuit, and a current limiting transistor N2. The bias circuit provides bias for the high-voltage isolation circuit and the current comparator. The high-voltage isolation circuit enables the current comparator to operate in a high-voltage environment.
[0009] Further, the current comparator includes comparator transistors HP2, HP3, bias transistor N5, and bias transistor N6. The gate of the comparator transistor HP2 is connected to its drain. The gates of the bias transistors N5 and N6 are connected, and their sources are respectively grounded.
[0010] Further, the high-voltage isolation circuit includes Zener diodes Z1, Z2, high-voltage isolation transistors HP4, HN3, HN4, HN2, and bias transistor N4. The positive electrode of the Zener diode Z1, the drain of the high-voltage isolation transistor HN2, and the gate of the high-voltage isolation transistor HP4 are connected. The source of the high-voltage isolation transistor HN2 is connected to the drain of N4. The drain of the high-voltage isolation transistor HP4 is connected to the positive electrode of the Zener diode Z2. The source of the bias transistor N4 is grounded.
[0011] Further, the bias circuit includes a current source IB and a bias transistor N3. The gate, drain, and the current source IB of the bias transistor N3 are connected, and the source of the bias transistor N3 is grounded.
[0012] One end of the sampling resistor R3 is connected to the source of the comparator transistor HP3 as the sampling signal. The source and drain of the high-voltage isolation transistor HP4 are respectively connected to the gate of the comparator transistor HP2 and the gate of the comparator transistor HP3. The drain and source of the high-voltage isolation transistor HN3 are respectively connected to the drain of the comparator transistor HP2 and the drain of N5. The drain and source of the high-voltage isolation transistor HN4 are respectively connected to the drain of the comparator transistor HP3 and the drain of N6. The gate of the current limiting transistor N2 is connected to the drain of N6. The gate of the bias transistor N3 is connected to the gates of N4, N5, and N6.
[0013] The source of HP3 in the high-voltage-resistant current-limiting circuit is connected to the source of HP1 in the LDO feedback control loop with a wide input voltage range. The drain of N2 in the high-voltage-resistant current-limiting circuit is connected to the source of N1 in the LDO feedback control loop with a wide input voltage range. The source of HP2 in the high-voltage-resistant current-limiting circuit is connected to the output VOUT in the LDO feedback control loop with a wide input voltage range; the input VIN is connected to the negative electrode of the Zener diode Z1, the negative electrode of the Zener diode Z2, the other end of the sampling resistor R3, and the source of the LDO power transistor to connect the input voltage VIN; the current source IB, the gates of the high-low voltage isolation transistors HN2, HN3, HN4, HN1, and the power supply voltage of the error amplifier are connected to the divided voltage VDD of VIN; the divided voltage VDD is a low-voltage input signal.
[0014] Further, when the circuit operates in the low-voltage region, the Zener diode is not broken down, the high-low voltage isolation transistor HP4 is turned on, and the gate voltages of the comparator transistors HP2 and HP3 are equal.
[0015] Further, when the circuit operates in the high-voltage region, the Zener diode is broken down, the high-low voltage isolation transistor HP4 is turned off, the gate-source voltage of the comparator transistor HP3 is clamped within the breakdown voltage of the Zener diode, and HP4 plays a role in high-low voltage isolation.
[0016] Preferably, the current sampling transistor HP1, the power transistor of the LDO, the comparator transistors HP2, HP3, and the high-low voltage isolation transistor HP4 are made of P-type high-voltage-resistant LDMOS transistors; the high-low voltage isolation transistors HN1, HN2, HN3, HN4 are made of N-type high-voltage-resistant LDMOS transistors; the driver transistors N1, N2, and the bias transistors N3, N4, N5, N6 are made of NMOS transistors.
[0017] Compared with the prior art, the present invention has at least the following beneficial effects:
[0018] The current-limiting circuit of the present invention effectively reduces the current in the LDO voltage drop region, obtaining a voltage drop region current without spikes and smaller than that in the stable output; the present invention uses a method of jointly using high-voltage transistors and low-voltage transistors to enable the circuit to operate in the high-voltage region, reducing the chip area on the premise of ensuring reliability. Further, the Zener diodes Z1 and Z2 enable the circuit to be unaffected by high-voltage devices in the low-voltage region and can operate normally in the high-voltage region. The high-low voltage isolation transistors HN1, HN2, HN3, HN4, and HP4 play a pressure-bearing role, ensuring the reliability of the circuit. Description of the Drawings
[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present invention and do not limit the present invention.
[0020] Figure 1 It is the structural block diagram of the circuit of the present invention;
[0021] Figure 2 It is the circuit diagram of the current limiting circuit of the LDO circuit applicable to a wide input voltage range in Embodiment 1 of the present invention;
[0022] Figure 3 It is the simulation comparison diagram before and after current limiting of the present invention. Detailed implementation manners
[0023] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.
[0024] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention belongs.
[0025] Embodiment 1:
[0026] A current limiting circuit applicable to an LDO circuit with a wide input voltage range, as Figure 1 shown, includes an LDO feedback control loop with a wide input voltage range and a high-voltage-resistant current limiting circuit. The high-voltage-resistant current limiting circuit includes a sampling resistor, a current limiting tube, a high-low voltage isolation circuit, a current comparison circuit, and a bias circuit; the LDO feedback control loop with a wide input voltage range accesses a low-voltage signal VDD, an input VIN, and a control signal of the current limiting tube, and is connected to the sampling resistor to output a VOUT signal; the sampling resistor accesses the input VIN and outputs a sampling signal to the current comparison module; the current limiting tube limits the current signal and outputs a control signal; the high-low voltage isolation circuit accesses the low-voltage signal VDD, the input VIN, and a bias signal to provide protection for current comparison; the current comparison module inputs the bias signal, VOUT, and the sampling signal and outputs a current limiting signal.
[0027] Refer to Figure 2As shown, the high-voltage resistant current-limiting circuit is within the dashed box, and the LDO feedback control loop with a wide input voltage range is within the dash-dotted box. According to the design specifications and application scenarios of the low dropout regulator (LDO), the LDO feedback control loop adopts a high-voltage resistant design. The LDO feedback control loop with a wide input voltage range includes an error amplifier, a driving transistor N1, a high-low voltage isolation transistor HN1, a current sampling transistor HP1, the power transistor of the LDO, and feedback resistors R1 and R2. The non-inverting input terminal of the error amplifier is connected to the reference voltage VREF, the inverting input terminal of the error amplifier is connected to one end of the feedback resistors R1 and R2, the output terminal of the error amplifier is connected to the gate of the driving transistor, the drain of the driving transistor is connected to the source of the high-low voltage isolation transistor, the drain of the high-low voltage isolation transistor is connected to the gate, drain of the current sampling transistor, and the gate of the LDO power transistor, the drain of the LDO power transistor is connected to the other end of the feedback resistor R2, and the other end of the feedback resistor R1 is connected to the ground terminal.
[0028] The current comparator includes a comparison transistor HP2, a comparison transistor HP3, a bias transistor N5, and a bias transistor N6. The gate of the comparison transistor HP2 is connected to its drain, and the gates of the bias transistors N5 and N6 are connected, and their sources are respectively grounded. The bias transistors provide bias for the comparator, and the comparison transistors compare the magnitudes of VIN and VOUT and output a current-limiting signal to the gate of the current-limiting transistor N2.
[0029] The high-low voltage isolation circuit includes a Zener diode Z1, a Zener diode Z2, a high-low voltage isolation transistor HP4, a high-low voltage isolation transistor HN3, a high-low voltage isolation transistor HN4, a high-low voltage isolation transistor HN2, and a bias transistor N4. The positive electrode of the Zener diode Z1, the drain of the high-low voltage isolation transistor HN2, and the gate of the high-low voltage isolation transistor HP4 are connected. The source of the high-low voltage isolation transistor HN2 is connected to the drain of N4. The drain of the high-low voltage isolation transistor HP4 is connected to the positive electrode of the Zener diode Z2, and the source of the bias transistor N4 is grounded. The high-low voltage isolation transistors enable the circuit to operate in the high-voltage region and improve the reliability of the circuit, and the Zener diodes enable the circuit to switch between the low-voltage operating state and the high-voltage operating state.
[0030] The bias circuit includes a current source IB and a bias transistor N3. The gate, drain of the bias transistor N3 are connected to the current source IB, and the source of the bias transistor N3 is grounded.
[0031] One end of the sampling resistor R3 is connected to the source of the comparison transistor HP3 as the sampling signal. The source and drain of the high-voltage isolation transistor HP4 are respectively connected to the gate of the comparison transistor HP2 and the gate of the comparison transistor HP3. The drain and source of the high-voltage low isolation transistor HN3 are respectively connected to the drain of the comparison transistor HP2 and the drain of N5. The drain and source of the high-voltage low isolation transistor HN4 are respectively connected to the drain of the comparison transistor HP3 and the drain of N6. The gate of the current-limiting transistor N2 is connected to the drain of N6. The gate of the biasing transistor N3 is connected to the gates of N4, N5, and N6.
[0032] The source of HP3 in the high-voltage resistant current-limiting circuit is connected to the source of HP1 in the LDO feedback control loop with a wide input voltage range. The drain of N2 in the high-voltage resistant current-limiting circuit is connected to the source of N1 in the LDO feedback control loop with a wide input voltage range. The source of HP2 in the high-voltage resistant current-limiting circuit is connected to the output VOUT in the LDO feedback control loop with a wide input voltage range; the input VIN is connected to the negative electrode of the Zener diode Z1, the negative electrode of the Zener diode Z2, the other end of the sampling resistor R3, and the source of the LDO power transistor to connect the input voltage VIN; the current source IB, the gates of the high-voltage isolation transistors HN2, HN3, HN4, HN1, and the power supply voltage of the error amplifier are connected to the divided voltage VDD of VIN; the divided voltage VDD is a low-voltage input signal.
[0033] Based on the above circuit, the working principle of the current-limiting circuit in this solution is as follows:
[0034] When operating in the low-voltage range: At this time, neither of the two Zener diodes is broken down. The gate voltage of HP4 is pulled down to ground, and HP4 conducts. The gate potentials of HP2 and HP3 are the same. When VIN is small and the circuit operates in the voltage drop region, VOUT cannot reach the nominal output voltage VOUT(NOM). The feedback signal FB < VREF generated by the feedback resistor, and the output of the error amplifier, that is, the gate potential of N1, increases. The gate potential of HP1 is pulled down, that is, the gate potential of the Power transistor is pulled down, which promotes the rise of VOUT, and a feedback loop is formed. At this time, V OUT ≈V IN . At this time, the potential at point A is low, less than VOUT. HP3 operates in the subthreshold region. The potential at point B is low, and current-limiting in the voltage drop region is achieved through N2. When VIN > VOUT(NOM) + ΔV (the magnitude of ΔV is directly related to R3), at this time, the potential at point A is high, the pulling-up ability of HP3 is enhanced, the potential at point B is high. At the same time, since VOUT has reached the nominal output voltage VOUT(NOM) at this time, the output of the error amplifier, that is, the gate potential of N1, decreases, and the potential at point C also decreases. N2 operates in the linear region and has no impact on the LDO feedback control loop.
[0035] When working in the high-voltage range: When VIN rises to a certain level, Z1 breaks down, and the gate of HP4 becomes one breakdown voltage smaller than VIN, rising as VIN rises. After rising to a certain level, HP4 turns off, and Z2 breaks down. At this time, the gate of HP3 becomes one breakdown voltage smaller than VIN, and HP4 withstands high-voltage and low-voltage isolation. Since the gate-source voltage of HP3 is fixed and large, the voltage at point B is also pulled up to a relatively high level, and N2 works in the linear region, having no impact on the LDO feedback control loop.
[0036] The circuit forms a loop at points A and B. Therefore, the potential of the current-limiting signal at point B is not either high or low, but an analog level, making the current in the voltage drop region have no spikes and be less than the current value during stable output.
[0037] Figure 3 The figure shows the comparison diagram before and after current limiting of the present invention. It can be seen from the figure that VOUT is the output of the LDO, and the current-limiting circuit has no impact on it during stable output. I1 is the simulation result of the short-circuit current-limiting transistor N2, that is, the current curve in the voltage drop region before current limiting. It can be seen that the current in the voltage drop region is very large and has spikes. I2 is the current curve in the voltage drop region after current limiting, and it can be seen that the current in the voltage drop region has no spikes and is less than the current during stable output.
[0038] The examples described in the present invention are only descriptions of the preferred embodiments of the present invention, not limitations on the concept and scope of the present invention. Without departing from the design concept of the present invention, various deformations and improvements made by those skilled in the art to the technical solutions of the present invention should fall within the protection scope of the present invention.
Claims
1. A current limiting circuit applicable to an LDO circuit with a wide input voltage range, characterized in that, Comprising: An LDO feedback control loop with a wide input voltage range and a high-voltage resistant current limiting circuit; The LDO feedback control loop with a wide input voltage range includes an error amplifier, a driving transistor N1, a high-voltage and low-voltage isolation transistor HN1, a current sampling transistor HP1, an LDO power transistor, and feedback resistors R1 and R2; The non-inverting input terminal of the error amplifier is connected to the reference voltage VREF, the inverting input terminal of the error amplifier is connected to one end of the feedback resistors R1 and R2, the output terminal of the error amplifier is connected to the gate of the driving transistor N1, the drain of the driving transistor N1 is connected to the source of the high-voltage and low-voltage isolation transistor HN1, the drain of the high-voltage and low-voltage isolation transistor HN1 is connected to the gate, drain of the current sampling transistor HP1, and the gate of the LDO power transistor, the drain of the LDO power transistor is connected to the other end of the feedback resistor R2, and the other end of the feedback resistor R1 is connected to the ground terminal; The high-voltage resistant current limiting circuit includes a sampling resistor R3, a current comparator, a bias circuit, a high-voltage and low-voltage isolation circuit, and a current limiting transistor N2; The bias circuit provides bias for the high-voltage and low-voltage isolation circuit and the current comparator, and the high-voltage and low-voltage isolation circuit enables the current comparator to operate in a high-voltage environment; The current comparator includes a comparison transistor HP2, a comparison transistor HP3, a bias transistor N5, and a bias transistor N6; The gate and drain of the comparison transistor HP2 are connected, the gates of the bias transistors N5 and N6 are connected, and the sources of the bias transistors N5 and N6 are respectively grounded; The high-voltage and low-voltage isolation circuit includes a Zener diode Z1, a Zener diode Z2, a high-voltage and low-voltage isolation transistor HP4, a high-voltage and low-voltage isolation transistor HN3, a high-voltage and low-voltage isolation transistor HN4, a high-voltage and low-voltage isolation transistor HN2, and a bias transistor N4; The positive electrode of the Zener diode Z1, the drain of the high-voltage and low-voltage isolation transistor HN2, and the gate of the high-voltage and low-voltage isolation transistor HP4 are connected, the source of the high-voltage and low-voltage isolation transistor HN2 is connected to the drain of the bias transistor N4, the drain of the high-voltage and low-voltage isolation transistor HP4 is connected to the positive electrode of the Zener diode Z2, and the source of the bias transistor N4 is grounded; The bias circuit includes a current source IB and a bias transistor N3, the gate, drain of the bias transistor N3 are connected to the current source IB, and the source of the bias transistor N3 is grounded; One end of the sampling resistor R3 is connected to the source of the comparison transistor HP3, the source and drain of the high-voltage and low-voltage isolation transistor HP4 are respectively connected to the gate of the comparison transistor HP2 and the gate of the comparison transistor HP3, the drain and source of the high-voltage and low-voltage isolation transistor HN3 are respectively connected to the drain of the comparison transistor HP2 and the drain of the bias transistor N5, the drain and source of the high-voltage and low-voltage isolation transistor HN4 are respectively connected to the drain of the comparison transistor HP3 and the drain of the bias transistor N6, the gate of the current limiting transistor N2 is connected to the drain of the bias transistor N6, and the gate of the bias transistor N3 is connected to the gates of the bias transistors N4, N5, and N6.
2. The circuit according to claim 1, characterized in that, The source of the comparator tube HP3 in the high-voltage-resistant current-limiting circuit is connected to the source of the comparator tube HP1 in the LDO feedback control loop with a wide input voltage range. The drain of the current-limiting tube N2 in the high-voltage-resistant current-limiting circuit is connected to the source of the current-limiting tube N1 in the LDO feedback control loop with a wide input voltage range. The source of the comparator tube HP2 in the high-voltage-resistant current-limiting circuit is connected to the output VOUT in the LDO feedback control loop with a wide input voltage range; the input VIN is connected to the negative electrode of the Zener diode Z1, the negative electrode of the Zener diode Z2, the other end of the sampling resistor R3, and the source of the LDO power tube to connect the input voltage VIN; the current source IB, the gates of the high-low voltage isolation tubes HN2, HN3, HN4, HN1, and the power supply voltage of the error amplifier are connected to the divided voltage VDD of VIN; the divided voltage VDD is a low-voltage input signal.
3. The circuit according to claim 2, wherein When the circuit operates in the low-voltage region, the Zener diodes Z1 and Z2 are not broken down, the high-low voltage isolation tube HP4 is turned on, and the gate voltages of the comparator tubes HP2 and HP3 are equal.
4. The circuit according to claim 2, wherein When the circuit operates in the high-voltage region, the Zener diodes Z1 and Z2 are broken down, the high-low voltage isolation tube HP4 is turned off, the gate-source voltage of the comparator tube HP3 is clamped within the breakdown voltages of the Zener diodes Z1 and Z2, and the high-low voltage isolation tube HP4 plays a role in high-low voltage isolation.
5. The circuit according to claim 2, wherein The current sampling tube HP1, the power tube of the LDO, the comparator tubes HP2 and HP3, and the high-low voltage isolation tube HP4 are made of P-type high-voltage-resistant LDMOS tubes; The high-low voltage isolation tubes HN1, HN2, HN3, and HN4 are made of N-type high-voltage-resistant LDMOS tubes; The driver tubes N1, N2, and the bias tubes N3, N4, N5, N6 are made of NMOS tubes.
Citation Information
Patent Citations
High-current high-power-supply-rejection-ratio LDO voltage stabilizer
CN111290462A
Power circuit
JP1997034572A