Calibration method, circuit, storage medium, clock recovery circuit and electronic device

Abstract

The present application provides a calibration method, circuit, storage medium, clock recovery circuit, and electronic device. The calibration method includes configuring a reference signal source to output a reference signal, wherein the reference signal includes a first number of reference signal waves; delaying the reference signal through a delay chain to output a delayed signal, wherein the delay chain includes a plurality of delay units; synchronously sampling the reference signal and the delayed signal; when the sampling result is a preset state, performing a count increment by 1 and obtaining a final count value; determining whether the ratio of the count value to the first number is within a preset range; when the ratio is within the preset range, obtaining an average delay time based on the time width of the reference signal wave and the number of enabled delay units; and outputting a control signal to the clock recovery circuit based on the average delay time to calibrate the delay time of the clock recovery circuit. The calibration method provided by the present application can realize dynamic calibration of the clock recovery circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and in particular to a calibration method, a calibration circuit, a storage medium, a clock recovery circuit and an electronic device for calibrating a delay time in a clock recovery circuit. Background Art

[0002] Current high-speed serial bus protocols typically include a clock signal within the data, eliminating the need for a separate clock signal to be transmitted in parallel with the data. Therefore, to correctly sample the data at the receiving end, the clock signal must be extracted from the data signal, a process known as clock recovery.

[0003] During the operation of the clock recovery circuit, an appropriate delay time needs to be provided to avoid data transmission failures caused by jitter, skew, and / or inter-symbol interference generated by the circuit. However, in existing clock recovery circuits, the delay time of each delay unit in the clock recovery circuit may deviate due to the influence of temperature, voltage, process, etc., resulting in a large error in the delay time, which in turn prevents data from being transmitted normally. For example, in some cases, for every 10-degree increase in temperature, the delay time of the clock recovery circuit increases by 1%, and the corresponding operating frequency decreases by 1%; for every 5% increase in voltage, the delay time decreases by 3%, and the corresponding operating frequency increases by 3%. In other words, the delay time in the current clock recovery circuit is easily affected by the environment, thereby affecting data transmission. Therefore, how to provide a method to reduce the error of the delay time in the clock recovery circuit has become an urgent problem that needs to be solved. Summary of the Invention

[0004] In view of the above, it is necessary to provide a calibration method, a correction circuit and an electronic device having the circuit to correct the delay time and ensure normal data transmission.

[0005] The first aspect of the present application provides a calibration method, including configuring a reference signal source to output a reference signal, and the reference signal includes a first number of reference signal waves; delaying the reference signal through a delay chain to output a delayed signal, the delay chain including a plurality of delay units; synchronously sampling the reference signal and the delayed signal; when the sampling result is a preset state, counting by 1 and obtaining a final count value; determining whether the ratio of the count value to the first number is within a preset range; when the ratio is within the preset range, obtaining an average delay time based on the time width of the reference signal wave and the number of delay units turned on in the delay chain; and outputting a control signal to a clock recovery circuit based on the average delay time to calibrate the delay time of the clock recovery circuit.

[0006] In some embodiments, the delayed signal includes a plurality of delayed signal waves, and a preset state is that the reference signal wave and the delayed signal wave at least partially overlap.

[0007] In some embodiments, when the ratio reaches a preset threshold, obtaining the average delay time based on the time width of the reference signal wave and the number of delay units turned on in the delay chain includes: obtaining the initial delay time based on the time width of the reference signal wave and the number of delay units turned on in the delay chain; repeatedly executing the calibration method to obtain several groups of initial delay times; and obtaining the average delay time based on preset rules and several groups of initial delay times.

[0008] In some embodiments, the preset rule includes: obtaining an average value of several groups of initial delay times as the average delay time; or obtaining a median value of several groups of initial delay times as the average delay time.

[0009] In some embodiments, outputting a control signal to a clock recovery circuit based on an average delay time to calibrate the delay time of the clock recovery circuit includes: obtaining a target delay time of the clock recovery circuit; determining the number of delay units turned on in the clock recovery circuit based on the average delay time and the target delay time, recorded as a second number; and outputting a control signal to the clock recovery circuit, wherein the control signal includes a numerical value of the second number.

[0010] In some embodiments, when the ratio is not within a preset range, the number of delay units in the delay chain is reconfigured and the calibration method is re-executed until the ratio is within the preset range.

[0011] A second aspect of the present application provides a computer-readable storage medium. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the calibration method as described in any one of the above items.

[0012] A third aspect of the present application provides a calibration circuit for calibrating the delay time of a clock recovery circuit, the calibration circuit comprising: a reference signal source for outputting a reference signal, wherein the reference signal comprises a first number of reference signal waves; a delay chain for delaying the reference signal to output a delayed signal, wherein the delay chain comprises a plurality of delay units; a sampling circuit for synchronously sampling the reference signal and the delayed signal; a counter for counting by adding 1 when the sampling result of the sampling circuit is in a preset state, and obtaining a final count value; a calculation circuit for obtaining the final count value of the counter to determine whether the ratio of the count value to the first number is within a preset range; the calculation circuit is also for calculating the average delay time according to the time width of the reference signal wave and the number of delay units turned on in the delay chain when the ratio is within the preset range; and a control circuit for outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

[0013] A fourth aspect of the present application provides a clock recovery circuit, which is connected to the calibration circuit as described above, and is used to receive a control signal output by the calibration circuit to adjust the calibration delay time according to the control signal.

[0014] A fifth aspect of the present application provides an electronic device comprising the clock recovery circuit as described above.

[0015] The present application configures a reference signal source to output a reference signal, and delays the reference signal through a delay chain to obtain a delayed signal. Based on the width of the reference signal wave and synchronous sampling of the reference signal and the delayed signal, the average delay time of each delay unit in the delay chain is estimated and output to a clock recovery circuit to calibrate the delay time of the clock recovery circuit. It can be understood that, compared to the existing method of further adjusting the delay time by decoding the preamble sequence of the received packet data, the calibration method provided by the present application does not require data channel resources, and the adjustment is more convenient and rapid, with simple control logic. It can achieve dynamic calibration of the clock recovery circuit, thereby reducing the interference caused by factors such as temperature, voltage, and / or process on the delay time output by the clock recovery circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a flowchart of a calibration method provided in one embodiment of the present application.

[0017] Figure 2 for Figure 1 The timing diagram of some signals involved in the flow chart shown.

[0018] Figure 3 for Figure 1 The flowchart of the sub-steps included in step S160 is shown.

[0019] Figure 4 for Figure 1 The flowchart of the sub-steps included in step S170 is shown.

[0020] Figure 5 A circuit block diagram of an electronic device provided in one embodiment of the present application.

[0021] Figure 6 A schematic diagram of the structure of an electronic device that implements calibration using the calibration method provided in an embodiment of the present application.

[0022] Description of main component symbols

[0023] electronic device 100

[0024] Processor 101

[0025] Memory 102

[0026] Computer Programs 103

[0027] Calibration circuit 200

[0028] Reference signal source 210

[0029] Delay Chain 220

[0030] Sampling circuit 230

[0031] Counter 240

[0032] Calculation circuit 250

[0033] Control circuit 260

[0034] Clock recovery circuit 300

[0035] Electronic device 400

[0036] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0037] It should be noted that when an element is referred to as being "electrically connected" to another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "electrically connected" to another element, it may be a contact connection, for example, a wire connection, or a contactless connection, for example, a contactless coupling.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0039] Current high-speed serial bus protocols typically include a clock signal within the data, eliminating the need for a separate clock signal to be transmitted in parallel with the data. Therefore, to correctly sample the data at the receiving end, a clock recovery circuit must be used to extract the clock signal from the data signal. This is the clock recovery process.

[0040] The clock recovery circuit includes a delay chain, and the delay chain includes a number of delay units. The delay chain is used to provide an appropriate delay time to avoid data transmission failures caused by jitter, skew, and / or inter-symbol interference generated by the circuit. However, in existing clock recovery circuits, the delay time of each delay unit may deviate due to the influence of temperature, voltage, process, etc., resulting in a large error in the delay time, which in turn causes data to be unable to be transmitted normally. For example, in some cases, for every 10-degree increase in temperature, the delay time of the clock recovery circuit increases by 1%, and the corresponding operating frequency decreases by 1%; for every 5% increase in voltage, the delay time decreases by 3%, and the corresponding operating frequency increases by 3%. In other words, the delay time in the current clock recovery circuit is easily affected by the environment, thereby affecting data transmission.

[0041] To do this, see Figure 1 One embodiment of the present application provides a calibration method that calculates the average delay time of each delay unit and outputs the average delay time to a clock recovery circuit to assist the clock recovery circuit in adjusting the number of enabled delay units, thereby calibrating the delay time in the clock recovery circuit. It will be appreciated that the calibration method provided by the present application can be implemented using other circuits connected to the clock recovery circuit, such as a calibration circuit.

[0042] In some embodiments, the calibration method provided in an embodiment of the present application includes the following steps:

[0043] Step S110 : configuring a reference signal source to output a reference signal CLOCK, wherein the reference signal CLOCK includes a first number of reference signal waves.

[0044] The reference signal source is used to output a periodic signal. For example, in some embodiments, a low-speed clock is used as the reference signal source to obtain a more accurate clock signal as the reference signal CLOCK. It will be understood that the present application does not limit the type of reference signal source. In other embodiments, other signal sources may be selected as the reference signal source based on actual conditions. For example, in some embodiments, an external signal source, such as an external crystal oscillator outputting the reference signal CLOCK, or an internal signal source, such as the output signal of a phase-locked loop, may be used as the reference signal CLOCK.

[0045] It is understood that the reference signal wave can be a square wave, a triangular wave, or other waveform, and this application does not limit the waveform or number of the reference signal waves. In the embodiment of this application, the specific working process of the calibration method is illustrated by taking the reference signal wave as a square wave and the reference signal source outputting 1000 square waves (i.e., the first number is 1000) each time it is started.

[0046] Step S120 : Delay the reference signal CLOCK via a delay chain to output a delayed signal DLY.

[0047] In step S120, a delay chain includes a plurality of delay cells for delaying the reference signal CLOCK. The number of delay cells configured in the delay chain can be adjusted as needed. For example, in an embodiment of the present application, 10 delay cells can be initially configured in the delay chain to delay the reference signal CLOCK, and the number can be adjusted later.

[0048] It can be understood that, ideally, the number of delayed signal waves of the delay signal DLY is equal to the number of reference signal waves, and the time width of the delayed signal wave is equal to the time width of the reference signal wave. Figure 2 , that is, ideally, the delay signal DLY also has 1000 square waves, and the time width of each square wave is equal to the time width of the square wave in the reference signal CLOCK.

[0049] It can be understood that the delay unit can be an element for delaying the phase, such as an inverter, a buffer, or a circuit for implementing the delay of the phase.

[0050] Step S130 : synchronously sampling the reference signal CLOCK and the delay signal DLY.

[0051] Step S140: When the sampling result is in a preset state, count by 1 and obtain a final count value.

[0052] In the present application, the preset state is that the reference signal wave and the delayed signal wave at least partially overlap.

[0053] For example, in the embodiment of the present application, the reference signal wave is a square wave, and accordingly, the delayed signal wave is also a square wave. Then, in step S140 , the default state may be that the reference signal CLOCK is at a falling edge and the delay signal DLY is at a high level.

[0054] Please refer again Figure 2 It can be understood that when the first reference signal wave of the reference signal and the first delayed signal wave of the delayed signal meet a predetermined condition, it indicates that the delay chain has completed the phase delay of at least one signal in the reference signal CLOCK within the time width of the reference signal wave, such as ΔT. Thus, the total delay time of the enabled delay cells in the current delay chain is less than or equal to ΔT. In particular, when the sampling result shows that the reference signal CLOCK is at a falling edge and the delayed signal DLY is exactly at a rising edge, that is, the phase of the delayed signal DLY lags the phase of the reference signal CLOCK by 180 degrees, it indicates that the total delay time of the enabled delay cells in the current delay chain is equal to ΔT.

[0055] It can be understood that since the time width △T of the reference signal wave is relatively short (for example, reaching the nanosecond level), when the first reference signal wave of the reference signal and the first delayed signal wave of the delayed signal meet the preset state, it can be approximately considered that the total delay time of the delay unit turned on in the delay chain is △T.

[0056] Furthermore, when the sampling result is in the preset state, a count is incremented. That is, after the reference signal CLOCK is output, the first time the sampling result is in the preset state, it is counted as 1; the second time the sampling result is in the preset state, it is counted as 2, and so on. This count is repeated until all 1000 reference signals CLOCK and the corresponding 1000 delay signals DLY are synchronously sampled. The final count value obtained is the number of times the sampling result in step S140 is in the preset state.

[0057] Step S150: Determine whether the ratio of the count value to the first quantity is within a preset range.

[0058] It is understood that, ideally, when the delay signal DLY lags the reference signal by less than 180 degrees, the count value obtained in step S140 should be 1000. However, due to errors that may occur during the operation of the delay chain and / or errors that may occur during the sampling process, the count value obtained in step S140 may be slightly less than 1000. If the delay chain has too many delay cells, causing the delay signal DLY to lag the reference signal CLOCK by more than 180 degrees, the count value obtained in step S140 may be significantly less than 1000. In this case, the time width ΔT of the reference signal wave is less than . Therefore, a preset range can be set. By confirming whether the ratio of the count value to the first number is within the preset range, the appropriate number of delay cells in the current delay chain can be determined. For example, in the embodiment of the present application, the preset range may be [90%, 100%].

[0059] For example, in the embodiment of the present application, when the final count value obtained in step S140 is 900, the ratio of the count value to the first number is 90%, which falls within the preset range. Therefore, it can be considered that the number of enabled delay cells in the delay chain configured in step S120 meets the requirement for calculating the average delay time of each delay cell.

[0060] It is understandable that the present application does not limit the preset range. In other embodiments, the preset range may also be other numerical ranges.

[0061] Step S160 : When the ratio is within a preset range, obtaining an average delay time according to the time width ΔT of the reference signal wave and the number of enabled delay units in the delay chain.

[0062] It is understood that in the embodiment of the present application, the number of delay units configured in step S120 is 10. Taking ΔT as 10 ns (nanoseconds) as an example, the average delay time of each delay unit in the delay chain is 1 ns.

[0063] It is understood that when the ratio in step S150 is not within the preset range, the number of delay units in the delay chain can be reconfigured and the above steps can be re-executed until the ratio is within the preset range, thereby further obtaining the average delay time.

[0064] Step S170 : Outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

[0065] It is understood that the delay unit used to calculate the average delay time in the embodiment of the present application is the same electronic component as the delay unit in the clock recovery circuit. Thus, the average delay time calculated in step S160 can be converted into a digital signal for output to the clock recovery circuit. The clock recovery circuit adjusts the number of enabled delay units in its own delay chain based on the target delay time and the received average delay time.

[0066] It can be understood that the target delay time can be the delay time provided by the clock recovery circuit calculated based on multiple sets of experimental data, which is used to reduce the probability of data transmission failure due to jitter, skew and / or inter-symbol interference generated by the circuit.

[0067] For example, in some embodiments, when the target delay time of the clock recovery circuit is 15 ns, the average delay time of each delay unit calculated according to step S160 is 1 ns, and the number of delay units turned on in the delay chain of the clock recovery circuit is 15 / 1=15.

[0068] It can be understood that in some embodiments, the above-mentioned calibration method can be run at preset time intervals after the electronic device is powered on to dynamically calculate the average delay time and output it to the clock recovery circuit, thereby dynamically adjusting the number of delay units turned on in the clock recovery circuit, and then dynamically calibrating the delay time of the clock recovery circuit.

[0069] The calibration method provided by the present application configures a reference signal source to output a reference signal CLOCK, and delays the reference signal CLOCK through a delay chain to obtain a delayed signal DLY. Based on the time width ΔT of the reference signal wave and the synchronous sampling of the reference signal CLOCK and the delayed signal DLY, the average delay time of each delay unit in the delay chain is estimated and output to a clock recovery circuit to calibrate the delay time of the clock recovery circuit. It can be understood that, compared to the existing method of further adjusting the delay time by decoding the preamble sequence of the received packet data, the calibration method provided by the present application does not require data channel resources, and the adjustment is more convenient and rapid, with simple control logic. It can achieve real-time dynamic calibration of the clock recovery circuit, thereby reducing the interference caused by factors such as temperature, voltage, and / or process on the delay time output by the clock recovery circuit.

[0070] For further information, please refer to Figure 3 In some embodiments, step S160 further includes:

[0071] Step S161 : obtaining an initial delay time according to the time width of the reference signal wave and the number of enabled delay units in the delay chain.

[0072] It can be understood that the method for calculating the initial delay time in step S161 is the same as or similar to the method for calculating the average delay time in step S160 , both of which are obtained by dividing the time width ΔT of the reference signal wave by the number of delay units configured in the delay chain.

[0073] Step S162: Repeat the above steps in the calibration method to obtain several sets of initial delay times.

[0074] It can be understood that after the average delay time is obtained in step S161, steps S110 to S161 are repeatedly performed to obtain several groups of initial delay times.

[0075] Step S163: Obtain an average delay time according to a preset rule and several groups of initial delay times.

[0076] In some embodiments, the preset rule may be to obtain an average value of several groups of initial delay times as the average delay time.

[0077] In other embodiments, the preset rule may also be to obtain the median of several groups of initial delay times as the average delay time.

[0078] It is understood that in other embodiments, the average delay time may be obtained based on a preset formula and several groups of initial delay times. This application does not specifically limit the preset formula.

[0079] Thus, in some embodiments, by executing the above steps S161 to S163 , the accuracy of the calculated average delay time can be further improved by obtaining multiple groups of initial delay times.

[0080] Further, see Figure 4 In some embodiments, step S170 further includes:

[0081] Step S171: Obtain the target delay time of the clock recovery circuit.

[0082] Step S172: Determine the number of delay units enabled in the clock recovery circuit according to the average delay time and the target delay time, and record it as a second number.

[0083] For example, in some embodiments, the number of delay units enabled in the clock recovery circuit is estimated by dividing the target delay time by the average delay time. It will be appreciated that when the value of the target delay time divided by the average delay time is not an integer, a rounding function may be used to obtain an integer representing the number of delay units in the clock recovery circuit.

[0084] Step S173: Output a control signal to the clock recovery circuit, wherein the control signal includes a second number of values.

[0085] In step S173, the second number is first converted into a digital code. This is then output to the clock recovery circuit via a control signal including the code of the second number. Upon receiving the control signal, the clock recovery circuit adjusts the number of enabled delay cells in its delay chain based on the code information included in the control signal.

[0086] It can be understood that in some embodiments, by executing the above steps S171 to S173, the complexity of the circuit structure of the clock recovery circuit is reduced and the control logic of the clock recovery circuit is simplified.

[0087] In some embodiments, the calibration method further includes receiving a feedback signal, where the feedback signal is used to provide feedback on whether an abnormality occurs in the sampling of the current receiving end.

[0088] When it is confirmed through the feedback signal that the sampling of the current receiving end is abnormal, the above steps S110 to S170 are re-executed to recalibrate the delay time of the clock recovery circuit.

[0089] It should be noted that the present application does not limit the specific structure of the clock recovery circuit. The calibration method or calibration circuit provided in the present application is applicable to any clock recovery circuit having several delay units.

[0090] Please continue reading Figure 5Another embodiment of the present application further provides a calibration circuit 200 for implementing the above calibration method. In this embodiment of the present application, the calibration circuit 200 includes a reference signal source 210, a delay chain 220, a sampling circuit 230, a counter 240, a calculation circuit 250, and a control circuit 260.

[0091] The reference signal source 210 is configured to output a reference signal. The reference signal source 210 is a periodic signal source. The reference signal includes a first number of reference signal waves.

[0092] The delay chain 220 is used to delay a reference signal to output a delayed signal. The delay chain 220 includes a plurality of delay units (not shown), and the number of enabled delay units in the delay chain 220 is adjustable.

[0093] The sampling circuit 230 is used to synchronously sample the reference signal and the delayed signal.

[0094] The counter 240 is configured to count up by 1 when the sampling result of the sampling circuit is in a preset state.

[0095] The calculation circuit 250 is configured to obtain a final count value of the counter and determine whether a ratio of the count value to the first number is within a preset range.

[0096] The calculation circuit 250 is further configured to calculate an average delay time according to the time width of the reference signal wave and the number of enabled delay units in the delay chain when the ratio is within a preset range.

[0097] The control circuit 260 is configured to output a control signal to the clock recovery circuit according to the average delay time, so as to calibrate the delay time of the clock recovery circuit.

[0098] It can be understood that the reference signal source 210, the delay chain 220, the sampling circuit 230, the counter 240, the calculation circuit 250 and the control circuit 260 in the calibration circuit 200 are used to perform Figure 1 ,and Figure 3-Figure 4 For details of the steps in the corresponding embodiments, please refer to the description of the relevant content above and will not be repeated here.

[0099] It is understood that the calculation circuit 250 also includes a filter (not shown). The filter is used to enable the calculation circuit 250 to obtain an average delay time from several groups of initial delay times when executing steps S161 to S163. It is understood that in some embodiments, the filter can be an average filter or a median filter; in other embodiments, the filter can also be any one or a combination of an infinite impulse response (IIR) filter or a finite impulse response (FIR) filter, and this application is not limited to this.

[0100] Please refer again Figure 5 Another embodiment of the present application further provides a clock recovery circuit 300. The clock recovery circuit 300 is connected to the calibration circuit 200 described above. The clock recovery circuit 300 is configured to receive a control signal output by the calibration circuit 200 and adjust the number of enabled delay units based on the control signal, thereby calibrating the delay time.

[0101] It is understood that the present application does not limit the specific structure of the clock recovery circuit 300. Furthermore, the implementation of the clock recovery circuit 300 should not be used to limit the scope of the present invention.

[0102] Please continue reading Figure 5 Another embodiment of the present application further provides an electronic device 400. The electronic device 400 includes the calibration circuit 200 and the clock recovery circuit 300 described above. It is understood that in some embodiments, the electronic device 400 may be a slave device having a high-speed transmission interface, such as an interface compliant with the Mobile Industry Processor Interface (MIPI) C-PHY specification, for receiving information from a master device (not shown). In some embodiments, the electronic device 400 may include, but is not limited to, a display, a laptop computer, a smart speaker, and other devices capable of receiving information.

[0103] Please continue reading Figure 6 An embodiment of the present application further provides a computer-readable storage medium storing a computer program 103 including at least one instruction, wherein the at least one instruction is executed by the processor 101 in the electronic device 100 to implement the above calibration method.

[0104] Exemplarily, the computer program may be divided into one or more modules / units, one or more of which are stored in memory 102 and executed by processor 101 to implement the calibration method provided by the present invention. One or more modules / units may be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of computer program 103 in the electronic device.

[0105] The present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through the computer program 103. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, executable files or some intermediate forms. The computer-readable medium may include: any entity or device that can carry computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical signals and software distribution media, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0106] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Those skilled in the art will appreciate that the technical solutions of the present invention may be modified or replaced with equivalents without departing from the spirit and scope of the technical solutions of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort shall fall within the scope of protection of the present invention.

Claims

1. A calibration method for calibrating the delay time of a clock recovery circuit, characterized in that: The method comprises: Configuring a reference signal source to output a reference signal, wherein the reference signal includes a first number of reference signal waves; delaying the reference signal through a delay chain to output a delayed signal, wherein the delay chain includes a plurality of delay units; synchronously sampling the reference signal and the delayed signal; When the sampling result is the preset state, count up by 1 and obtain the final count value; determining whether a ratio of the count value to the first quantity is within a preset range; When the ratio is within the preset range, obtaining an average delay time according to the time width of the reference signal wave and the number of enabled delay units in the delay chain; A control signal is output to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

2. The calibration method according to claim 1, wherein: The delayed signal includes a plurality of delayed signal waves, and the preset state is that the reference signal wave and the delayed signal wave at least partially overlap.

3. The calibration method according to claim 1, wherein: When the ratio is within the preset range, obtaining the average delay time according to the time width of the reference signal wave and the number of enabled delay units in the delay chain includes: Obtaining an initial delay time according to the time width of the reference signal wave and the number of enabled delay units in the delay chain; Repeating the calibration method to obtain several sets of initial delay times; The average delay time is obtained according to a preset rule and several groups of the initial delay times.

4. The calibration method according to claim 3, wherein: The preset rules include: Obtaining an average value of several groups of the initial delay times as the average delay time; or The median value of several groups of the initial delay times is obtained as the average delay time.

5. The calibration method according to claim 1, wherein: Outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit includes: Obtaining a target delay time of the clock recovery circuit; Determining the number of delay units enabled in the clock recovery circuit according to the average delay time and the target delay time, recorded as a second number; A control signal is output to the clock recovery circuit, wherein the control signal includes a value of the second quantity.

6. The calibration method according to claim 1, wherein: When the ratio is not within the preset range, the number of delay units in the delay chain is reconfigured, and the calibration method is re-executed until the ratio is within the preset range.

7. A computer-readable storage medium, characterized in that When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is caused to perform the calibration method according to any one of claims 1 to 6.

8. A calibration circuit for calibrating the delay time of a clock recovery circuit, characterized in that: The calibration circuit comprises: A reference signal source, configured to output a reference signal, wherein the reference signal includes a first number of reference signal waves; a delay chain, configured to delay the reference signal to output a delayed signal, wherein the delay chain comprises a plurality of delay units; A sampling circuit for synchronously sampling a reference signal and a delayed signal; The counter is used to count up by 1 when the sampling result of the sampling circuit is in a preset state and obtain a final count value; a calculation circuit, configured to obtain a final count value of the counter to determine whether a ratio of the count value to the first number is within a preset range; The calculation circuit is further configured to calculate an average delay time based on the time width of the reference signal wave and the number of enabled delay units in the delay chain when the ratio is within the preset range; A control circuit is configured to output a control signal to the clock recovery circuit according to the average delay time, so as to calibrate the delay time of the clock recovery circuit.

9. A clock recovery circuit, characterized in that: The clock recovery circuit is connected to the calibration circuit according to claim 8 , and is configured to receive a control signal output by the calibration circuit to adjust a calibration delay time according to the control signal.

10. An electronic device, characterized in that: The electronic device comprises the clock recovery circuit according to claim 9.

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