Display device

Abstract

A display device according to an embodiment of the disclosure can include a display panel including a plurality of pixels connected to a data line and a gate line, a data driver configured to be driven by being divided into a driving period in which a data voltage is applied to the data line and a blank period in which the data voltage is not applied, a gate driver configured to apply a scan signal to the gate line, and a controller configured to control the plurality of pixels to drive in one band of a plurality of bands having different maximum target luminances, wherein a resident voltage can be applied to the data line during the blank period, and a voltage level of the resident voltage applied to the data line is different in at least one of the plurality of bands from a voltage level of the resident voltage applied to the data line in another band of the plurality of bands.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0129648, filed on September 30, 2021, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] Embodiments of this disclosure relate to a display device, and more specifically, to a display device capable of improving uniformity degradation caused by brightness non-uniformity, such as flicker and strain. Background Technology

[0004] Display devices that display various information on a screen are an important technology in the information and communication age, and they are evolving towards thinner, lighter, more portable, and higher-performance designs. Therefore, display devices that can be manufactured in a lightweight and slim form have become a focus of attention. Display devices using self-emissive elements not only have advantages in power consumption due to low-voltage operation, but also offer excellent high-speed response, high luminous efficiency, viewing angle, and contrast, and are being researched as next-generation display devices. Display devices realize images through multiple sub-pixels arranged in a matrix. Each of the multiple sub-pixels includes a light-emitting device and pixel circuitry (e.g., multiple transistors independently driving the light-emitting device).

[0005] Specific examples of such flat panel displays can include liquid crystal displays (LCDs), quantum dot displays (QDs), field emission displays (FEDs), and organic light-emitting diode (OLED) displays. OLED displays do not require a separate light source and are attracting attention as devices for compact devices and vibrant color displays. OLED displays use organic light-emitting diodes (OLEDs) that emit light themselves and have advantages such as fast response time, high contrast, high luminous efficiency, high brightness, and wide viewing angle.

[0006] Organic light-emitting diode (OLED) display devices, which include OLEDs, display images based on light generated by light-emitting devices within pixels, offering numerous advantages. However, uniformity defects can arise due to uneven brightness, such as flickering and blemishes, caused by coupling between lines within pixels during driving or the operating conditions of the driving signal. This can be a factor reducing satisfaction with the image quality of the display device.

[0007] Therefore, various driving techniques have been developed to address image anomalies, and to improve image quality, it is necessary to improve performance by controlling the driving conditions of pixels. Summary of the Invention

[0008] The purpose of embodiments of this disclosure is to provide a display device capable of improving flicker and uniformity degradation by controlling the driving voltage conditions of the pixel circuit.

[0009] In one aspect of this disclosure, a display device is provided, comprising: a display panel including a plurality of pixels connected to data lines and gate lines; a data driver configured to drive by dividing into a driving period during which a data voltage is applied to the data lines and a blank period during which no data voltage is applied; a gate driver configured to apply a scan signal to the gate lines; and a controller configured to control the plurality of pixels to drive in one of a plurality of frequency bands having different maximum target brightness, wherein a parking voltage may be applied to the data lines during the blank period, and the voltage level of the parking voltage applied to the data lines in at least one of the plurality of frequency bands is different from the voltage level of the parking voltage applied to the data lines in another of the plurality of frequency bands.

[0010] In addition to the technical problems of this disclosure described above, other features and advantages of this disclosure will be described below, or will be clearly understood by those skilled in the art from these descriptions.

[0011] According to embodiments of this disclosure, by applying a dwell voltage to each of a plurality of frequency bands, the non-uniformity of the dwell voltage can be reduced and the uniformity of the display panel can be improved to enhance image quality.

[0012] The effects of this disclosure are not limited to those exemplified above; this disclosure may include many more effects. Attached Figure Description

[0013] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0014] Figures 2A to 2C This is a circuit diagram illustrating the pixel circuitry of a display device according to an embodiment of the present disclosure.

[0015] Figures 3A to 3C This is a diagram illustrating the driving of the pixel circuit and the light-emitting device of a display device according to an embodiment of the present disclosure.

[0016] Figure 4 The operation of a scan signal of a frame in a display device according to an embodiment of the present disclosure is illustrated.

[0017] Figure 5 The dimming level of each frequency band of the pixel circuit in the display device according to an embodiment of the present disclosure is shown.

[0018] Figure 6The dimming level adjustment method for each frequency band of the pixel circuit in the display device according to an embodiment of the present disclosure is shown.

[0019] Figure 7A The data voltage and dwell voltage of a display device according to an embodiment of the present disclosure are shown. Figure 7B The waveform changes of the second node are shown according to the duty cycle of the light-emitting signal in the pixel circuit.

[0020] Figure 8 The non-uniformity of the dwell voltage generated by the dwell voltage in the display device according to an embodiment of the present disclosure is shown.

[0021] Figures 9A to 9B This is a diagram illustrating the calculation of the optimal dwell voltage in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0022] The advantages and features of this disclosure, as well as its methods, will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. These embodiments are provided only to explain that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of this disclosure, which will be defined by the scope of the claims.

[0023] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to explain the embodiments in this specification are exemplary, and the embodiments in this specification are not limited to those shown in the drawings. Furthermore, in describing embodiments, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the gist of the embodiments.

[0024] In the use of terms such as “comprising,” “having,” “comprising,” or “including” in this specification, unless “only” is used, it should be understood that other parts or elements can be added. When an element is represented in the singular, unless otherwise expressly stated, it should be understood that the plural case is also included.

[0025] Furthermore, when interpreting components, even without a separate explicit description, they should be interpreted as including a range of error.

[0026] In descriptions relating to spatial relationships, for example, when the terms “upper,” “above,” “below,” “below,” “under,” “lower,” “near,” “close to,” or “adjacent” are used to describe the positional relationship between two elements, unless terms such as “directly” or “only” are used, it should be understood that one or more elements may be further inserted between the elements.

[0027] When describing temporal relationships, such as when the temporal relationship is described as "after", "following", "next", "then", or "before", discontinuous situations may be included unless "immediately" or "directly" is used.

[0028] When terms such as "first" and "second" are used herein to describe various elements or components, it should be understood that these elements or components are not limited thereto. These terms are used only to distinguish one element from other elements. Therefore, the first element mentioned below may be a second element in the technical concept of this disclosure.

[0029] The term "at least one" should be understood to include all possible combinations of one or more related elements. For example, "at least one of the first, second, and third elements" can mean two or more of the first, second, and third elements, as well as all combinations of each of the first, second, and third elements.

[0030] Features of each embodiment in this specification can be combined or integrated with each other in part or in whole, and can be interconnected or operated with each other in various technical ways. Furthermore, each embodiment can be implemented independently of the other, or can be implemented together in a related manner.

[0031] In the following description, embodiments of the display device according to the present disclosure will be described with reference to the accompanying drawings. When adding reference numerals to components in each drawing, identical components may have the same reference numerals whenever possible, even if they are shown in different drawings. Furthermore, for ease of explanation, the scale of components shown in the drawings may differ from the actual scale, and the scale shown in the drawings is not limited thereto.

[0032] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0034] Reference Figure 1 The display device 10 may include: a display panel 100 including a plurality of pixels; a gate driver 300 for providing gate signals to each of the plurality of pixels; a data driver 400 for providing data signals to each of the plurality of pixels; a light emission signal generator 500; and a controller 200 for providing light emission signals to each of the plurality of pixels.

[0035] The controller 200 can process externally input RGB image data according to the size and resolution of the display panel 100, and provide the processed image data to the data driver 400. The controller 200 can use externally input synchronization signals SYNC, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsyn, to generate multiple gate control signals GCS, data control signals DCS, and light emission control signals ECS. The generated multiple gate control signals GCS, data control signals DCS, and light emission control signals ECS can be provided to the gate driver 300, the data driver 400, and the light emission signal generator 500 respectively to control the gate driver 300, the data driver 400, and the light emission signal generator 500.

[0036] Depending on the device on which the controller is installed, the controller 200 can be configured in combination with various processors (e.g., microprocessors, mobile processors, application processors, etc.).

[0037] The controller 200 can generate signals that allow pixels to be driven at various refresh rates. That is, the controller 200 can generate drive-related signals that enable pixels to be driven in a variable refresh rate (VRR) mode or to allow pixels to switch between a first refresh rate and a second refresh rate. For example, the controller 200 can simply change the speed of a clock signal to generate a synchronization signal to produce horizontal or vertical spacing, or use a masking method with the gate driver 300 to drive pixels at various refresh rates.

[0038] Furthermore, the controller 200 can generate various signals for driving the pixel at a first refresh rate. Specifically, when driving at the first refresh rate, a light emission control signal ECS can be generated to cause the light emission signal generator 500 to generate a light emission signal EM(N) with a first duty cycle. Subsequently, the controller 200 can operate to drive the pixel at a second refresh rate, and can generate various signals for driving the pixel at the second refresh rate. Specifically, when driving the pixel at the second refresh rate, the controller can generate the light emission control signal ECS to cause the light emission signal generator 500 to generate a light emission signal EM(N) with a second duty cycle different from the first duty cycle.

[0039] The gate driver 300 can provide the scan signal SC to the gate line GL according to the gate control signal GCS provided from the controller 200. Although Figure 1 The gate driver 300 is shown to be spaced apart from one side of the display panel 100, but the number and arrangement of the gate drivers 300 are not limited thereto. That is, the gate drivers 300 can be disposed on one or both sides of the display panel 100 using the gate in-plane (GIP) method.

[0040] The data driver 400 converts image data RGB into data voltage Vdata according to the data control signal DCS provided by the controller 200, and provides the converted data voltage Vdata to the pixels through the data line DL.

[0041] In the display panel 100, multiple gate lines GL, multiple emitter lines EL, and multiple data lines DL can intersect each other, and each of the multiple pixels can be connected to the gate lines GL, emitter lines EL, and data lines DL. Specifically, a pixel receives a gate signal from a gate driver 300 via the gate line GL, a data signal from a data driver 400 via the data line DL, a light emission signal EM(N) via the emitter line EL, and various power supply signals via power lines. Here, the gate line GL provides a scan signal SC, the emitter line EL provides the light emission signal EM(N), and the data line DL provides a data voltage Vdata. However, according to various embodiments, the gate line GL may include multiple scan signal lines, and the data line DL may additionally include multiple power supply lines VL. Furthermore, the emitter line EL may include multiple light emission signal lines. In addition, a pixel receives a high potential voltage or a first power supply voltage ELVDD and a low potential voltage or a second power supply voltage ELVSS. Furthermore, a first bias voltage V1 and a second bias voltage V2 can be provided through one or more power supply lines VL.

[0042] Furthermore, each pixel includes a light-emitting device (ELD) and a pixel circuit for controlling the ELD. Here, the ELD includes an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The pixel circuit includes multiple switching devices, driving switching devices, and a capacitor. Here, the switching devices can be composed of TFTs, and in the pixel circuit, the driving TFT controls the amount of current supplied to the ELD based on the difference between the data voltage charged into the capacitor and a reference voltage, thereby adjusting the amount of light emitted by the ELD. Additionally, the multiple switching TFTs receive a scan signal SC provided through the gate line GL and a light emission signal EM(N) provided through the emission line EL to apply the data voltage Vdata to the capacitor.

[0043] The display device 10 according to embodiments of the present disclosure may include a gate driver 300, a data driver 400, a light-emitting signal generator 500 for driving a display panel 100 including a plurality of pixels, and a controller 200 for controlling the gate driver 300, the data driver 400, and the light-emitting signal generator 500. Here, the light-emitting signal generator 500 may be configured to adjust the duty cycle of the light-emitting signal EM(N). For example, the light-emitting signal generator 500 may include a shift register and a latch for adjusting the duty cycle of the light-emitting signal EM(N). When the pixel circuit is driven at a first refresh rate according to the light-emitting control signal ECS generated by the controller 200, the light-emitting signal generator 500 may generate a light-emitting signal having a first duty cycle and provide the light-emitting signal to the pixel circuit. When the pixel circuit is driven at a second refresh rate, the light-emitting signal generator 500 may be configured to generate a light-emitting signal having a second duty cycle different from the first duty cycle and provide the light-emitting signal to the pixel circuit.

[0044] Figures 2A to 2C This is a circuit diagram illustrating the pixel circuitry of a display device according to an embodiment of the present disclosure.

[0045] Figure 2 illustrates only a pixel circuit for explanation and is not limited thereto, as long as it has a structure capable of controlling the light emission of the light-emitting device ELD by applying a light emission signal EM(N). For example, the pixel circuit may include an additional scan signal, a switching TFT connected thereto, and a switching TFT to which an additional initialization voltage is applied, and the connection relationship between the switching devices or the connection position of the capacitors may be set in various ways. That is, if the light emission of the light-emitting device ELD is controlled according to the change of the duty cycle of the light emission signal EM(N), and the light emission can be controlled according to the refresh rate, then pixel circuits with various structures can be used. For example, various pixel circuits such as 3T1C, 4T1C, 6T1C, 7T1C, and 7T2C can be used. In the following description, for ease of description, a display device including the 7T1C pixel circuit of Figure 2 will be described.

[0046] Reference Figure 2A Each of the multiple pixels P may include a pixel circuit with a driving transistor DT and a light-emitting device ELD connected to the pixel circuit.

[0047] The pixel circuit drives the light-emitting device (ELD) by controlling the drive current Id flowing through it. The pixel circuit may include a drive transistor DT, first to sixth transistors T1 to T6, and a storage capacitor Cst. Each of transistors DT and T1 to T6 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other may be a drain electrode.

[0048] Each of transistors DT and T1 through T6 can be a PMOS transistor or an NMOS transistor. Figure 2A and Figure 2B In this embodiment, the first transistor T1 is an NMOS transistor, and the other transistors DT and T2 through T6 are PMOS transistors. Furthermore, in... Figure 2C In one embodiment, the first transistor T1 is also configured as a PMOS transistor.

[0049] In the following description, the case where the first transistor T1 is an NMOS transistor and the remaining transistors DT, T2 through T6 are PMOS transistors will be exemplarily described. Therefore, the first transistor T1 is turned on by applying a logic high voltage, and the other transistors DT, T2 through T6 are turned on by applying a logic low voltage.

[0050] According to one example, the first transistor T1 constituting the pixel circuit can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, and the fifth transistor T5 and the sixth transistor T6 can be used as bias transistors.

[0051] A light-emitting device (ELD) may include a pixel electrode (or anode) and a cathode. The pixel electrode of the ELD may be connected to a fifth node N5, and the cathode may be connected to a second power supply voltage ELVSS.

[0052] The driving transistor DT may include a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a gate electrode connected to a first node N1. The driving transistor DT may provide a driving current Id to the light-emitting device ELD based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst, described later).

[0053] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode for receiving the first scan signal SC1. The first transistor T1 may be turned on in response to the first scan signal SC1 and may transmit a data signal Vdata to the first node N1. The first transistor T1 may be diode-connected between the first node N1 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0054] A capacitor Cst can be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst can store or maintain the provided data signal Vdata.

[0055] The second transistor T2 has a first electrode connected to the data line DL (or to receive the data signal Vdata), a second electrode connected to the second node N2, and a gate electrode for receiving the third scan signal SC3. The second transistor T2 can be turned on in response to the third scan signal SC3 and can transmit the data signal Vdata to the second node N2. The second transistor T2 can be a data supply transistor.

[0056] The third transistor T3 and the fourth transistor T4 (or the first light-emitting control transistor and the second light-emitting control transistor) can be connected between the first power supply voltage ELVDD and the light-emitting device ELD, and can form a current movement path through which the driving current Id generated by the driving transistor DT flows.

[0057] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the first power supply voltage ELVDD, a second electrode connected to the second node N2, and a gate electrode for receiving the light emission signal EM(N).

[0058] Similarly, the fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fourth node N5 (or the pixel electrode of the light-emitting device ELD), and a gate electrode for receiving the light-emitting signal EM(N).

[0059] The third transistor T3 and the fourth transistor T4 can be turned on in response to the light emission signal EM(N), and in this case, the drive current Id is provided to the light emission device ELD, and the light emission device ELD can emit light with a brightness corresponding to the drive current Id.

[0060] The fifth transistor T5 may include a first electrode connected to the third node N3, a second electrode receiving a first bias voltage V1, and a gate electrode receiving a second scan signal SC2.

[0061] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode receiving a second bias voltage V2, and a gate electrode receiving a second scan signal SC2. Figure 2A In this configuration, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to jointly receive the second scan signal SC2. However, this disclosure is not limited thereto, such as... Figure 2B and Figure 2C As shown, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to receive separate scan signals for independent control.

[0062] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode connected to the second bias voltage V2, and a gate electrode for receiving the second scan signal SC2. The sixth transistor T6 may be turned on in response to the second scan signal SC2 before (or after) the light-emitting device ELD emits light, and the pixel electrode (or anode) of the light-emitting device ELD may be initialized using the second bias voltage V2. The light-emitting device ELD may have a parasitic capacitor formed between the pixel electrode and the cathode. Furthermore, the parasitic capacitor is charged when the light-emitting device ELD emits light, allowing the pixel electrode of the light-emitting device ELD to have a specific voltage. Therefore, by applying the second bias voltage V2 to the pixel electrode of the light-emitting device ELD via the sixth transistor T6, the amount of charge accumulated in the light-emitting device ELD can be initialized.

[0063] Figure 3 is a diagram illustrating the driving of the pixel circuit and light-emitting device of the display device shown in Figure 2.

[0064] Referring to Figure 3, each of the plurality of pixels P can initialize the voltage charged or remaining in the pixel circuit. Specifically, the effects of the data voltage Vdata and drive voltage VDD stored in the previous frame can be eliminated. Therefore, each of the plurality of pixels P can display an image corresponding to the new data voltage Vdata.

[0065] The operation of a pixel circuit may include an initialization period, a sampling period, and an emission period, but this is just an example and is not necessarily limited to this order.

[0066] In the following text, reference will be made to Figures 3A to 3C Describe in detail the process of driving the pixel circuit for each of the initialization period, sampling period, and emission period.

[0067] Figure 3A This corresponds to the initialization period. The initialization period is the time during which the voltage of the gate electrode of the driving transistor DT is initialized.

[0068] exist Figure 3AIn the initialization process, the first scan signal SC1 is a logic high voltage, and the first transistor T1 is turned on. The second scan signal SC2 is a logic low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. With the first transistor T1 and the fifth transistor T5 turned on, the gate electrode of the driving transistor DT connected to the first node N1 is initialized to the first bias voltage V1. Furthermore, with the sixth transistor T6 turned on, the pixel electrode (or anode) of the light-emitting device ELD is initialized to the second bias voltage V2. However, as mentioned above, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to be controlled independently by receiving separate scan signals. That is, during the initialization period, it is not always necessary to apply bias voltages to the source electrode of the driving transistor DT and the pixel electrode of the light-emitting device ELD simultaneously.

[0069] Figure 3B The sampling period is shown. Figure 3B In this process, a logic low voltage is input as the third scan signal SC3, and the second transistor T2 is turned on. With the second transistor T2 turned on, the current frame's Vdata voltage is applied to the drain electrode of the driving transistor DT connected to the second node N2, while the first transistor T1 remains on. Since the driving transistor DT is in a diode-connected state when the first transistor T1 is on, the voltage at the gate electrode of the driving transistor DT connected to the first node N1 becomes Vdata - |Vth|. That is, the first transistor T1 can be diode-connected between the first node N1 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT.

[0070] Figure 3C The emission period is shown. The emission period is the time during which the light-emitting device (ELD) emits light with a drive current corresponding to the sampled data voltage after the threshold voltage Vth of the sample has been eliminated.

[0071] exist Figure 3C In the middle, the light-emitting signal EM(N) is at a logic low voltage, and the third transistor T3 and the fourth transistor T4 are turned on.

[0072] With the third transistor T3 turned on, the first power supply voltage ELVDD, connected to the fourth node N4, is applied through the third transistor T3 to the drain electrode of the driving transistor DT, which is connected to the second node N2. The driving current Id supplied by the driving transistor DT to the light-emitting device ELD via the fourth transistor T4 is independent of the threshold voltage Vth of the driving transistor DT, thus the threshold voltage Vth of the driving transistor DT can be compensated.

[0073] Figure 4 The operation of a scan signal of a frame in a display device according to an embodiment of the present disclosure is illustrated.

[0074] Reference Figure 4 Each of the multiple pixels P can be driven at a constant frequency, or it can be driven in a variable refresh rate (VRR) mode. In the variable refresh rate mode, when high-speed driving is required, the refresh rate used to update the data voltage Vdata is increased to operate the pixel circuit, or when low-speed driving is required, the refresh rate is decreased to operate the pixel circuit to reduce power consumption.

[0075] Each of multiple pixels P can be driven by a combination of refresh frames and hold frames within a single frame.

[0076] For example, when driven at a 120Hz refresh rate, it can be driven by only the refresh frame, and when driven at a 60Hz refresh rate, the refresh frame and the hold frame can be driven alternately. That is, the refresh frame and the hold frame can be driven alternately 60 times in one frame.

[0077] Therefore, during low-speed driving, refresh frames and hold frames are driven alternately, and in the hold frame, the pixel electrode of the light-emitting device ELD is periodically initialized by the sixth transistor T6 of the pixel circuit, thereby reducing the hysteresis characteristics of the driving transistor DT.

[0078] In this case, the second scan signal SC2 provided from the gate driver 300 to drive the sixth transistor T6 can be driven at a frequency twice as high as the driving frequency provided from the controller 200 to the display panel 100.

[0079] For example, if the refresh rate is 120Hz, the drive frequency can operate at 120Hz, and the second scan signal SC2 used to turn on the TFT can operate at 240Hz. That is, since the second scan signal SC2 is driven at a frequency twice as high as the drive frequency, the sixth transistor T6 is turned on more often, and the fifth node N5 is initialized more frequently, thereby improving the performance of the drive transistor DT.

[0080] Figure 5 The dimming levels of each frequency band of the pixel circuit in a display device according to an embodiment of the present disclosure are shown.

[0081] Reference Figure 5The display panel 100 may include multiple frequency bands, Band 1, Band 2, Band 3, ..., Band 13, to apply target brightness Lv according to different working environments. Multiple frequency bands, Band 1, Band 2, Band 3, ..., Band 13, can serve as a reference for adjusting the dimming level. For example, the first frequency band, Band 1, can be set for the maximum target brightness Lv required based on the ambient illuminance during the day. The second frequency band, Band 2, can be set for situations in shadows during the day. The seventh frequency band, Band 7, can be set for cloudy days, and the eighth frequency band, Band 8, can be set for nighttime environments. The thirteenth frequency band, Band 13, can be set for darkroom environments. Furthermore, the frequency bands can be further subdivided and categorized according to various usage environments and applications.

[0082] Multiple frequency bands (Band1, Band2, Band3, ..., Band13) can have their dimming levels varied to adjust the brightness step size for specific grayscale levels. Furthermore, the target brightness Lv can be set so that all frequency bands (Band1, Band2, Band3, ..., Band13) have the same number of brightness steps. For example, the target brightness Lv of the first frequency band (Band1) and the target brightness Lv of the second frequency band (Band2) can have a difference of 256 steps.

[0083] The dimming level used to adjust brightness can vary from 0 to 100%. Even with the same gray level, the dimming level differs depending on the frequency band, thus resulting in different brightness levels. For example, the maximum target brightness Lv of the first frequency band, Band 1, can have a dimming level of 100%. Furthermore, the dimming level can be adjusted by the data voltage applied to the pixel, or it can be adjusted based on the duty cycle of the emission signal EM(N).

[0084] Figure 6 The dimming level adjustment method for each frequency band of the pixel circuit in the display device according to an embodiment of the present disclosure is shown.

[0085] Reference Figure 6 The dimming levels of multiple bands Band1, Band2, Band3, ..., Band13 can be adjusted based on at least one of the duty cycle of the data voltage Vdata applied to the pixel or the duty cycle of the emission signal EM(N).

[0086] In multiple frequency bands (Band1, Band2, Band3, ..., Band13), the maximum target brightness Lv of one band can be the same as the minimum target brightness Lv of another band. For example, the minimum target brightness Lv of the first frequency band (Band1) can be the maximum target brightness Lv of the second frequency band (Band2).

[0087] Because the first to seventh frequency bands (Band1, Band2, ..., Band7) have relatively high target brightness (Lv), the brightness variation at each grayscale level will be significant. In this case, since brightness corresponds to the data voltage (Vdata), the dimming level can be adjusted by changing the data voltage (Vdata).

[0088] In bands 8 through 13 (Band 8, Band 9, ..., Band 13), the target brightness Lv is relatively low and the brightness variation at each gray level is small. Adjusting the dimming level via the data voltage Vdata might not drive the pixels properly. Therefore, the dimming level in bands 8 through 13 (Band 8, Band 9, ..., Band 13) can be adjusted via the duty cycle of the emission signal EM(N).

[0089] In other words, in the first to seventh frequency bands (Band1, Band2, ..., Band7), the duty cycle of the emitted signal EM(N) can be fixed or constant, and the dimming level can be adjusted by changing the data voltage Vdata. On the other hand, in the eighth to thirteenth frequency bands (Band8, Band9, ..., Band13), the data voltage Vdata can be fixed or constant, and the dimming level can be adjusted by changing the duty cycle of the emitted signal EM(N).

[0090] Figure 7A The data voltage and dwell voltage of a display device according to an embodiment of the present disclosure are shown. Figure 7B The waveform changes of the second node are shown according to the duty cycle of the light-emitting signal in the pixel circuit.

[0091] Reference Figure 7A The period during which data voltage is applied can be a driving period, and the period during which no data voltage is applied can be a blank period. A refresh frame can be included during the driving period, and both refresh frames and hold frames can be included during the blank period.

[0092] When the data line DL is in a floating state during the idle period, the adjacent first node N1 and second node N2 may be affected by coupling, which may cause flickering.

[0093] Therefore, for drives such as Variable Refresh Rate (VRR) mode, a dwell voltage V can be applied during the idle period after the data voltage Vdata is applied to the data line DL and before the data voltage Vdata of the next frame is applied. park .

[0094] The dwell voltage V at a specific voltage level is applied. park In this case, a dwell voltage V is required. parkTo control the flicker performance of all grayscale levels, it may be based on the data voltage Vdata and the dwell voltage V park The relationship between these factors identifies non-uniformity at specific gray levels, such as that caused by blemishes. This non-uniformity can be termed voltage non-uniformity (Vpark Mura).

[0095] In addition, when a specific voltage level of dwell voltage V is applied during the blank period park At this time, because the second scan signal SC2, which is sequentially applied to the gate line GL, operates at twice the driving frequency, multiple pixels located in the central portion of the display panel 100 can operate, causing the sixth transistor T6 to conduct. As a result, coupling occurs between the data line DL and the fifth node N5, which may cause uneven dwell voltage (Vpark Mura) in the central region of the display panel 100, thereby reducing uniformity.

[0096] Uneven dwell voltage based on dwell voltage V park The voltage level is more sensitive to low gray levels, and the light-emitting device (ELD) may emit light unnecessarily.

[0097] Reference Figure 7B Even if the data voltage Vdata and the dwell voltage V park Even at the same voltage level, the luminous characteristics may differ depending on the duty cycle of the luminous signal EM(N).

[0098] like Figure 6 As shown, the first to seventh frequency bands, Band1, Band2, ..., Band7, have relatively high target brightness Lv, and the duty cycle of the emission signal EM(N) can be fixed, and the dimming level can be adjusted by changing the data voltage Vdata. Furthermore, in the eighth to thirteenth frequency bands, Band8, Band9, ..., Band13, the data voltage Vdata can be fixed, and the dimming level can be adjusted by changing the duty cycle of the emission signal EM(N).

[0099] Therefore, since the first to seventh frequency bands (Band1, Band2, ..., Band7) use the same duty cycle of the emission signal EM(N), their emission characteristics are also the same. On the other hand, in the eighth to thirteenth frequency bands (Band8, Band9, ..., Band13), since the dimming level is adjusted by the duty cycle of the emission signal EM(N), their emission characteristics may differ from one another.

[0100] In other words, in the second node N2 connected to the third transistor T3 which is turned on / off according to the light emission signal EM(N), the voltage waveform can vary according to the duty cycle of the light emission signal EM(N).

[0101] For example, if the duty cycle of the emitted signal EM(N) is 90%, then when the dwell voltage V is applied... park During the blank period, the voltage waveform of the second node (node2) can remain unchanged even if no light emission signal EM(N) is applied. Furthermore, if the duty cycle of the light emission signal EM(N) is 4%, the voltage waveform of the second node (node2) can change only when the light emission signal EM(N) is applied.

[0102] In other words, due to the required dwell voltage V park The voltage level varies depending on the brightness. To reduce flicker and uneven dwell voltage, different dwell voltages V need to be applied to each of the multiple frequency bands Band1, Band2, Band3, ..., Band13. park .

[0103] Figure 8 The non-uniformity of the dwell voltage generated by the dwell voltage in the display device according to an embodiment of the present disclosure is shown.

[0104] Reference Figure 8 Region A is an area with uneven dwell voltage identified in the low grayscale range, which can be identified using black light voltage V. black and blue light voltage V blue To calculate the optimal dwell voltage V park .

[0105] Each of the multiple pixels can have subpixels that emit different colors of light, from the first subpixel to the third subpixel. For example, the first subpixel can emit red light, the second subpixel can emit green light, and the third subpixel can emit blue light. Besides red, green, and blue light, the first to third subpixels can be driven independently or together to represent color. Furthermore, blue light emitted from the third subpixel can be driven at the lowest voltage level, and black light can be driven at the highest voltage level.

[0106] In this case, the dwell voltage V park The closer to the black light voltage V black Uneven residence voltage will be perceived as darker. In other words, if the residence voltage V... park Set to the first level V park1 If this occurs, the red, green, and blue light from the first to the third sub-pixel will all be up-coupled, resulting in uneven visible dwell voltage in dark areas.

[0107] Conversely, if the dwell voltage V park Set to near blue light voltage V blue The second level V park2 This may result in uneven red dwell voltage due to the effect of dual coupling.

[0108] Therefore, it is necessary to reduce the dwell voltage V park Set to blue light voltage V blue With black light voltage V black The internal division point between them is used to balance the data voltage Vdata and the dwell voltage V. park The differences between them.

[0109] Figures 9A to 9B This is a diagram illustrating the calculation of the optimal dwell voltage in a display device according to an embodiment of the present disclosure.

[0110] Referring to Figure 9, multiple frequency bands Band1, Band2, Band3, ..., Band13 represent different target brightness Lv. Among the multiple frequency bands Band1, Band2, Band3, ..., Band13, the first to seventh frequency bands Band1, Band2, ..., Band7 can have the same luminous characteristics, while the eighth to thirteenth frequency bands Band8, Band9, ..., Band13 can control the dimming level by changing the duty cycle of the luminous signal EM(N). Therefore, the optimal dwell voltage V... park They may differ from each other due to their different luminescent properties.

[0111] In this case, within the seventh band (Band 7) and the thirteenth band (Band 13) with different luminescence characteristics, the black light voltage V can be used as a reference. black With blue light voltage V blue The optimal dwell voltage V is calculated using a specific ratio relationship expression between them. park .

[0112] For example, the maximum target brightness Lv of Band 7 (7th band) can be 100 nits, and the maximum target brightness Lv of Band 13 (13th band) can be 4 nits. The 44 gray levels of Band 7 (7th band) and the 205 gray levels of Band 13 (13th band) each correspond to a brightness level of 2 nits, and at brightness levels higher than these, no unevenness in the dwell voltage will be detected.

[0113] To balance the data voltage Vdata and the dwell voltage V park The difference between them requires the dwell voltage V to be adjusted. park Set to blue light voltage V blue With black light voltage V black The dividing point between them. The optimal dwell voltage V in Band 7. park_a It can be calculated based on [Equation 1] derived from the visual evaluation experiment.

[0114] [Equation 1]

[0115]

[0116] In equation 1, V park_a The optimal dwell voltage in Band 7 is V. black The voltage for black light, V blue (G1) is the blue light voltage in the first gray level G1. For example, the gray level G1 can have 44 gray levels.

[0117] Similarly, in the thirteenth band (Band 13) with the lowest maximum target luminance Lv, the optimal dwell voltage V is compared to that in the seventh band (Band 7). park_b It can get closer to the black light voltage V black And it can be calculated according to [Equation 2].

[0118] [Equation 2]

[0119]

[0120] In equation 2, V park_b It is the optimal dwell voltage in Band 13, V black It is the voltage of black light, V blue (G2) is the blue light voltage in the second gray level G2. Here, the second gray level G2 can be a higher gray level than the first gray level G1, for example, it can be 205 gray levels.

[0121] Furthermore, for the remaining eighth to twelfth frequency bands (Band 8, Band 9, ..., Band 12) with different luminescence characteristics, the optimal dwell voltage V can be calculated in the seventh frequency band (Band 7). park_a The optimal dwell voltage V calculated in Band 13. park_b Linear interpolation between the two values ​​is used to obtain each dwell voltage V. park .

[0122] Therefore, by calculating the dwell voltage V for each of the multiple frequency bands Band1, Band2, Band3, ..., Band13 during the blank period... park Applying this to the data line DL can reduce dwell voltage unevenness (Vpark Mura).

[0123] Furthermore, as the dwell voltage non-uniformity decreases, the uniformity of the display panel 100 can be improved, and the image quality can be enhanced.

[0124] The display device according to embodiments of the present disclosure can be described as follows.

[0125] A display device according to embodiments of the present disclosure may include: a display panel including a plurality of pixels connected to data lines and gate lines; a data driver configured to drive by dividing the drive period into a drive period for which a data voltage is applied to the data lines and a blank period for which no data voltage is applied; a gate driver configured to apply a scan signal to the gate lines; and a controller configured to control the plurality of pixels to drive at an intermediate frequency band among a plurality of frequency bands having different maximum target brightness. In this case, a dwell voltage may be applied to the data lines during the blank period, and the voltage level of the dwell voltage applied to the data lines in at least one of the plurality of frequency bands may be different from the voltage level of the dwell voltage applied to the data lines in another of the plurality of frequency bands.

[0126] In the display device according to embodiments of the present disclosure, the multiple frequency bands may include a first frequency band to a thirteenth frequency band, and in the first frequency band to the thirteenth frequency band, the dimming level may be adjusted according to the duty cycle of the light emission signal or the magnitude of the data voltage.

[0127] In the display device according to embodiments of the present disclosure, the duty cycle of the light emission signal can be constant in the first to seventh frequency bands, and the data voltage can be varied.

[0128] In the display device according to embodiments of the present disclosure, the first to seventh frequency bands may have the same light emission characteristics. In each of the first to seventh frequency bands, the light emission characteristics of the pixels may be the same.

[0129] In a display device according to an embodiment of the present disclosure, the dwell voltage in the seventh frequency band can be calculated using Equation 1.

[0130] In the display device according to embodiments of the present disclosure, the duty cycle of the light emission signal can be varied in the eighth to thirteenth frequency bands, and the data voltage can be constant.

[0131] In a display device according to an embodiment of the present disclosure, the dwell voltage in the thirteenth frequency band can be calculated using Equation 2.

[0132] In a display device according to an embodiment of the present disclosure, the dwell voltage can be calculated using the voltage ratio of black light to blue light.

[0133] In the display device according to embodiments of the present disclosure, the dwell voltage of the first frequency band to the seventh frequency band may be the same.

[0134] In a display device according to an embodiment of the present disclosure, the dwell voltages of the eighth to twelfth frequency bands can be calculated by linear interpolation between the dwell voltages of the seventh and thirteenth frequency bands.

[0135] In a display device according to an embodiment of the present disclosure, the controller can change the driving frequency according to the refresh rate, and the frequency of the scan signal applied by the gate driver can be higher than the driving frequency.

[0136] In a display device according to an embodiment of the present disclosure, the scanning signal may be twice the driving frequency.

[0137] The features, structures, effects, etc., described in the examples above in this disclosure are included in at least one embodiment of this disclosure, and are not necessarily limited to one embodiment. Furthermore, those skilled in the art to which this disclosure pertains can combine or modify the features, structures, effects, etc., shown in at least one example of this disclosure with respect to other examples. Therefore, anything relating to these combinations and modifications should be interpreted as being included within the scope of this disclosure.

[0138] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications can be made to the present disclosure without departing from the spirit of the present disclosure. Therefore, the embodiments disclosed herein are not intended to limit the spirit of the present disclosure, but rather to exemplify the present disclosure, and the scope of the spirit of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of protection of this disclosure should be interpreted by the appended claims, and all technical concepts within their equivalents should be interpreted as included within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels connected to data lines and gate lines; A data driver configured to drive by dividing the data line into a driving period in which a data voltage is applied and a blank period in which no data voltage is applied; A gate driver configured to apply a scan signal to the gate line; as well as A controller configured to drive the plurality of pixels to one of a plurality of frequency bands having different maximum target brightness. During the blank period, a dwell voltage is applied to the data line. Wherein, the voltage level of the dwell voltage applied to the data line in at least one of the multiple frequency bands is different from the voltage level of the dwell voltage applied to the data line in another of the multiple frequency bands, and The dwell voltage is calculated using the voltage ratio of black light to blue light.

2. The display device according to claim 1, wherein, The multiple frequency bands include the first frequency band to the thirteenth frequency band. The dimming levels of the first frequency band to the thirteenth frequency band are adjusted according to the duty cycle of the emitted signal or the magnitude of the data voltage.

3. The display device according to claim 2, wherein, In the first to seventh frequency bands, the duty cycle of the emitted signal is constant, while the data voltage is variable.

4. The display device according to claim 3, wherein, The first to the seventh frequency bands have the same luminescence characteristics.

5. The display device according to claim 3, wherein, In the seventh frequency band, based on the black light voltage V using the following equation 1... black And the blue light voltage V in the first gray level G1 blue To calculate the dwell voltage V park_a , [Equation 1] 。 6. The display device according to claim 2, wherein, In the eighth to the thirteenth frequency bands, the duty cycle of the light-emitting signal is variable, and the data voltage is constant.

7. The display device according to claim 6, wherein, In the thirteenth frequency band, based on the black light voltage V using the following equation 2... black Blue light voltage V in the second gray level G2 blue To calculate the dwell voltage V park_b , [Equation 2] 。 8. The display device according to claim 1, wherein, The plurality of frequency bands includes the first to the thirteenth frequency bands, and the dwell voltages of the first to the seventh frequency bands are the same.

9. The display device according to claim 1, wherein, The dwell voltages of the eighth to twelfth frequency bands are calculated by linear interpolation between the dwell voltage of the seventh frequency band and the dwell voltage of the thirteenth frequency band.

10. The display device according to claim 1, wherein, The controller changes the drive frequency according to the refresh rate. The frequency of the scan signal applied by the gate driver is higher than the driving frequency.

11. The display device according to claim 10, wherein, The scanning signal is twice the driving frequency.

12. The display device according to claim 1, wherein, The dwell voltage is the inner dividing point between the blue light voltage and the black light voltage.

Images