Read voltage correction method, storage device and memory control circuit unit

Abstract

The present application provides a read voltage correction method, a memory storage device and a memory control circuit unit. The method comprises: reading data from a first physical cell using a plurality of read voltage levels; decoding the data to obtain a plurality of error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining a plurality of candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the plurality of candidate read voltage levels; and re-reading the data from the first physical cell using the target read voltage level. Thus, the correction efficiency of the read voltage level can be effectively improved.

Description

Technical Field

[0001] The present invention relates to a memory control technology, and in particular to a read voltage correction method, a memory storage device, and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as smartphones and laptops have experienced rapid growth in recent years, leading to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideal for integration into various portable electronic devices, due to their non-volatility, power efficiency, compact size, and lack of mechanical structure.

[0003] In a memory storage device where a single memory cell can store multiple bits, multiple preset read voltage levels can be used to read the data stored in the memory cell. However, after a period of use, as the memory cell wears out, these preset read voltage levels may shift relative to the critical voltage distribution of the memory cell. Reading data using these shifted read voltage levels may increase the bit error rate and even shorten the lifespan of the memory storage device. Summary of the Invention

[0004] The present invention provides a read voltage correction method, a memory storage device and a memory control circuit unit, which can improve the correction efficiency of the read voltage level.

[0005] An exemplary embodiment of the present invention provides a read voltage correction method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical cells. The read voltage correction method includes: reading data from a first physical cell among the plurality of physical cells using a plurality of read voltage levels; decoding the data to obtain a plurality of error assessment parameters, wherein the plurality of error assessment parameters respectively correspond to one of the plurality of read voltage levels; determining a first vector distance parameter based on a first error assessment parameter among the plurality of error assessment parameters, wherein the first error assessment parameter corresponds to a first read voltage level among the plurality of read voltage levels; determining a plurality of candidate read voltage levels based on the first vector distance parameter and the first read voltage level; determining a target read voltage level based on one of the plurality of candidate read voltage levels; and rereading the data from the first physical cell using the target read voltage level.

[0006] In an example embodiment of the present application, the step of decoding the data to obtain the plurality of error evaluation parameters comprises performing a parity check operation on the data read using the first read voltage level to obtain a syndrome sum, and obtaining the first error evaluation parameter according to the syndrome sum.

[0007] In an example embodiment of the present application, the read voltage correction method further comprises comparing the plurality of error evaluation parameters, and determining one of the plurality of error evaluation parameters as the first error evaluation parameter according to the comparison result.

[0008] In an example embodiment of the present application, the step of determining the first vector distance parameter according to the first error evaluation parameter of the plurality of error evaluation parameters comprises converting the first error evaluation parameter to the first vector distance parameter according to a conversion function.

[0009] In an example embodiment of the present application, the step of determining the plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level comprises determining a first coordinate point in a coordinate space according to the first read voltage level, obtaining a plurality of second coordinate points in the coordinate space according to the first coordinate point and the first vector distance parameter, and determining the plurality of candidate read voltage levels according to the plurality of second coordinate points.

[0010] In an example embodiment of the present application, the plurality of candidate read voltage levels comprises a first candidate read voltage level and a second candidate read voltage level, and the step of determining the target read voltage level according to one of the plurality of candidate read voltage levels comprises obtaining a first candidate vector distance parameter between the first candidate read voltage level and a second read voltage level of the plurality of read voltage levels, obtaining a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level, and determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter.

[0011] In an exemplary embodiment of the present invention, the step of determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first candidate vector distance parameter and the second candidate vector distance parameter includes: determining a second vector distance parameter based on a second error assessment parameter among the multiple error assessment parameters, wherein the second error assessment parameter corresponds to the second read voltage level; obtaining a first difference between the first candidate vector distance parameter and the second vector distance parameter; obtaining a second difference between the second candidate vector distance parameter and the second vector distance parameter; and determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first difference and the second difference.

[0012] In an exemplary embodiment of the present invention, the step of determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first difference and the second difference includes: obtaining a first difference sum corresponding to the first candidate read voltage level based on the first difference; obtaining a second difference sum corresponding to the second candidate read voltage level based on the second difference; in response to the first difference sum being less than the second difference sum, determining the first candidate read voltage level as the target read voltage level; and in response to the second difference sum being less than the first difference sum, determining the second candidate read voltage level as the target read voltage level.

[0013] Another exemplary embodiment of the present invention provides a memory storage device comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The rewritable non-volatile memory module comprises a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: send multiple first read instruction sequences, wherein the multiple first read instruction sequences are used to indicate the use of multiple read voltage levels to read data from a first physical unit among the multiple physical units; decode the data to obtain multiple error assessment parameters, wherein the multiple error assessment parameters respectively correspond to one of the multiple read voltage levels; determine a first vector distance parameter based on a first error assessment parameter among the multiple error assessment parameters, wherein the first error assessment parameter corresponds to a first read voltage level among the multiple read voltage levels; determine multiple candidate read voltage levels based on the first vector distance parameter and the first read voltage level; determine a target read voltage level based on one of the multiple candidate read voltage levels; and send a second read instruction sequence, wherein the second read instruction sequence is used to indicate the use of the target read voltage level to re-read the data from the first physical unit.

[0014] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit decoding the data to obtain the multiple error assessment parameters includes: performing a parity check operation on the data read using the first read voltage level to obtain a syndrome sum; and obtaining the first error assessment parameter based on the syndrome sum.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: compare the plurality of error assessment parameters; and determine one of the plurality of error assessment parameters as the first error assessment parameter according to a comparison result.

[0016] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit determining the first vector distance parameter according to the first error estimation parameter among the plurality of error estimation parameters includes: converting the first error estimation parameter into the first vector distance parameter according to a conversion function.

[0017] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit determining the multiple candidate read voltage levels based on the first vector distance parameter and the first read voltage level includes: determining a first coordinate point in a coordinate space based on the first read voltage level; obtaining multiple second coordinate points in the coordinate space based on the first coordinate point and the first vector distance parameter; and determining the multiple candidate read voltage levels based on the multiple second coordinate points.

[0018] In an exemplary embodiment of the present invention, the multiple candidate read voltage levels include a first candidate read voltage level and a second candidate read voltage level, and the operation of the memory control circuit unit determining the target read voltage level based on one of the multiple candidate read voltage levels includes: obtaining a first candidate vector distance parameter between the first candidate read voltage level and a second read voltage level among the multiple read voltage levels; obtaining a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level; and determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first candidate vector distance parameter and the second candidate vector distance parameter.

[0019] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first candidate vector distance parameter and the second candidate vector distance parameter includes: determining a second vector distance parameter based on a second error assessment parameter among the multiple error assessment parameters, wherein the second error assessment parameter corresponds to the second read voltage level; obtaining a first difference between the first candidate vector distance parameter and the second vector distance parameter; obtaining a second difference between the second candidate vector distance parameter and the second vector distance parameter; and determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first difference and the second difference.

[0020] In an example embodiment of the present disclosure, the operation of determining, by the memory control circuit unit, the one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first difference value and the second difference value includes: obtaining a first difference sum corresponding to the first candidate read voltage level according to the first difference value; obtaining a second difference sum corresponding to the second candidate read voltage level according to the second difference value; determining the first candidate read voltage level as the target read voltage level in response to the first difference sum being less than the second difference sum; and determining the second candidate read voltage level as the target read voltage level in response to the second difference sum being less than the first difference sum.

[0021] An example embodiment of the present disclosure further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, an error check and correction circuit, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory management circuit is connected to the host interface, the memory interface, and the error check and correction circuit. The memory management circuit is configured to: send a plurality of first read instruction sequences, wherein the plurality of first read instruction sequences are configured to instruct reading data from a first physical unit of the plurality of physical units using a plurality of read voltage levels; instruct the error check and correction circuit to decode the data to obtain a plurality of error evaluation parameters, wherein the plurality of error evaluation parameters respectively correspond to one of the plurality of read voltage levels; determine a first vector distance parameter according to a first error evaluation parameter of the plurality of error evaluation parameters, wherein the first error evaluation parameter corresponds to a first read voltage level of the plurality of read voltage levels; determine a plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level; determine a target read voltage level according to one of the plurality of candidate read voltage levels; and send a second read instruction sequence, wherein the second read instruction sequence is configured to instruct re-reading the data from the first physical unit using the target read voltage level.

[0022] In an example embodiment of the present disclosure, the operation of instructing, by the memory management circuit, the error check and correction circuit to decode the data to obtain the plurality of error evaluation parameters includes: instructing the error check and correction circuit to perform a parity check operation on data of the data that is read using the first read voltage level to obtain a syndrome sum; and obtaining the first error evaluation parameter according to the syndrome sum.

[0023] In an example embodiment of the present disclosure, the memory management circuit is further configured to compare the plurality of error evaluation parameters; and determine one of the plurality of error evaluation parameters as the first error evaluation parameter according to a comparison result.

[0024] In an example embodiment of the present disclosure, the memory management circuit is further configured to determine the first vector distance parameter according to the first error evaluation parameter of the plurality of error evaluation parameters.

[0025] In an example embodiment of the present disclosure, the memory management circuit is further configured to determine the plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level, including: determining a first coordinate point in a coordinate space according to the first read voltage level; obtaining a plurality of second coordinate points in the coordinate space according to the first coordinate point and the first vector distance parameter; and determining the plurality of candidate read voltage levels according to the plurality of second coordinate points.

[0026] In an example embodiment of the present disclosure, the plurality of candidate read voltage levels include a first candidate read voltage level and a second candidate read voltage level, and the memory management circuit is further configured to determine the target read voltage level according to one of the plurality of candidate read voltage levels, including: obtaining a first candidate vector distance parameter between the first candidate read voltage level and a second read voltage level of the plurality of read voltage levels; obtaining a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level; and determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter.

[0027] In an example embodiment of the present disclosure, the memory management circuit is further configured to determine one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter, including: determining a second vector distance parameter according to a second error evaluation parameter of the plurality of error evaluation parameters, wherein the second error evaluation parameter corresponds to the second read voltage level; obtaining a first difference value between the first candidate vector distance parameter and the second vector distance parameter; obtaining a second difference value between the second candidate vector distance parameter and the second vector distance parameter; and determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first difference value and the second difference value.

[0028] In an exemplary embodiment of the present invention, the operation of the memory management circuit determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level based on the first difference and the second difference includes: obtaining a first difference sum corresponding to the first candidate read voltage level based on the first difference; obtaining a second difference sum corresponding to the second candidate read voltage level based on the second difference; in response to the first difference sum being less than the second difference sum, determining the first candidate read voltage level as the target read voltage level; and in response to the second difference sum being less than the first difference sum, determining the second candidate read voltage level as the target read voltage level.

[0029] Based on the above, after reading data from the first physical cell using multiple read voltage levels, the data can be decoded to obtain multiple error estimation parameters corresponding to these read voltage levels. Based on a first error estimation parameter among these error estimation parameters, a first vector distance parameter corresponding to the first read voltage level can be determined. Based on the first vector distance parameter and the first read voltage level, multiple candidate read voltage levels can be determined. Subsequently, a target read voltage level can be determined based on one of these candidate read voltage levels. This effectively improves the efficiency of read voltage level calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0033] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0034] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0035] Figure 6 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;

[0036] Figure 7is a schematic diagram showing a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention;

[0037] Figure 8 is a schematic diagram showing a threshold voltage distribution of a memory cell after degradation according to an exemplary embodiment of the present invention;

[0038] Figure 9 is a schematic diagram of a parity check operation according to an exemplary embodiment of the present invention;

[0039] Figure 10 is a schematic diagram showing a first coordinate point and a plurality of second coordinate points according to an exemplary embodiment of the present invention;

[0040] Figures 11A to 11C is a schematic diagram of multiple candidate vector distances between multiple candidate read voltage levels and multiple second read voltage levels according to an exemplary embodiment of the present invention;

[0041] Figure 12 is a schematic diagram showing a first coordinate point and a plurality of second coordinate points according to an exemplary embodiment of the present invention;

[0042] Figure 13A and Figure 13B is a schematic diagram of multiple candidate vector distances between multiple candidate read voltage levels and multiple second read voltage levels according to an exemplary embodiment of the present invention;

[0043] Figure 14 is a flow chart of a read voltage calibration method according to an exemplary embodiment of the present invention;

[0044] Figure 15 FIG. 4 is a flow chart of a read voltage calibration method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0046] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to the memory storage device or read data from the memory storage device.

[0047] Figure 1FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be connected to a system bus 110 .

[0049] In one exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be connected to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0050] In one exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless method.

[0051] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a Wi-Fi (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210, via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0052] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 The memory storage device 30 and the host system 31 are connected.

[0053] Figure 3 FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0055] Figure 4is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention.

[0056] Referring to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0057] The connection interface unit 41 is used to connect the memory storage device 10 to a host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 41 can also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that includes the memory control circuit unit 42.

[0058] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions of the host system 11.

[0059] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), other flash memory modules, or other memory modules having the same characteristics.

[0060] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer can be changed, and thus the threshold voltage of the memory cell can be changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable non-volatile memory module 43 has a plurality of storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus one or more bits stored in the memory cell can be obtained.

[0061] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If a memory cell can store more than two bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0062] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains the minimum number of memory cells to be erased together. For example, a physical erase unit is a physical block.

[0063] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0064] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read, and erase operations, etc. when the memory storage device 10 is in operation. The operation of the memory management circuit 51 is equivalent to the operation of the memory control circuit unit 42.

[0065] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read, and erase operations, etc.

[0066] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code form in a specific area (e.g., a system area in the memory module that is dedicated for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read, and erase operations, etc.

[0067] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0068] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0069] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing a garbage collection operation). These command sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0070] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0071] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it also reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0072] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10 .

[0073] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0074] In one exemplary embodiment, the ECC circuit 54 supports low-density parity-check (LDPC) codes. For example, the ECC circuit 54 may utilize LDPC codes for encoding and decoding. However, in another exemplary embodiment, the ECC circuit 54 may also support BCH codes, convolutional codes, turbo codes, and the like, without limitation to the present invention.

[0075] In low-density parity-check codes, a parity-check matrix is ​​used to define valid codewords. Hereinafter, the parity-check matrix is ​​labeled as matrix H, and the codeword is labeled as CW. According to the following equation (1), if the product of matrix H and codeword CW is a zero vector, it means that codeword CW is a valid codeword. In equation (1), the operator represents modulo 2 matrix multiplication. In other words, the null space of matrix H contains all valid codewords. However, the present invention is not limited to the content of codeword CW. For example, codeword CW may also include an error-correcting code or an error-checking code generated by any algorithm.

[0076]

[0077] In equation (1), the dimension of the matrix H is k-by-n, and the dimension of the codeword CW is 1-by-n. k and n are positive integers. The codeword CW includes information bits and parity bits. For example, the codeword CW can be expressed as [MP], where the vector M is composed of information bits and the vector P is composed of parity bits. The dimension of the vector M is 1-by-(nk), and the dimension of the vector P is 1-by-k. Hereinafter, the information bits and parity bits are collectively referred to as data bits. In other words, there are n data bits in the codeword CW. In the codeword CW, the length of the information bits is (nk) bits, the length of the parity bits is k bits, and the code rate of the codeword CW is (nk) / n.

[0078] Generally, a generation matrix (hereinafter referred to as G) is used during encoding so that the following equation (2) is satisfied for any vector M. For example, the dimension of the generation matrix G is (nk)-by-n.

[0079]

[0080] The codeword CW generated by equation (2) is a valid codeword. Therefore, equation (2) can be substituted into equation (1), thereby obtaining the following equation (3).

[0081]

[0082] Since the vector M can be any vector, the following equation (4) must be satisfied. That is, after determining the matrix H (i.e., the parity check matrix), the corresponding generation matrix G can also be determined.

[0083]

[0084] When decoding a codeword CW, a parity check operation is first performed on the data bits in the codeword CW. For example, the matrix H is multiplied by the codeword CW to generate a vector (hereinafter labeled S, as shown in the following equation (5)). Vector S is also called a syndrome vector. If vector S is a zero vector, the codeword CW can be directly output. If vector S is not a zero vector, it indicates that the codeword CW is not a valid codeword.

[0085]

[0086] The dimension of vector S is k by -1. Each element in vector S is also called a syndrome. If the codeword CW is not a valid codeword, the error checking and correction circuit 54 may attempt to correct errors (i.e., erroneous bits) in the codeword CW through a decoding operation.

[0087] Figure 6 FIG. 4 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention.

[0088] Please refer to Figure 6, the dimension of parity check matrix 600 is k-by-n. For example, k is 8 and n is 9. However, the present invention is not limited to the numerical values ​​of positive integers k and n. Each row of parity check matrix 600 can represent a constraint. Taking the first row of parity check matrix 600 as an example, if a codeword is a valid codeword, then after adding the 3rd, 5th, 8th and 9th bits in this codeword modulo 2 (mod 2), a bit "0" will be obtained. Those with ordinary knowledge in this field should be able to understand how to use parity check matrix 600 for encoding and decoding, so this will not be repeated here. In addition, parity check matrix 600 is merely an example matrix and is not intended to limit the present invention.

[0089] When the memory management circuit 51 stores data (comprising multiple bits) in the rewritable non-volatile memory module 43, the error checking and correction circuit 54 generates k parity bits for each (nk) bit (i.e., information bit) in the data. The memory management circuit 51 then writes these n bits (i.e., data bits) as a codeword into the rewritable non-volatile memory module 43.

[0090] Figure 7 FIG. 1 is a schematic diagram showing a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention.

[0091] Please refer to Figure 7 , the horizontal axis represents the critical voltage of the memory cell, and the vertical axis represents the number of memory cells. For example, Figure 7 It may represent the threshold voltage of each memory cell in a physical unit (also referred to as a first physical unit) in a healthy state. For example, the first physical unit may include one or more physical programming units.

[0092] In one exemplary embodiment, it is assumed that the rewritable non-volatile memory module 43 includes an MLC NAND flash memory module. Therefore, a memory cell in the first physical unit can have four states 701-704. For example, states 701-704 correspond to bits "11", "10", "01" and "00", respectively. If the threshold voltage of a memory cell belongs to state 701, then the memory cell stores bit "11". If the threshold voltage of a memory cell belongs to state 702, then the memory cell stores bit "10". If the threshold voltage of a memory cell belongs to state 703, then the memory cell stores bit "01". Alternatively, if the threshold voltage of a memory cell belongs to state 704, then the memory cell stores bit "00". It should be noted that in other exemplary embodiments, the total number of states 701-704 and the bit value corresponding to each state can be adjusted according to practical needs, and the present invention is not limited thereto.

[0093] When data is to be read from the rewritable non-volatile memory module 43, the memory management circuit 51 may send a read instruction sequence to the rewritable non-volatile memory module 43. The read instruction sequence is used to instruct the rewritable non-volatile memory module 43 to use at least one read voltage level to read at least one memory cell in the first physical unit (also referred to as the first memory cell) to obtain the data stored in the first memory cell. For example, according to the read instruction sequence, the rewritable non-volatile memory module 43 may use Figure 7 The first memory cell is read using the read voltage levels RV(1), RV(2), and RV(2)′ in the memory management circuit 51. Based on whether the read memory cell is turned on by these read voltage levels, the memory management circuit 51 can obtain the bit data currently stored in the memory cell. However, as the usage time and / or usage frequency of the rewritable non-volatile memory module 43 increases, at least some of the memory cells in the rewritable non-volatile memory module 43 may degrade.

[0094] Figure 8 FIG. 1 is a schematic diagram showing a threshold voltage distribution of a memory cell after degradation according to an exemplary embodiment of the present invention.

[0095] Please refer to Figure 8 , states 711 to 714 may be used to represent states 701 to 704 after the decay occurs. For example, after the decay occurs, the threshold voltage distributions corresponding to states 711 to 714 may shift and / or overlap with each other. At this time, if uncorrected read voltage levels (e.g., read voltage levels RV(1), RV(2), and RV(2)') are continuously used to read data from the first memory cell, the read data may contain a large number of error bits. In one exemplary embodiment, the error checking and correction circuit 54 may decode the read data to attempt to correct the errors in the data. In addition, the error checking and correction circuit 54 may perform a parity check operation on the read data to confirm whether the read data contains error bits.

[0096] Figure 9 FIG. 1 is a schematic diagram illustrating a parity check operation according to an exemplary embodiment of the present invention.

[0097] Please refer to Figure 9, assuming that the data read from the first storage unit includes codeword 901. In the parity check operation, according to equation (5), matrix 900 (i.e., parity check matrix) can be multiplied with codeword 901 to generate vector 902 (i.e., vector S). Vector 902 is also called a check vector. Each bit in codeword 901 corresponds to at least one element (i.e., syndrome) in vector 902. For example, bit V0 in codeword 901 (corresponding to the first row in parity check matrix 900) corresponds to syndromes S1, S4, and S7; bit V1 (corresponding to the second row in parity check matrix 900) corresponds to syndromes S2, S3, and S6; and so on, bit V8 (corresponding to the ninth row in parity check matrix 900) corresponds to syndromes S0, S4, and S5.

[0098] If bit V0 is an error bit, then at least one of syndromes S1, S4, and S7 may be "1." If bit V1 is an error bit, then at least one of syndromes S2, S3, and S6 may be "1." Similarly, if bit V8 is an error bit, then at least one of syndromes S0, S4, and S5 may be "1."

[0099] In other words, if all syndromes S0-S7 are "0," codeword 901 likely contains no error bits, and thus error checking and correction circuit 54 can directly output codeword 901. However, if codeword 901 contains at least one error bit, at least one of syndromes S0-S7 may be "1," and error checking and correction circuit 54 can correct the error by performing a decoding operation on codeword 901. Furthermore, the total number of syndromes S0-S7 may be greater or less, and the present invention is not limited thereto.

[0100] In one exemplary embodiment, the memory management circuit 51 may instruct the ECC circuit 54 to decode data using either a hard decoding mode (also known as a hard bit decoding mode) or a soft decoding mode (also known as a soft bit decoding mode). In the hard decoding mode, when a decoding failure occurs, the memory management circuit 51 may change the read voltage level to re-read the data from the first physical cell (or first memory cell). For example, the memory management circuit 51 may query one or more retry tables to obtain adjustment parameters for the read voltage level. These adjustment parameters may be used to adjust the read voltage level. The memory management circuit 51 may re-read the data from the first physical cell (or first memory cell) using the adjusted read voltage level to attempt to reduce the number of error bits included in the data read from the first physical cell (or first memory cell). However, if the number of error bits in the re-read data is still excessive (e.g., exceeds the upper limit of the number of error bits that the ECC circuit 54 can correct), the ECC circuit 54 may still be unable to successfully decode the data.

[0101] In one exemplary embodiment, in hard decoding mode, if decoding fails or the number of data rereads exceeds a predetermined number (or the reread table is exhausted), the memory management circuit 51 may instruct the error checking and correction circuit 54 to enter soft decoding mode. In soft decoding mode, more information (also known as soft information or soft bits) is available to assist in decoding the read data, and the error checking and correction circuit 54 can use this information to decode the read data in an attempt to increase the decoding success rate. However, compared to hard decoding mode, the time required to decode data in soft decoding mode is significantly increased. Therefore, how to improve the decoding success rate of the error checking and correction circuit 54 before entering soft decoding mode (i.e., in hard decoding mode) has been a topic of research for those skilled in the art.

[0102] In one exemplary embodiment, in hard decoding mode, the memory management circuit 51 may issue multiple read command sequences (also referred to as first read command sequences). For example, these first read command sequences may be sequentially issued to the rewritable non-volatile memory module 43. These first read command sequences may be used to instruct the rewritable non-volatile memory module 43 to sequentially use multiple read voltage levels to read data from the first physical cell. For ease of description, the data instructed to be read by the first read command sequences will be collectively referred to as first data. Furthermore, the memory management circuit 51 may instruct the error checking and correction circuit 54 to decode the read data (including performing a parity check operation).

[0103] In one exemplary embodiment, in hard decoding mode, the memory management circuit 51 may send one of the plurality of first read command sequences to instruct the rewritable non-volatile memory module 43 to read data from the first physical cell using one of the plurality of read voltage levels. The error checking and correction circuit 54 may decode the read data. If the decoding is successful, the error checking and correction circuit 54 may output the successfully decoded data. If the decoding fails (i.e., is unsuccessful), the memory management circuit 51 may send another of the plurality of first read command sequences to instruct the rewritable non-volatile memory module 43 to read data from the first physical cell using another of the plurality of read voltage levels. The error checking and correction circuit 54 may then decode the read data again. For example, these read voltage levels may be determined based on the reread table.

[0104] In one exemplary embodiment, during decoding of the first data, the memory management circuit 51 may obtain and record a plurality of error assessment parameters. Each of these error assessment parameters corresponds to one of the plurality of read voltage levels. For example, each of these error assessment parameters may reflect an error status of data read using one of the plurality of read voltage levels.

[0105] Taking, for example, an error assessment parameter (also referred to as a first error assessment parameter) corresponding to a certain read voltage level (also referred to as a first read voltage level) among these error assessment parameters, the first error assessment parameter may reflect the error status of data read from the first physical cell using the first read voltage level in a previously executed hard decoding operation. For example, the first error assessment parameter may be positively correlated with the total number of error bits included in the data read from the first physical cell using the first read voltage level. That is, a larger value of the first error assessment parameter indicates a greater total number of error bits included in the data read from the first physical cell using the first read voltage level. However, in one exemplary embodiment, the first error assessment parameter may also be negatively correlated with the total number of error bits included in the data read from the first physical cell using the first read voltage level. Alternatively, in one exemplary embodiment, the first error assessment parameter may also reflect the error status of data read from the first physical cell using the first read voltage level in a previously executed hard decoding operation using other methods, and the present invention is not limited thereto.

[0106] In an exemplary embodiment, the memory management circuit 51 may instruct the error checking and correction circuit 54 to perform a parity check operation on the data read using the first read voltage level in the first data to obtain a syndrome sum. Figure 9 For example, assuming codeword 901 includes data read from a first physical unit using a first read voltage level, the memory management circuit 51 may accumulate the syndromes S0-S7 in the check vector 902 to obtain a syndrome sum. Alternatively, from another perspective, the syndrome sum may reflect the sum of the syndromes S0-S7 in the check vector 902. The memory management circuit 51 may record a first error assessment parameter based on the syndrome sum. For example, the memory management circuit 51 may directly set the syndrome sum as the first error assessment parameter. For example, assuming the syndrome sum is 500, the memory management circuit 51 may record the first error assessment parameter as 500. Alternatively, the memory management circuit 51 may perform a logical operation on the syndrome sum to obtain the first error assessment parameter, although this is not a limitation of the present invention. Similarly, the memory management circuit 51 may record the error assessment parameters corresponding to each of the multiple read voltage levels.

[0107] In one exemplary embodiment, the memory management circuit 51 may compare the multiple error assessment parameters. Based on the comparison result, the memory management circuit 51 may determine one of the multiple error assessment parameters as the first error assessment parameter. For example, based on the comparison result, the memory management circuit 51 may determine the error assessment parameter with the smallest value among the multiple error assessment parameters as the first error assessment parameter. Alternatively, in one exemplary embodiment, based on the comparison result, the memory management circuit 51 may determine the error assessment parameter among the multiple error assessment parameters that meets a specific condition as the first error assessment parameter, although the present invention is not limited thereto.

[0108] In one exemplary embodiment, the memory management circuit 51 may determine a vector distance parameter (also referred to as a first vector distance parameter) based on the first error assessment parameter. The first vector distance parameter corresponds to the first read voltage level. For example, the memory management circuit 51 may convert the first error assessment parameter into the first vector distance parameter according to the conversion function (2.1).

[0109] f(s)=d(2.1)

[0110] In conversion function (2.1), parameter s represents the error estimation parameter, and d represents the vector distance parameter. After substituting the first error estimation parameter (i.e., parameter s) into conversion function (2.1), the first vector distance parameter (i.e., parameter d) can be obtained based on the output of conversion function (2.1). Furthermore, in one exemplary embodiment, conversion function (2.1) can be replaced by a data table (or conversion table). Thus, memory management circuit 51 can convert the error estimation parameter into the vector distance parameter by table lookup or calculation.

[0111] In one exemplary embodiment, the memory management circuit 51 may determine a plurality of read voltage levels (also referred to as candidate read voltage levels) based on a first vector distance parameter and the first read voltage level. For example, the distance (also referred to as the vector distance) between the candidate read voltage levels and the first read voltage level may be related to the first vector distance parameter. For example, the vector distance between the candidate read voltage levels and the first read voltage level may be positively correlated with the first vector distance parameter.

[0112] In one exemplary embodiment, the first vector distance parameter may be used to determine, control, limit, or restrict the vector distances between the first read voltage level and each of the plurality of candidate read voltage levels. The memory management circuit 51 may then determine a read voltage level (also referred to as a target read voltage level) based on one of the plurality of candidate read voltage levels. For example, the target read voltage level may include a calibrated read voltage level.

[0113] In one exemplary embodiment, after determining the target read voltage level, the memory management circuit 51 may again send a read command sequence (also referred to as a second read command sequence) to the rewritable non-volatile memory module 43. This second read command sequence may be used to instruct the rewritable non-volatile memory module 43 to read data (also referred to as second data) from the first physical cell using the target read voltage level. The error checking and correction circuit 54 may then decode the second data in hard decoding mode.

[0114] In one exemplary embodiment, the total number of error bits contained in the second data read from the first physical cell using the target read voltage level can be effectively reduced compared to the first data read from the first physical cell using multiple uncorrected read voltage levels. In one exemplary embodiment, the decoding success rate of the second data by the error checking and correction circuit 54 in the hard decoding mode can also be effectively improved compared to the first data. In one exemplary embodiment, before entering the soft decoding mode, the data read from the first physical cell (i.e., the second data) can be decoded more quickly (in the hard decoding mode), thereby improving the decoding efficiency of the error checking and correction circuit 54.

[0115] In one exemplary embodiment, the memory management circuit 51 may determine a coordinate point (also referred to as a first coordinate point) in a coordinate space based on the first read voltage level. The dimensionality of this coordinate space is not limited. The memory management circuit 51 may obtain multiple coordinate points (also referred to as second coordinate points) in the coordinate space based on the first coordinate point and the first vector distance parameter. The memory management circuit 51 may determine the multiple candidate read voltage levels based on these second coordinate points. For example, the coordinate position of the first coordinate point in the coordinate space may reflect or correspond to the first read voltage level, and the coordinate position of each second coordinate point in the coordinate space may reflect or correspond to one of the multiple candidate read voltage levels.

[0116] In one exemplary embodiment, the first vector distance parameter reflects or corresponds to a distance in the coordinate space (also referred to as the first vector distance). The memory management circuit 51 may determine a second coordinate point in the coordinate space based on the first coordinate point and the first vector distance. In particular, the vector distance between the second coordinate point and the first coordinate point in the coordinate space (also referred to as the second vector distance) may be equal to, greater than, or less than the first vector distance.

[0117] In one exemplary embodiment, the memory management circuit 51 may determine the second vector distance based on the first vector distance parameter (or the first vector distance). For example, the memory management circuit 51 may directly set the first vector distance as the second vector distance. Alternatively, the memory management circuit 51 may perform a logical operation on the first vector distance parameter to obtain the second vector distance. In one exemplary embodiment, the memory management circuit 51 may determine a second coordinate point in the coordinate space based on the first coordinate point and the second vector distance.

[0118] Figure 10 FIG. 1 is a schematic diagram showing a first coordinate point and a plurality of second coordinate points according to an exemplary embodiment of the present invention.

[0119] Please refer to Figure 10 , assuming that parameter S(0) represents an error assessment parameter corresponding to the first read voltage level (i.e., a first error assessment parameter), and parameter d(0) represents a first vector distance parameter. For example, the memory management circuit 51 may obtain parameter d(0) based on parameter S(0). For example, parameter S(0) may be "500" and parameter d(0) may be "4," but the present invention is not limited thereto.

[0120] In one exemplary embodiment, the memory management circuit 51 may determine a coordinate point CP(0) (i.e., a first coordinate point) in the coordinate space based on the first read voltage level. The memory management circuit 51 may determine a plurality of coordinate points SP(1)-SP(8) (i.e., a second coordinate point) in the coordinate space based on the coordinate point CP(0) and the parameter d(0). It should be noted that the total number of coordinate points SP(1)-SP(8) may be greater or less.

[0121] In one exemplary embodiment, the distance between each of the coordinate points SP(1) to SP(8) and the coordinate point CP(0) is the same. For example, the distance between each of the coordinate points SP(1) to SP(8) and the coordinate point CP(0) is the vector distance (i.e., the first vector distance) corresponding to the parameter d(0). From another perspective, Figure 10 In the exemplary embodiment, coordinate point CP(0) is used as the center of circle 1010 and the vector distance corresponding to parameter d(0) is used as the radius of circle 1010. Then, coordinate points SP(1) to SP(8) are all located on the circumference of circle 1010. In particular, each of these coordinate points SP(1) to SP(8) corresponds to a candidate read voltage level.

[0122] In one exemplary embodiment, the position of coordinate point CP(0) in the coordinate space may reflect at least one voltage value of the first read voltage level. Similarly, the positions and distribution of coordinate points SP(1)-SP(8) in the coordinate space may reflect the voltage values ​​of multiple candidate read voltage levels and the distribution of these voltage values.

[0123] In an example embodiment, the aforementioned first read voltage level, the candidate read voltage levels, or the remaining read voltage levels can each comprise a set of voltage values. For example, Figure 7 For example, a set of voltage values can include voltage values of read voltage levels RV(1), RV(2), and RV(2)' (or voltage values of read voltage levels RV(2) and RV(2)'). Assuming that a set of voltage values includes n voltage values V(1) ~ V(n), the coordinates of any coordinate point in the coordinate space can be represented as (V(1), V(2), …, V(n)). Further, assuming that the coordinates of two coordinate points in the coordinate space are (Vi(1), Vi(2), …, Vi(n)) and (Vj(1), Vj(2), …, Vj(n)) respectively, the distance d(ij) between the two coordinate points can be obtained by the following equation (3.1).

[0124]

[0125] Therefore, in an example embodiment of the present application, Figure 10 the positions and / or distributions of coordinate points CP(0) and SP(1) ~ SP(8) in the coordinate space can reflect the voltage relative relationships between the read voltage levels to which coordinate points CP(0) and SP(1) ~ SP(8) correspond respectively.

[0126] In an example embodiment, the memory management circuit 51 can obtain a vector distance parameter (also referred to as a first candidate vector distance parameter) between a candidate read voltage level (also referred to as a first candidate read voltage level) of the plurality of candidate read voltage levels and another read voltage level (also referred to as a second read voltage level) of the plurality of read voltage levels. The second read voltage level is different from the first read voltage level. On the other hand, the memory management circuit 51 can obtain a vector distance parameter (also referred to as a second candidate vector distance parameter) between another candidate read voltage level (also referred to as a second candidate read voltage level) of the plurality of candidate read voltage levels and the second read voltage level. The memory management circuit 51 can determine one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter.

[0127] In one exemplary embodiment, the memory management circuit 51 may determine a vector distance parameter (also referred to as a second vector distance parameter) based on the error estimation parameter corresponding to the second read voltage level among the plurality of error estimation parameters (also referred to as the second error estimation parameter). For example, based on a previous comparison result of the plurality of error estimation parameters, the memory management circuit 51 may determine at least one error estimation parameter among the plurality of error estimation parameters that is not the smallest in value as the second error estimation parameter. The memory management circuit 51 may then convert one or more second error estimation parameters into corresponding second vector distance parameters according to the conversion function (2.1).

[0128] In one exemplary embodiment, the memory management circuit 51 may obtain a difference between the first candidate vector distance parameter and the second vector distance parameter (also referred to as a first difference). Furthermore, the memory management circuit 51 may obtain a difference between the second candidate vector distance parameter and the second vector distance parameter (also referred to as a second difference). Based on the first difference and the second difference, the memory management circuit 51 may determine one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level.

[0129] In one exemplary embodiment, the memory management circuit 51 may update a difference sum corresponding to the first candidate read voltage level (also referred to as the first difference sum) based on the first difference. Alternatively, the memory management circuit 51 may update a difference sum corresponding to the second candidate read voltage level (also referred to as the second difference sum) based on the second difference. The memory management circuit 51 may determine whether to determine the first candidate read voltage level or the second candidate read voltage level as the target read voltage level based on the numerical magnitude relationship between the first difference sum and the second difference sum. For example, in response to the first difference sum being less than the second difference sum, the memory management circuit 51 may determine the first candidate read voltage level as the target read voltage level. Alternatively, in response to the second difference sum being less than the first difference sum, the memory management circuit 51 may determine the second candidate read voltage level as the target read voltage level.

[0130] Figures 11A to 11C FIG is a schematic diagram of multiple candidate vector distances between multiple candidate read voltage levels and multiple second read voltage levels according to an exemplary embodiment of the present invention. Figure 10 The coordinate points SP(1) to SP(3) in FIG. 1 are used as examples for explanation.

[0131] Please refer to Figures 11A to 11C, assuming that the coordinate points CP(0) to CP(3) correspond to a read voltage level respectively. In particular, the parameter S(0) (i.e., the first error assessment parameter) corresponding to the read voltage level (i.e., the first read voltage level) corresponding to the coordinate point CP(0) (i.e., the first coordinate point) is smaller than the parameters S(1) to S(3) (i.e., the second error assessment parameter) corresponding to the multiple read voltage levels (i.e., the second read voltage level) corresponding to the coordinate points CP(1) to CP(3) (i.e., the second coordinate point). Parameters S(1) to S(3) are all greater than parameter S(0). In addition, the memory management circuit 51 can convert the parameters S(0) to S(3) into parameters d(0) to d(3) respectively according to the aforementioned conversion function (2.1). Among them, parameter d(0) can be regarded as the first vector distance parameter, and parameters d(1) to d(3) can be regarded as the second vector distance parameters. For example, assuming that parameters S(0) to S(3) are "500", "700", "750" and "800" respectively, parameters d(0) to d(3) can be "4", "6", "8" and "10" respectively.

[0132] exist Figure 11A In the exemplary embodiment, the memory management circuit 51 can obtain parameters d(11) to d(13) (i.e., candidate vector distance parameters) according to the aforementioned equation (3.1). Parameter d(11) reflects the vector distance between coordinate point SP(1) and coordinate point CP(1). Parameter d(12) reflects the vector distance between coordinate point SP(1) and coordinate point CP(2). Parameter d(13) reflects the vector distance between coordinate point SP(1) and coordinate point CP(3). In addition, the memory management circuit 51 can obtain the difference Δ(11) between parameter d(11) and parameter d(1), the difference Δ(12) between parameter d(12) and parameter d(2), and the difference Δ(13) between parameter d(13) and parameter d(3). For example, Δ(11) = |d(11) - d(1) |, Δ(12) = |d(12) - d(2) |, and Δ(13) = |d(13) - d(3) |. The memory management circuit 51 can then obtain the difference sum ΔSUM(1) corresponding to the coordinate point SP(1) based on the difference values ​​Δ(11) to Δ(13). For example, ΔSUM(1) = Δ(11) + Δ(12) + Δ(13).

[0133] exist Figure 11BIn the exemplary embodiment, the memory management circuit 51 can obtain parameters d(21) to d(23) according to the aforementioned equation (3.1). Parameter d(21) reflects the vector distance between coordinate point SP(2) and coordinate point CP(1). Parameter d(22) reflects the vector distance between coordinate point SP(2) and coordinate point CP(2). Parameter d(23) reflects the vector distance between coordinate point SP(2) and coordinate point CP(3). In addition, the memory management circuit 51 can obtain the difference Δ(21) between parameter d(21) and parameter d(1), the difference Δ(22) between parameter d(2) and parameter d(2), and the difference Δ(23) between parameter d(23) and parameter d(3). For example, Δ(21) = |d(21) - d(1) |, Δ(22) = |d(22) - d(2) |, and Δ(23) = |d(23) - d(3) |. The memory management circuit 51 can then obtain the difference sum ΔSUM(2) corresponding to the coordinate point SP(2) based on the difference values ​​Δ(21) to Δ(23). For example, ΔSUM(2) = Δ(21) + Δ(22) + Δ(23).

[0134] exist Figure 11C In the exemplary embodiment, the memory management circuit 51 can obtain parameters d(31) to d(33) according to the aforementioned equation (3.1). Parameter d(31) reflects the vector distance between coordinate point SP(3) and coordinate point CP(1). Parameter d(32) reflects the vector distance between coordinate point SP(3) and coordinate point CP(2). Parameter d(33) reflects the vector distance between coordinate point SP(3) and coordinate point CP(3). In addition, the memory management circuit 51 can obtain the difference Δ(31) between parameter d(31) and parameter d(1), the difference Δ(32) between parameter d(32) and parameter d(2), and the difference Δ(33) between parameter d(33) and parameter d(3). For example, Δ(31) = |d(31) - d(1) |, Δ(32) = |d(32) - d(2) |, and Δ(33) = |d(33) - d(3) |. The memory management circuit 51 can then obtain the difference sum ΔSUM(3) corresponding to the coordinate point SP(3) based on the difference values ​​Δ(31) to Δ(33). For example, ΔSUM(3) = Δ(31) + Δ(32) + Δ(33).

[0135] In one exemplary embodiment, the memory management circuit 51 may determine the candidate read voltage level corresponding to one of the coordinate points SP(1)-SP(3) as the target read voltage level based on the difference sums ΔSUM(1)-ΔSUM(3). For example, the memory management circuit 51 may compare the difference sums ΔSUM(1)-ΔSUM(3). If the comparison result indicates that the difference sum ΔSUM(1) is less than the difference sums ΔSUM(2) and ΔSUM(3), the memory management circuit 51 may determine the candidate read voltage level corresponding to the coordinate point SP(1) as the target read voltage level. If the comparison result indicates that the total difference ΔSUM(2) is less than the total difference ΔSUM(1) and ΔSUM(3), the memory management circuit 51 may determine the candidate read voltage level corresponding to the coordinate point SP(2) as the target read voltage level. Alternatively, if the comparison result indicates that the total difference ΔSUM(3) is less than the total difference ΔSUM(1) and ΔSUM(2), the memory management circuit 51 may determine the candidate read voltage level corresponding to the coordinate point SP(3) as the target read voltage level.

[0136] It should be noted that in Figures 10 to 11C In the exemplary embodiment, it is assumed that the vector distance between each second coordinate point (e.g., coordinate points SP(1) to SP(8)) and the first coordinate point (e.g., coordinate point CP(0)) is the same. However, in an exemplary embodiment, at least some of the second coordinate points may have different vector distances from the first coordinate point.

[0137] Figure 12 FIG. 1 is a schematic diagram showing a first coordinate point and a plurality of second coordinate points according to an exemplary embodiment of the present invention.

[0138] Please refer to Figure 12 , assuming that the coordinate point CP(0) is the first coordinate point, and the coordinate points SP(1) to SP(5) belong to the second coordinate point. However, compared to Figure 10 In the exemplary embodiment of Figure 12 In the exemplary embodiment, coordinate points SP(4) and SP(5) may not be located on the circumference of circle 1010. For example, the vector distance between coordinate point SP(4) and coordinate point CP(0) may be greater than the vector distances between coordinate points SP(1) to SP(3) and coordinate point CP(0). The vector distance between coordinate point SP(5) and coordinate point CP(0) may be less than the vector distances between coordinate points SP(1) to SP(3) and coordinate point CP(0).

[0139] Figure 13A and Figure 13BFIG is a schematic diagram of multiple candidate vector distances between multiple candidate read voltage levels and multiple second read voltage levels according to an exemplary embodiment of the present invention. Figure 12 The coordinate points SP(4) and SP(5) in FIG are used as examples for explanation.

[0140] Please refer to Figure 13A and Figure 13B , compared to Figures 11A to 11C ,exist Figure 13A In the exemplary embodiment, the memory management circuit 51 can obtain parameters d(40) to d(43) (i.e., candidate vector distance parameters) according to the aforementioned equation (3.1). Parameter d(40) reflects the vector distance between coordinate point SP(4) and coordinate point CP(0). Parameter d(41) reflects the vector distance between coordinate point SP(4) and coordinate point CP(1). Parameter d(42) reflects the vector distance between coordinate point SP(4) and coordinate point CP(2). Parameter d(43) reflects the vector distance between coordinate point SP(4) and coordinate point CP(3). In addition, the memory management circuit 51 can obtain the difference Δ(40) between parameter d(40) and parameter d(0), the difference Δ(41) between parameter d(41) and parameter d(1), the difference Δ(42) between parameter d(42) and parameter d(2), and the difference Δ(43) between parameter d(43) and parameter d(3). For example, Δ(40) = |d(40) - d(0) |, Δ(41) = |d(41) - d(1) |, Δ(42) = |d(42) - d(2) |, and Δ(43) = |d(43) - d(3) |. The memory management circuit 51 can then obtain the difference sum ΔSUM(4) corresponding to the coordinate point SP(4) based on the difference values ​​Δ(40) to Δ(43). For example, ΔSUM(4) = Δ(40) + Δ(41) + Δ(42) + Δ(43).

[0141] exist Figure 13BIn the exemplary embodiment, the memory management circuit 51 can obtain parameters d(50) to d(53) (i.e., candidate vector distance parameters) according to the aforementioned equation (3.1). Parameter d(50) reflects the vector distance between coordinate point SP(5) and coordinate point CP(0). Parameter d(51) reflects the vector distance between coordinate point SP(5) and coordinate point CP(1). Parameter d(52) reflects the vector distance between coordinate point SP(5) and coordinate point CP(2). Parameter d(53) reflects the vector distance between coordinate point SP(5) and coordinate point CP(3). In addition, the memory management circuit 51 can obtain the difference Δ(50) between parameter d(50) and parameter d(0), the difference Δ(51) between parameter d(51) and parameter d(1), the difference Δ(52) between parameter d(52) and parameter d(2), and the difference Δ(53) between parameter d(53) and parameter d(3). For example, Δ(50) = |d(50) - d(0) |, Δ(51) = |d(51) - d(1) |, Δ(52) = |d(52) - d(2) |, and Δ(53) = |d(53) - d(3) |. Then, the memory management circuit 51 can obtain the difference sum ΔSUM(5) corresponding to the coordinate point SP(5) based on the difference values ​​Δ(50) to Δ(53). For example, ΔSUM(5) = Δ(50) + Δ(51) + Δ(52) + Δ(53). Then, the memory management circuit 51 can determine the target read voltage level based on the minimum of the difference sums ΔSUM(1) to ΔSUM(5). The relevant operation details have been described above and will not be repeated here.

[0142] It should be noted that the aforementioned exemplary embodiment uses only 3 to 5 second coordinate points and 3 second read voltage levels as examples to illustrate how to select the most appropriate coordinate point from a plurality of second coordinate points to determine the target read voltage level. However, the same or similar operations can be applied to scenarios where more or fewer second coordinate points and more or fewer second read voltage levels are used to determine the target read voltage level. The relevant operational details have been described above and will not be repeated here.

[0143] Figure 14 FIG. 4 is a flow chart of a read voltage calibration method according to an exemplary embodiment of the present invention.

[0144] Please refer to Figure 14In step S1401, data is read from a first physical cell using a plurality of read voltage levels. In step S1402, the data is decoded to obtain a plurality of error estimation parameters, wherein the plurality of error estimation parameters respectively correspond to one of the plurality of read voltage levels. In step S1403, a first vector distance parameter is determined based on a first error estimation parameter among the plurality of error estimation parameters, wherein the first error estimation parameter corresponds to a first read voltage level among the plurality of read voltage levels. In step S1404, a plurality of candidate read voltage levels are determined based on the first vector distance parameter and the first read voltage level. In step S1405, a target read voltage level is determined based on one of the plurality of candidate read voltage levels. In step S1406, data is re-read from the first physical cell using the target read voltage level.

[0145] Figure 15 FIG. 4 is a flow chart of a read voltage calibration method according to an exemplary embodiment of the present invention.

[0146] Please refer to Figure 15 In step S1501, a second vector distance parameter is determined according to a second error assessment parameter among the plurality of error assessment parameters, wherein the second error assessment parameter corresponds to a second read voltage level among the plurality of read voltage levels.

[0147] In step S1502, a first candidate vector distance parameter between a first candidate read voltage level and a second candidate read voltage level is obtained. In step S1503, a first difference between the first candidate vector distance parameter and the second vector distance parameter is obtained. In step S1504, a first difference sum corresponding to the first candidate read voltage level is updated based on the first difference.

[0148] On the other hand, in step S1505, a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level is obtained. In step S1506, a second difference between the second candidate vector distance parameter and the second vector distance parameter is obtained. In step S1507, a second difference sum corresponding to the second candidate read voltage level is updated based on the second difference.

[0149] In step S1508, a determination is made as to whether the first sum of the differences is less than the second sum of the differences. In response to the first sum of the differences being less than the second sum of the differences, in step S1509, the first candidate read voltage level is determined as the target read voltage level. Alternatively, in response to the first sum of the differences being not less than the second sum of the differences (or the second sum of the differences being less than the first sum of the differences), in step S1510, the second candidate read voltage level is determined as the target read voltage level.

[0150] However, Figure 14 and Figure 15 The steps in the method have been described in detail above, and thus will not be described again. It is worth noting that, Figure 14 The method of Figure 15 The steps in the method can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 14 The method of Figure 15 The method of

[0151] In summary, the read voltage correction method, the memory storage device, and the memory control circuit unit provided by the example embodiments of the present application can determine a plurality of candidate read voltage levels according to a plurality of error evaluation parameters corresponding to different read voltage levels. Then, a target read voltage level can be determined according to the distribution of coordinate points in the coordinate space corresponding to the candidate read voltage levels. In this way, the correction efficiency of the read voltage level can be effectively improved.

[0152] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A read voltage calibration method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the read voltage calibration method includes: reading data from a first physical cell of the plurality of physical cells using a plurality of read voltage levels; decoding the data to obtain a plurality of error assessment parameters, wherein the plurality of error assessment parameters respectively correspond to the plurality of read voltage levels; determining a first vector distance parameter based on a first error estimation parameter of the plurality of error estimation parameters, wherein the first error estimation parameter corresponds to a first read voltage level of the plurality of read voltage levels; determining a plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level; determining a target read voltage level according to one of the plurality of candidate read voltage levels; and The data is re-read from the first physical cell using the target read voltage level.

2. The read voltage correction method according to claim 1 , wherein the step of decoding the data to obtain the plurality of error assessment parameters comprises: performing a parity check operation on the data read using the first read voltage level to obtain a syndrome sum; as well as The first error assessment parameter is obtained according to the syndrome sum.

3. The read voltage calibration method according to claim 1 , further comprising: comparing the plurality of error assessment parameters; as well as One of the plurality of error assessment parameters is determined as the first error assessment parameter according to the comparison result.

4. The read voltage calibration method according to claim 1 , wherein the step of determining the first vector distance parameter according to the first error estimation parameter among the plurality of error estimation parameters comprises: The first error estimation parameter is converted into the first vector distance parameter according to a conversion function.

5. The read voltage calibration method according to claim 1 , wherein the step of determining the plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level comprises: determining a first coordinate point in a coordinate space according to the first read voltage level; Obtain a plurality of second coordinate points in the coordinate space according to a distance parameter between the first coordinate point and the first vector; as well as The plurality of candidate read voltage levels are determined according to the plurality of second coordinate points.

6. The read voltage calibration method according to claim 1 , wherein the plurality of candidate read voltage levels include a first candidate read voltage level and a second candidate read voltage level, and the step of determining the target read voltage level according to the one of the plurality of candidate read voltage levels comprises: obtaining a first candidate vector distance parameter between the first candidate read voltage level and a second read voltage level among the plurality of read voltage levels; obtaining a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level; as well as One of the first candidate read voltage level and the second candidate read voltage level is determined as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter.

7. The read voltage calibration method according to claim 6 , wherein the step of determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter comprises: determining a second vector distance parameter based on a second error assessment parameter among the plurality of error assessment parameters, wherein the second error assessment parameter corresponds to the second read voltage level; Obtaining a first difference between the first candidate vector distance parameter and the second vector distance parameter; obtaining a second difference between the second candidate vector distance parameter and the second vector distance parameter; as well as According to the first difference and the second difference, one of the first candidate read voltage level and the second candidate read voltage level is determined as the target read voltage level.

8. The read voltage calibration method according to claim 7 , wherein when both the number of the first difference values ​​and the number of the second difference values ​​are plural, the step of determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first difference value and the second difference value comprises: obtaining a first difference value sum corresponding to the first candidate read voltage level according to the first difference value; obtaining a second difference sum corresponding to the second candidate read voltage level according to the second difference; In response to the first difference sum being less than the second difference sum, determining the first candidate read voltage level as the target read voltage level; as well as In response to the second difference sum being smaller than the first difference sum, the second candidate read voltage level is determined as the target read voltage level.

9. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; as well as a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module; The memory control circuit unit is used to: sending a plurality of first read instruction sequences, wherein the plurality of first read instruction sequences are used to instruct to read data from a first physical cell among the plurality of physical cells using a plurality of read voltage levels; decoding the data to obtain a plurality of error assessment parameters, wherein the plurality of error assessment parameters respectively correspond to the plurality of read voltage levels; determining a first vector distance parameter based on a first error estimation parameter of the plurality of error estimation parameters, wherein the first error estimation parameter corresponds to a first read voltage level of the plurality of read voltage levels; determining a plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level; determining a target read voltage level according to one of the plurality of candidate read voltage levels; as well as A second read command sequence is sent, wherein the second read command sequence is used to instruct to re-read the data from the first physical cell using the target read voltage level.

10. The memory storage device according to claim 9, wherein the operation of the memory control circuit unit decoding the data to obtain the plurality of error assessment parameters comprises: performing a parity check operation on the data read using the first read voltage level to obtain a syndrome sum; as well as The first error assessment parameter is obtained according to the syndrome sum.

11. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: comparing the plurality of error assessment parameters; and One of the plurality of error assessment parameters is determined as the first error assessment parameter according to the comparison result.

12. The memory storage device according to claim 9, wherein the memory control circuit unit determines the first vector distance parameter according to the first error estimation parameter among the plurality of error estimation parameters, comprising: The first error estimation parameter is converted into the first vector distance parameter according to a conversion function.

13. The memory storage device according to claim 9 , wherein the memory control circuit unit determines the plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level, comprising: determining a first coordinate point in a coordinate space according to the first read voltage level; Obtain a plurality of second coordinate points in the coordinate space according to a distance parameter between the first coordinate point and the first vector; as well as The plurality of candidate read voltage levels are determined according to the plurality of second coordinate points.

14. The memory storage device according to claim 9 , wherein the plurality of candidate read voltage levels include a first candidate read voltage level and a second candidate read voltage level, and the memory control circuit unit determines the target read voltage level according to the one of the plurality of candidate read voltage levels, comprising: obtaining a first candidate vector distance parameter between the first candidate read voltage level and a second read voltage level among the plurality of read voltage levels; obtaining a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level; as well as One of the first candidate read voltage level and the second candidate read voltage level is determined as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter.

15. The memory storage device according to claim 14 , wherein the memory control circuit unit determines one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter, comprising: determining a second vector distance parameter based on a second error assessment parameter among the plurality of error assessment parameters, wherein the second error assessment parameter corresponds to the second read voltage level; Obtaining a first difference between the first candidate vector distance parameter and the second vector distance parameter; obtaining a second difference between the second candidate vector distance parameter and the second vector distance parameter; as well as According to the first difference and the second difference, one of the first candidate read voltage level and the second candidate read voltage level is determined as the target read voltage level.

16. The memory storage device according to claim 15 , wherein when both the number of the first difference values ​​and the number of the second difference values ​​are plural, the memory control circuit unit determines one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first difference value and the second difference value, comprising: obtaining a first difference value sum corresponding to the first candidate read voltage level according to the first difference value; obtaining a second difference sum corresponding to the second candidate read voltage level according to the second difference; In response to the first difference sum being less than the second difference sum, determining the first candidate read voltage level as the target read voltage level; as well as In response to the second difference sum being smaller than the first difference sum, the second candidate read voltage level is determined as the target read voltage level.

17. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, the memory control circuit unit includes: A host interface for connecting to a host system; A memory interface for connecting to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units; Error checking and correction circuitry; and a memory management circuit connected to the host interface, the memory interface, and the error checking and correction circuit, The memory management circuit is used to: sending a plurality of first read instruction sequences, wherein the plurality of first read instruction sequences are used to instruct to read data from a first physical cell among the plurality of physical cells using a plurality of read voltage levels; instructing the error checking and correction circuit to decode the data to obtain a plurality of error assessment parameters, wherein the plurality of error assessment parameters respectively correspond to the plurality of read voltage levels; determining a first vector distance parameter based on a first error estimation parameter of the plurality of error estimation parameters, wherein the first error estimation parameter corresponds to a first read voltage level of the plurality of read voltage levels; determining a plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level; determining a target read voltage level according to one of the plurality of candidate read voltage levels; and A second read command sequence is sent, wherein the second read command sequence is used to instruct to re-read the data from the first physical cell using the target read voltage level.

18. The memory control circuit unit according to claim 17, wherein the operation of the memory management circuit instructing the error checking and correction circuit to decode the data to obtain the plurality of error assessment parameters comprises: instructing the error checking and correction circuit to perform a parity check operation on the data read using the first read voltage level to obtain a syndrome sum; as well as The first error assessment parameter is obtained according to the syndrome sum.

19. The memory control circuit unit according to claim 17, wherein the memory management circuit is further configured to: comparing the plurality of error assessment parameters; and One of the plurality of error assessment parameters is determined as the first error assessment parameter according to the comparison result.

20. The memory control circuit unit according to claim 17, wherein the operation of the memory management circuit determining the first vector distance parameter according to the first error assessment parameter among the plurality of error assessment parameters comprises: The first error estimation parameter is converted into the first vector distance parameter according to a conversion function.

21. The memory control circuit unit according to claim 17 , wherein the memory management circuit determines the plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level, comprising: determining a first coordinate point in a coordinate space according to the first read voltage level; Obtain a plurality of second coordinate points in the coordinate space according to a distance parameter between the first coordinate point and the first vector; as well as The plurality of candidate read voltage levels are determined according to the plurality of second coordinate points.

22. The memory control circuit unit according to claim 17 , wherein the plurality of candidate read voltage levels include a first candidate read voltage level and a second candidate read voltage level, and the memory management circuit determines the target read voltage level according to the one of the plurality of candidate read voltage levels, comprising: obtaining a first candidate vector distance parameter between the first candidate read voltage level and a second read voltage level among the plurality of read voltage levels; obtaining a second candidate vector distance parameter between the second candidate read voltage level and the second read voltage level; as well as One of the first candidate read voltage level and the second candidate read voltage level is determined as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter.

23. The memory control circuit unit according to claim 22 , wherein the memory management circuit determines one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first candidate vector distance parameter and the second candidate vector distance parameter, comprising: determining a second vector distance parameter based on a second error assessment parameter among the plurality of error assessment parameters, wherein the second error assessment parameter corresponds to the second read voltage level; Obtaining a first difference between the first candidate vector distance parameter and the second vector distance parameter; obtaining a second difference between the second candidate vector distance parameter and the second vector distance parameter; as well as According to the first difference and the second difference, one of the first candidate read voltage level and the second candidate read voltage level is determined as the target read voltage level.

24. The memory control circuit unit according to claim 23 , wherein when both the number of the first difference values ​​and the number of the second difference values ​​are plural, the memory management circuit determining one of the first candidate read voltage level and the second candidate read voltage level as the target read voltage level according to the first difference value and the second difference value comprises: obtaining a first difference value sum corresponding to the first candidate read voltage level according to the first difference value; obtaining a second difference sum corresponding to the second candidate read voltage level according to the second difference; In response to the first difference sum being less than the second difference sum, determining the first candidate read voltage level as the target read voltage level; as well as In response to the second difference sum being smaller than the first difference sum, the second candidate read voltage level is determined as the target read voltage level.

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