Decoupled RDL connections between die and UBM

Abstract

A semiconductor device has a semiconductor die. A first contact pad, a second contact pad, and a third contact pad are formed over the semiconductor die. An under bump metallization (UBM) is formed over the first, second, and third contact pads. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. A conductive trace can be formed to extend between the first and second contact pads under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.

Description

Technical Field

[0001] This invention generally relates to semiconductor devices, and more specifically to semiconductor devices and methods for forming a discrete connection between semiconductor die terminals and under-bump metallization. Background Technology

[0002] Semiconductor devices are ubiquitous in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between the voltage and current necessary for the circuit to function.

[0004] Back-end manufacturing refers to the process of dicing or isomerizing a completed wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To isomerize a semiconductor die, the wafer is scribed and broken along non-functional regions (called serrations or markings). This is done using laser cutting tools or saw blades. After isomerization, the individual semiconductor dies are mounted onto a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive adhesive, or wirebonds. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the semiconductor device functional and available to other system components.

[0005] Figure 1aA semiconductor wafer or panel 100 is shown, having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. The wafer or panel 100 may also be a fan-out wafer with embedded dies or other components. Multiple semiconductor dies, fan-out dies, or components 104 are formed on or embedded in the wafer or panel 100, separated by non-active inter-die wafer regions or saw tracks 106. Saw tracks 106 provide dicing areas to individualize the semiconductor wafer 100 into individual semiconductor dies, fan-out dies, or components 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). In another embodiment, the reconstructed wafer or panel has a diameter between 200 mm and 450 mm. In other embodiments, the size of the rectangular panel is between 200 mm × 200 mm and 650 mm × 650 mm.

[0006] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0007] A conductive layer 112 is formed over the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads for electrical connections to circuitry on the active surface 110.

[0008] exist Figure 1cIn this process, a saw blade or laser cutting tool 118 is used to monomerize the semiconductor wafer 100 into individual semiconductor dies 104 through the saw groove 106. Individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) after monomerization. Contact pads 112 function as terminals or leads of the semiconductor die. An additional conductive layer, typically including conductive traces and conductive vias, is present, connecting the contact pads 112 to the actual circuitry formed on the active surface 110.

[0009] Subsequent back-end manufacturing steps will encapsulate the semiconductor die 104 in a sealant, a redistribution layer (RDL), and other structures useful for protecting the die 104 and interconnecting it with other semiconductor components. An important aspect of the package is the formation of the RDL to fan in or fan out the terminals of the contact pads 112 into a pattern more suitable for soldering to a larger substrate. A bump under-metallization (UBM) layer is formed over the RDL to improve solder adhesion and integrity over time.

[0010] Figure 2 A typical UBM layer formed over semiconductor die 104 is shown. A passivation layer 130 is typically formed over semiconductor die 104 at the end of front-end fabrication to protect active surface 110. In some embodiments, passivation layer 130 is an inorganic material. Openings are formed in passivation layer 130 for electrical interconnection with die pads 112. Contact pads 112 are referred to as die pads to distinguish them from RDL contact pads formed later. If sealant is deposited around die 104, an insulating layer 132 is formed over passivation layer 130 and sealant. Openings in insulating layer 130 are aligned with openings in passivation layer 130 to expose die pads 112.

[0011] A conductive layer 134 is formed over an insulating layer 132 and includes contact pads 134a and conductive traces 134b. Figure 2 The contact pad 134a shown connects to two different die pads 112: 112a and 112c. Contact pad 134a needs to be large enough to physically contact both die pads 112a and 112c through an opening in the insulating layer 132. Conductive trace 134b is used for... Figure 2 Electrical connections are distributed between other die pads 112 (not shown) and other contact pads 134a in the partial cross-section.

[0012] An insulating layer 136 is formed over the conductive layer 134. An opening is formed through the insulating layer 136 to expose the contact pad 134a. Most of the contact pad 134a is exposed, but a ring surrounding the outside of the contact pad remains covered by the insulating layer 136. A UBM layer 138 is formed directly on the contact pad 134a and extends onto the insulating layer 136 surrounding the outside of the contact pad. The UBM layer 138 physically contacts the contact pad 134a for the entire footprint of the opening in the insulating layer 136. The contact pad 134a and the UBM layer 138 have nearly the same footprint, although their widths may differ. Solder bumps 140 are disposed on the UBM layer 138. The solder bumps 140 flow back to the contact pad on the larger substrate for electrical integration.

[0013] One problem with forming a large UBM that covers and connects to two different die pads 112 is that the underlying RDL contact pad 134a can easily cover other die pads 112 (e.g., die pad 112b), making it difficult or practically impossible to use. Contact pad 134a also occupies valuable RDL routing space, potentially requiring additional RDL layers for the required horizontal signal routing. Furthermore, trace 134b must be routed around UBM 138, increasing trace length and thus circuit resistance and heat generation. Attached Figure Description

[0014] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw marks;

[0015] Figure 2 The diagram illustrates the RDL and UBM formed above one of the semiconductor dies;

[0016] Figures 3a-3c The diagram illustrates a separate RDL pad;

[0017] Figure 4 The diagram illustrates multiple separate RDL layers;

[0018] Figure 5a and Figure 5b The illustration shows an insulating layer with buffering characteristics;

[0019] Figures 6a-6c An embodiment of the additional buffer layer is illustrated; and

[0020] Figure 7 The diagram illustrates a conductive layer buffer. Detailed Implementation

[0021] In the following description with reference to the figures, the invention is described in one or more embodiments, wherein similar numerals denote the same or similar elements. While the invention has been described according to the best mode for carrying out its objectives, those skilled in the art will appreciate that the invention is intended to cover substitutions, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, supported by the following disclosure and the accompanying drawings. The term “semiconductor die” as used herein refers to both the singular and plural forms of the word and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0022] Figure 3a A cross-sectional view of semiconductor die 104 is shown, with RDL and UBM formed above active surface 110. Insulating layer 200 is formed above semiconductor die 104 and passivation layer 130. In some embodiments, semiconductor die 104 is a semiconductor die embedded in a sealant, or after monomerization, a sealant is deposited around semiconductor die 104 and passivation layer 130, and then insulating layer 200 is also formed above the sealant. Insulating layer 200 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), polymer matrix composites having fillers such as Ajinomoto deposited film (ABF) or molding compound, and other materials having similar insulating and structural properties. Insulating layer 200 is formed using spin coating, sputtering, lamination, molding, or any other suitable process. An opening is formed through the insulating layer 200 above the die pad 112 using photolithography or another suitable patterning process.

[0023] A conductive layer 202 is formed above the insulating layer 200. The conductive layer 202 can be one or more layers of Al, Cu, Ti / Cu, TiW / Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 202 is formed using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layer 202 is patterned into a pair of UBM connection contact pads 204a and 204b, an RDL contact pad 206, conductive traces 208 routed around the contact pads 204a and 204b, and conductive traces 210 routed between the contact pads 204a and 204b.

[0024] An insulating layer 220 is formed over the conductive layer 202 and the insulating layer 200. The insulating layer 220 is made of a similar material to the insulating layer 200 and is formed in a similar manner. Openings are formed in the insulating layer 220 over the contact pads 204a and 204b to expose the contact pads for subsequent UBM formation.

[0025] UBM 222 is formed over insulating layer 220 and into openings in exposed contact pads 204a and 204b. UBM 222 is formed in a similar manner to conductive layer 202 and from a similar material. In one embodiment, UBM 222 includes a wetting layer, a barrier layer, and an adhesion layer with different alloy compositions. UBM 222 physically contacts contact pads 204a and 204b in the openings of insulating layer 220. Contact pads 204a and 204b connect UBM 222 in parallel to die pads 112a and 112c, but conductive layer 202 does not otherwise connect contact pads 204a to contact pads 204b or to die pads 112a to die pads 112c. UBM 222 electrically couples contact pads 204a and 204b to each other, thus UBM operates as an RDL coupling die pads 112a and 112c to each other.

[0026] Conductive bump material is deposited on the UBM 222 using evaporation, electrolytic plating, electroless plating, droplet coating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the UBM 222 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 224. The bumps 224 can also be compression bonded or thermocompressed bonded to the UBM 222.

[0027] The conductive layer 202 includes a gap between contact pads 204a and 204b, which allows for the routing of conductive traces and the placement of additional contact pads under the UBM 222, whereas in the prior art, the entire area under the UBM is occupied by RDL contact pads of the same size as the UBM. Figure 3bA plan view of conductive layer 202 is shown. Instead of an RDL having one of its large contact pads covering both die pads 112a and 112c, a pair of contact pads 204 are formed to interconnect between die 104 and UBM 222. The split contact pads 204a and 204b alleviate the routing requirements of the RDL because conductive traces 210 can now be routed between the split contact pads without direct connection to the contact pads. Die pad 112b can even be used with the overlying UBM because contact pad 206 can be formed as part of conductive layer 202 without interference from a large contact pad large enough to cover both die pads 112a and 112c. The split contact pads 204a and 204b allow for the formation of additional contact pads 206 above die pad 112, which is located under the UBM and is not available in the prior art. Although die pad 112b is shown directly between die pads 112a and 112b, die pad 112b and contact pad 206 can be anywhere within the footprint of UBM 222, and the same benefits apply.

[0028] Instead of requiring an RDL layer such as conductive layer 202 to connect die pads 112a and 112c as in existing technologies, UBM 222 operates as an RDL to connect the die pads to each other. Using UBM 222 as an RDL solves the problem of allowing the underlying conductive layers to cross each other to both connect die pads 112a and 112c to each other and route conductive traces 210 under the UBM. Connecting multiple die pads 112 in parallel to UBM 222 also has the benefit of reducing the circuit resistance from die 104 to the UBM. Reduced resistance reduces voltage drop, heat generation, and power consumption, and ensures that semiconductor die 104 remains in good condition for a longer lifespan. UBM 222 connects the die pads 112 horizontally to each other, while conductive layer 202 connects the die pads 112 vertically to the UBM. UBM 222 acts as a metal bridge to bypass other RDL patterns under the UBM and connects die pads 112 from different locations to each other.

[0029] Although two die pads 112 are connected in parallel to UBM 222, any number of die pads can be vertically routed to UBM via conductive layer 202 by using discrete contact pads 204 instead of one large contact pad. Die pads 112 are not interconnected via conductive layer 202, but only via UBM 222 and possibly also by die 104. In other embodiments, two die pads 112 can be connected to each other and to UBM 222 via a single contact pad 204, while a third die pad 112 is connected to UBM in parallel via a separate contact pad 204. Figure 3cAnother embodiment with a rectangular UBM 232 is shown. The UBM can be any suitable shape and is formed above any number of single or separately connected die pads 112.

[0030] Although Figure 3a Only a single RDL layer, namely conductive layer 202, between die pad 112 and UBM 222 is shown, but any suitable number of RDL layers can be stacked to allow for more complex signal routing. Figure 4 A second conductive layer 252 is shown, formed as a second RDL layer above the conductive layer 202. The insulating layer 220 has openings formed to expose contact pads 204 and 206. The conductive layer 252 includes two contact pads 254a and 254b corresponding to and stacked thereon, and stacked thereon. Another contact pad 256 is formed between contact pads 254a and 254b, and below the final footprint of the UBM 222. Contact pad 256 is formed directly above and stacked on contact pad 206, but may also be laterally offset and connected via conductive traces. Conductive traces 260 are routed between contact pads 254a and 254b without direct electrical connection to them. Conductive traces 258 are routed outside the contact pads 254a and 254b.

[0031] An insulating layer 262 is formed over the conductive layer 252. Openings are formed in the insulating layer 262 to expose contact pads 254a and 254b. Contact pads 256 remain covered by the insulating layer 262 and are connected to other locations within the die 104 plan view via conductive traces 258 and 260. A UBM 222 is formed over the insulating layer 262 and extends into the openings in the insulating layer 262 onto the contact pads 254a and 254b. Solder bumps 224 are formed on the UBM 222.

[0032] Contact pads 204a and 254a are stacked to form a vertical conductive path from die 104 to UBM 222. Contact pads 204b and 254b are stacked to form a second vertical conductive path from die 104 to UBM 222 parallel to the first path. Contact pads 204a and 254a electrically connect die pad 112a in series to UBM 222 and in parallel with contact pads 204b and 254b that connect UBM to die pad 112c. Because conductive traces 210 and 230 can be routed between vertical stacks, having separate vertical paths for each die pad 112, rather than a large pad on multiple die pads, allows for additional routing flexibility. The double-layer contact pads with parallel connection to UBM 222 provide even more flexible routing because two layers of conductive traces can be formed through the area between die pads 112a and 112c. Any number of RDL layers can have vertically stacked contact pads to provide discrete signal routing between die pad 112 and UBM 222.

[0033] Figure 5a and Figure 5b The illustration shows passivation buffers formed on contact pads 204a and 204b. An insulating layer 220 is patterned to form a peninsula 270 over contact pad 204a and an island 272 over contact pad 204b. Any combination of buffer peninsulas and islands can be used on any number of contact pads, but for illustrative purposes, one of each is shown. The peninsula 270 can also be formed to extend completely across contact pad 204a, which would form a bridge to divide the contact pad into two separate exposed portions. Contact pad 204a may optionally extend in a direction perpendicular to the peninsula 270 to create more surface area on either side of the peninsula.

[0034] Peninsulas 270 and 272 are passivation buffers that help alleviate physical stress between UBM 222 and die 104, thus improving resilience to thermal cycling and other physical stresses on semiconductor die 104. Stacked via structures such as vias 204 and 254 have better electrical properties than horizontal conductive traces connecting one via to another, but also create higher physical stresses at the interfaces between layers, which can lead to delamination. The buffers reduce interfacial stresses between conductive layers, including the interfacial stress between the top conductive layer and UBM 222.

[0035] Figure 6a and Figure 6bThe diagram illustrates passivation buffers formed over contact pads 254a and 254b. Insulating layer 262 is patterned to form a peninsula 274 over contact pad 254a and an island 276 over contact pad 254b. Both buffers can be either peninsulas or islands, but for illustrative purposes, one of each is shown. Any combination of islands and peninsulas can be used when more than two contact pads 254 are formed over die 104. Contact pad 254a may optionally extend in a direction perpendicular to peninsula 274 to create more surface area on the sides of the peninsula.

[0036] Figure 6c A bridge 280 is shown that divides contact pad 254a into two discrete exposed portions. In other embodiments, contact pad 254a extends perpendicular to bridge 280 to increase the size of the discrete exposed portions. Any combination of bridges, peninsulas, and islands can be used as a buffer layer on any stack of contact pads of conductive layers 202 and 252 to relieve physical stress between UBM 222 and die 104. Both conductive layers 202 and 252 can have buffers on their respective contact pads. The buffers reduce interfacial stress between the conductive layers.

[0037] Figure 7 The diagram illustrates a buffer conductive layer 290 formed between die pad 112 and conductive layer 202. Conductive layer 290 is typically formed of a softer metal, such as copper, to add flexibility to the contact pad stack. The slight compressibility of conductive layer 290 helps alleviate some physical stress on the stacked contact pads 204 and 254. The interface between contact pad 204, typically aluminum, and die pad 112 can often be the weakest link in the stack. Conductive layer 290 includes contact pad 290 and trace 290b. Adding a copper layer between contact pad 204 and die pad 112 increases reliability.

[0038] After packaging die 104, establishing all desired RDL layers, forming all desired UBM 222 and solder bumps 224, and performing any other desired packaging steps, a complete semiconductor package with semiconductor die 104 is formed. This semiconductor package can be any suitable type of package, such as a multi-chip module (MCM), system-in-package (SiP) module, ball grid array (BGA), or embedded wafer-level ball grid array (eWLB). In the completed package, one or more solder bumps 224 are exposed to allow subsequent integration into a larger electrical system. Device manufacturers will integrate the package by picking it up and placing it on a larger substrate and reflowing the solder bumps 224 onto the contact pads of the larger substrate.

[0039] Although one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device comprising: a semiconductor die; a first insulating layer formed over the semiconductor die; a first conductive layer formed over the semiconductor die on the first insulating layer, wherein the first conductive layer is patterned to form a first contact pad, a second contact pad, a third contact pad, and a first conductive trace extending between the first contact pad and the third contact pad; a second insulating layer formed over the first insulating layer and the first conductive layer; a second conductive layer formed on the second insulating layer, wherein the second conductive layer is patterned to form a fourth contact pad, a fifth contact pad, a sixth contact pad, and a second conductive trace extending between the fourth contact pad and the sixth contact pad, wherein the fourth contact pad is formed in a first opening of the second insulating layer directly on the first contact pad, the fifth contact pad is formed in a second opening of the second insulating layer directly on the second contact pad, and the sixth contact pad is formed in a third opening of the second insulating layer directly on the third contact pad; wherein the first opening of the second insulating layer is shaped to include an island of the second insulating layer extending towards a center of the first contact pad as a buffer feature; a third insulating layer formed over the second insulating layer and the second conductive layer; an under bump metallization (UBM) formed directly on the third insulating layer and physically contacting the fourth contact pad through the first opening of the third insulating layer and the fifth contact pad through the second opening of the third insulating layer, wherein the sixth contact pad is held physically and electrically isolated from the UBM by the third insulating layer, and wherein the UBM electrically connects the first contact pad to the second contact pad and the third contact pad is electrically isolated from the UBM; a solder bump formed directly on the UBM and physically contacting the UBM, wherein the first contact pad, the second contact pad, the third contact pad, the fourth contact pad, the fifth contact pad, and the sixth contact pad are all within the footprint of the UBM and the solder bump; and wherein the UBM bypasses the third contact pad, the sixth contact pad, the first conductive trace, and the second conductive trace between the first contact pad and the second contact pad under the UBM.

2. A semiconductor device comprising: a semiconductor die; a first contact pad formed over the semiconductor die; a second contact pad formed over the semiconductor die; an under bump metallization (UBM) formed over the first contact pad and the second contact pad, wherein the first contact pad and the second contact pad are completely within the footprint of the UBM; a solder bump disposed directly on the UBM, wherein the first contact pad and the second contact pad are completely within the footprint of the solder bump; and a conductive trace extending between the first contact pad and the second contact pad under the UBM.

3. The semiconductor device of claim 2, further comprising: a third contact pad formed over the first contact pad; and a fourth contact pad formed over the second contact pad, wherein the UBM is formed over the third contact pad and the fourth contact pad. ​ ​ 4. The semiconductor device of claim 2, further comprising a buffer conductive layer formed between the semiconductor die and the first contact pad.

5. A method of manufacturing a semiconductor device, comprising: providing a semiconductor die; forming a first contact pad over the semiconductor die; forming a second contact pad over the semiconductor die; forming a conductive trace extending between the first contact pad and the second contact pad; forming an under bump metallization (UBM) directly over the first contact pad and the second contact pad and within the footprint of the first contact pad and the second contact pad, wherein the conductive trace is disposed under the UBM, and wherein the first contact pad and the second contact pad are entirely within the footprint of the UBM; and forming a solder bump directly on the UBM, wherein the first contact pad and the second contact pad are entirely within the footprint of the solder bump.

6. The method of claim 5, further comprising: forming a third contact pad over the first contact pad; forming a fourth contact pad over the second contact pad; and forming a UBM over the third contact pad and the fourth contact pad.

7. The method of claim 5, further comprising forming a buffer conductive layer between the semiconductor die and the first contact pad.

8. The method of claim 5, further comprising forming a third contact pad under the UBM, wherein the UBM electrically connects the first contact pad to the second contact pad, and the third contact pad is electrically isolated from the UBM.

9. The method of claim 5, further comprising a solder bump formed directly on and physically contacting the UBM.

10. The method of claim 5, further comprising forming an insulating layer over the first contact pad and the second contact pad, the insulating layer including an island of the insulating layer as a buffer feature of the insulating layer disposed over the first contact pad.

11. A method of manufacturing a semiconductor device, comprising: providing a semiconductor die; forming a conductive layer over the semiconductor die; patterning the conductive layer to form a first contact pad, a second contact pad, and a third contact pad; forming a buffer conductive layer between the semiconductor die and the first contact pad; and forming an under bump metallization (UBM) directly on and physically contacting the first contact pad and the second contact pad, wherein the UBM electrically connects the first contact pad to the second contact pad, and the third contact pad is electrically isolated from the UBM, and wherein the first contact pad and the second contact pad are entirely contained within the footprint of the UBM.

12. The method of claim 11, further comprising patterning the conductive layer to form a conductive trace extending between the first contact pad and the second contact pad under the UBM without physically contacting the first contact pad or the second contact pad.

13. The method of claim 11, further comprising forming an insulating layer over the first and second contact pads, the insulating layer including an insulating layer peninsula as a buffer feature disposed over the first contact pad.

14. The method of claim 11, further comprising: forming an insulating layer over the conductive layer; forming a first opening in the insulating layer over the first contact pad; forming a second opening in the insulating layer over the second contact pad; and forming a UBM over the insulating layer, wherein the UBM extends through the first and second openings to physically contact the first and second contact pads, and wherein the insulating layer remains fully covering the third contact pad to electrically isolate the third contact pad from the UBM.

15. The semiconductor device of claim 1, wherein, the third contact pad is directly between the first and second contact pads, and the sixth contact pad is directly between the fourth and fifth contact pads.

16. The semiconductor device of claim 2, further comprising a third contact pad formed under the UBM, wherein the UBM electrically connects the first contact pad to the second contact pad, and the third contact pad is electrically isolated from the UBM.

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