Semiconductor device, electronic system and method for electrostatic discharge protection of semiconductor device

Abstract

This disclosure provides a semiconductor device, an electronic system, and a method for electrostatic discharge (ESD) protection of the semiconductor device. The semiconductor chip has a substrate; an operating solder structure disposed on a first surface of the substrate to receive an operating signal; a detection solder structure disposed on the first surface of the substrate to receive a chip connection signal; and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip has an operating electrical contact coupled to the operating solder structure; a detection electrical contact coupled to the detection solder structure; an ESD protection unit coupled to the operating electrical contact; and a logic circuit coupled to the detection electrical contact to adjust the capacitance value of the ESD protection unit according to the chip connection signal.

Description

[0001] Cross-references

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 396,275, filed August 6, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. More particularly, it relates to a semiconductor device having multiple electrostatic discharge protection units with adjustable capacitance values. Background Technology

[0004] Electrostatic discharge (ESD) occurs when two objects with different charges come into contact. For example, an ESD event occurs when a pad of a semiconductor chip comes into contact with a charged object, such as a human body or a circuit board. In this case, a strong discharge current will be induced on the pad of the semiconductor chip to discharge the charge accumulated in the semiconductor chip or the charged object. To protect the components in the semiconductor chip from damage by this strong and concentrated discharge current, ESD protection circuitry is typically attached to the pad of the semiconductor chip.

[0005] However, electrostatic discharge (ESD) protection circuits typically include multiple capacitors, which can cause distortion in multiple signals received by these capacitors. For example, because a signal must charge or discharge these capacitors, the rise and fall times of the signal are prolonged. Furthermore, when these signals have higher frequencies, it becomes more difficult to distinguish the data transmitted by them. Additionally, in a multi-chip device, such as a memory device comprising multiple stacked dynamic random access memory (DRAM) chips, these chips in different orders can be coupled to each other to receive the same signals and operate in parallel. In this example, those signals must charge or discharge the capacitors in all the coupled chips, thereby further degrading the quality of the signals.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device including a substrate, an operational solder structure, a detection solder structure, and a first semiconductor chip. The operational solder structure is disposed on a first surface of the substrate and configured to receive an operational signal. The detection solder structure is disposed on the first surface of the substrate and configured to receive a chip connection signal. The first semiconductor chip is disposed on a second surface of the substrate and includes a first operational electrical contact, a first detection electrical contact, a first electrostatic discharge (ESD) protection unit, and a first logic circuit. The first operational electrical contact is coupled to the operational solder structure via the substrate. The first detection electrical contact is coupled to the detection solder structure via the substrate. The first ESD protection unit is coupled to the first operational electrical contact. The first logic circuit is coupled to the first detection electrical contact and configured to adjust the capacitance value of the first ESD protection unit according to the first chip connection signal.

[0008] In some embodiments, the first semiconductor chip further includes a memory circuit configured to perform a plurality of operations in response to at least the operation signal.

[0009] In some embodiments, the first electrostatic discharge protection unit includes a first electrostatic discharge protection element coupled between the first operating electrical contact and a voltage terminal; a second electrostatic discharge protection element; and a control circuit connected in series with the second electrostatic discharge protection element and coupled between the first operating electrical contact and the voltage terminal. The voltage terminal is coupled to a ground or a power supply voltage.

[0010] In some embodiments, the control circuit includes a switch, and the first logic circuit is configured to turn the switch on or off, thereby adjusting the capacitance value of the first electrostatic discharge protection unit.

[0011] In some embodiments, the control circuit includes a fuse, and the first logic circuit is configured to blow the fuse, thereby reducing the capacitance value of the first electrostatic discharge protection unit.

[0012] In some embodiments, the semiconductor device further includes a second semiconductor chip, laterally adjacent to the first semiconductor chip and disposed on the second surface of the substrate or stacked on the first semiconductor chip. The second semiconductor chip includes a second operational electrical contact, a second detection electrical contact, a second electrostatic discharge (ESD) protection unit, and a second logic circuit. The second operational electrical contact is coupled to the operational solder structure. The second detection electrical contact is coupled to the detection solder structure. The second ESD protection unit is coupled to the second operational electrical contact. The second logic circuit is coupled to the second detection electrical contact and configured to adjust the capacitance value of the second ESD protection unit according to a chip connection signal.

[0013] Another embodiment of this disclosure provides an electronic system. The electronic system includes a circuit board, a first semiconductor element, and a second semiconductor element. The first semiconductor element is coupled to the circuit board and includes a first substrate, a first operational solder structure, a first detection solder structure, and a first semiconductor chip. The first operational solder structure is disposed on a first surface of the first substrate and configured to receive a first operational signal. The first detection solder structure is disposed on the first surface of the first substrate and configured to receive a first chip connection signal. The first semiconductor chip is disposed on a second surface of the first substrate and includes a first operational electrical contact, a first detection electrical contact, a first electrostatic discharge (ESD) protection unit, and a first logic circuit. The first operational electrical contact is coupled to the first operational solder structure. The first detection electrical contact is coupled to the first detection solder structure. The first ESD protection unit is coupled to the first operational electrical contact. The first logic circuit is coupled to the first detection electrical contact and configured to adjust the capacitance value of the first ESD protection unit according to at least the first chip connection signal.

[0014] In some embodiments, the first semiconductor element further includes a second semiconductor chip, laterally adjacent to the first semiconductor chip and disposed on the second surface of the first substrate or stacked on the first semiconductor substrate. The second semiconductor chip includes a second operational electrical contact, a second detection electrical contact, a second electrostatic discharge (ESD) protection unit, and a second logic circuit. The second operational electrical contact is coupled to the first operational solder structure. The second detection electrical contact is coupled to the first detection solder structure. The second ESD protection unit is coupled to the second operational electrical contact. The second logic circuit is coupled to the second detection electrical contact and configured to adjust the capacitance value of the second ESD protection unit according to the first chip connection signal.

[0015] In some embodiments, the electronic system further includes a second semiconductor element coupled to the first semiconductor element via the circuit board. The second semiconductor element has a structure identical to that of the first semiconductor element. The second semiconductor element and the first semiconductor element receive the first operation signal and perform multiple operations in parallel thereon. A third logic circuit of a third semiconductor chip in the second semiconductor element is configured to adjust the capacitance value of a third electrostatic discharge protection unit of the third semiconductor chip according to the first chip connection signal.

[0016] In some embodiments, the first semiconductor element is disposed on a first surface of the circuit board, and the second semiconductor element is disposed on a second surface of the circuit board; and the first semiconductor element and the second semiconductor element are laterally disposed on the same surface of the circuit board.

[0017] In some embodiments, the first semiconductor chip further includes a memory circuit configured to perform a plurality of operations in response to at least the first operation signal.

[0018] In some embodiments, the electronic system further includes a third semiconductor element coupled to the first semiconductor element via the circuit board, wherein the third semiconductor element includes a memory controller configured to control the memory circuit in the first semiconductor chip and generate the first chip connection signal.

[0019] In some embodiments, the first semiconductor element is disposed on a first surface of the circuit board, and the third semiconductor element is disposed on a second surface of the circuit board; or the first semiconductor element and the second semiconductor element are disposed laterally on the same surface of the circuit board.

[0020] In some embodiments, the first electrostatic discharge (ESD) protection unit includes a first ESD protection element, a second ESD protection element, and a control circuit. The first ESD protection element is coupled between the first electrical contact and a voltage terminal, wherein the voltage terminal is coupled to a ground or a power supply voltage. The control circuit is connected in series with the second ESD protection element and coupled between the first operating electrical contact and the ground.

[0021] In some embodiments, the control circuit includes a switch, and the first logic circuit is configured to turn the switch on or off, thereby adjusting the capacitance value of the first electrostatic discharge protection unit.

[0022] In some embodiments, the control circuit includes a fuse, and the first logic circuit is configured to blow the fuse, thereby reducing the capacitance value of the first electrostatic discharge protection unit.

[0023] Another embodiment of this disclosure provides a method for electrostatic discharge (ESD) protection of a first semiconductor device. The first semiconductor device includes a substrate; an operational solder structure disposed on a first surface of the substrate; and a first semiconductor chip disposed on a second surface of the substrate. The ESD protection method includes forming an ESD protection unit in the first semiconductor chip, wherein the ESD protection unit is coupled between a voltage terminal and an operational electrical contact of the first semiconductor chip coupled to the operational solder structure via the substrate, and the voltage terminal is coupled to a ground or a power supply voltage; coupling the first semiconductor device to a circuit board; transmitting an operational signal to the operational solder structure via the substrate; and adjusting the capacitance values ​​of the plurality of ESD protection units according to a total number of plurality of semiconductor chips that transmit the operational signal and operate in parallel with the first semiconductor chip.

[0024] In some embodiments, the electrostatic discharge protection unit includes a plurality of electrostatic discharge protection elements coupled between the operating electrical contact and the voltage terminal, and the capacitance value of the plurality of electrostatic discharge protection units is adjusted by a total number of a plurality of semiconductor chips that transmit the operating signal and operate in parallel with the first semiconductor chip, including disconnecting at least one electrostatic discharge protection element from the operating electrical contact or the voltage terminal.

[0025] In some embodiments, one of the semiconductor chips that transmits the operation signal and operates in parallel with the first semiconductor chip is in the first semiconductor element or in a second semiconductor element coupled to the first semiconductor element via the circuit board.

[0026] In some embodiments, the first semiconductor element and the second semiconductor element include memory circuits with different ranks.

[0027] Since the electrostatic discharge protection method of the semiconductor element, the electronic system, and the semiconductor element can adjust the capacitance value of the plurality of electrostatic discharge protection units according to the number of the plurality of semiconductor elements coupled together to operate in parallel, the signal distortion caused by the capacitance value of the plurality of electrostatic discharge protection units can be reduced.

[0028] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0029] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0030] Figure 1 This is a schematic diagram illustrating a semiconductor element according to an embodiment of the present disclosure.

[0031] Figure 2 This is a circuit diagram illustrating an embodiment of the present disclosure. Figure 1 Semiconductor chips in the process.

[0032] Figure 3 This is a circuit diagram illustrating other embodiments of this disclosure. Figure 2 Multiple electrostatic discharge protection units are included.

[0033] Figure 4 This is a circuit diagram illustrating an electrostatic discharge protection unit in other embodiments of this disclosure.

[0034] Figure 5 This is a circuit diagram illustrating an electrostatic discharge protection unit in other embodiments of this disclosure.

[0035] Figure 6 This is a circuit diagram illustrating an electrostatic discharge protection unit in other embodiments of this disclosure.

[0036] Figure 7 This is a schematic diagram illustrating a semiconductor element in other embodiments of this disclosure.

[0037] Figure 8 This is a circuit diagram illustrating an embodiment of the present disclosure. Figure 7 Multiple semiconductor chips in the process.

[0038] Figure 9 This is a structural schematic diagram illustrating an electronic system according to other embodiments of this disclosure.

[0039] Figure 10 This is a circuit diagram illustrating an embodiment of the present disclosure. Figure 9 Multiple semiconductor chips in the process.

[0040] Figure 11 This is a structural schematic diagram illustrating an electronic system according to other embodiments of this disclosure.

[0041] Figure 12 This is a flowchart illustrating an electrostatic discharge protection method for a semiconductor device according to an embodiment of the present disclosure.

[0042] Explanation of reference numerals in the attached figures:

[0043] 6: Electronic Systems

[0044] 7: Electronic Systems

[0045] 10: Semiconductor components

[0046] 12: Base

[0047] 14A1~14AN: Operating solder structure

[0048] 16A1~16AM: Inspect solder structure

[0049] 50: Semiconductor components

[0050] 52: Base

[0051] 54A1~54AN: Operating solder structure

[0052] 56A1~56AM: Inspecting solder structure

[0053] 60A: First semiconductor element

[0054] 60B: Second semiconductor element

[0055] 60C: Third semiconductor element

[0056] 62A: First substrate

[0057] 62B: Second substrate

[0058] 64A1~64AN: First Operation Solder Structure

[0059] 64B1~64BN: Second Operation Solder Structure

[0060] 66A1~66AM: First inspection of solder structure

[0061] 66B1~66BM: Second inspection solder structure

[0062] 100: Semiconductor chip

[0063] 110A1~110AN: Operating electrical contacts

[0064] 120: Memory circuit

[0065] 130A1~130AN: Electrostatic Discharge Protection Unit

[0066] 130B1~130BN: Electrostatic Discharge Protection Unit

[0067] 132A: First electrostatic discharge protection element

[0068] 132B: First electrostatic discharge protection element

[0069] 134A: Second electrostatic discharge protection element

[0070] 134B: Second electrostatic discharge protection element

[0071] 136A: Control circuit

[0072] 136B: Control circuit

[0073] 140A1~140AM: Detecting electrical contact points

[0074] 150: Logic Circuits

[0075] 210: Operating electrical contact point

[0076] 230: Electrostatic Discharge Protection Unit

[0077] 232: First electrostatic discharge protection element

[0078] 234: Second electrostatic discharge protection element

[0079] 236: First control circuit

[0080] 238: Second control circuit

[0081] 310: Operating electrical contact points

[0082] 330: Electrostatic Discharge Protection Unit

[0083] 332: Electrostatic Discharge Protection Components

[0084] 336: Control Circuit

[0085] 410: Operating electrical contact points

[0086] 430: Electrostatic Discharge Protection Unit

[0087] 432: Electrostatic Discharge Protection Components

[0088] 436: Control Circuit

[0089] 500A: First Semiconductor Chip

[0090] 500B: Second Semiconductor Chip

[0091] 510A1~510AN: First operating electrical contact points

[0092] 510B1~510BN: Second operating electrical contact points

[0093] 520A: First Memory Circuit

[0094] 520B: Second Memory Circuit

[0095] 530A1~530AN: First electrostatic discharge protection unit

[0096] 530B1~530BN: First electrostatic discharge protection unit

[0097] 540A1~540AN: First detection electrical contact point

[0098] 540B1~540BM: Second detection electrical contact point

[0099] 550A: First Logic Circuit

[0100] 550B: Second Logic Circuit

[0101] 600A: First Semiconductor Chip

[0102] 600B: Second Semiconductor Chip

[0103] 600C: Third Semiconductor Chip

[0104] 610A1~610AN: Operating electrical contacts

[0105] 610B1~610BN: Operating electrical contacts

[0106] 620A: Memory circuit

[0107] 620B: Memory circuit

[0108] 640A1~640AM: Detection of electrical contact points

[0109] 640B1~640BM: Detection of electrical contact points

[0110] 650A: Logic Circuit

[0111] 650B: Logic Circuit

[0112] 800: Electrostatic Discharge Protection Methods

[0113] A1: First surface

[0114] A2: Second surface

[0115] B1: Circuit Board

[0116] CL: Inner conductive layer

[0117] D1A: Diode

[0118] D1B: Diode

[0119] D2A: Diode

[0120] D2B: Diode

[0121] F1: Fuse

[0122] GND: Ground

[0123] MC1: Memory Controller

[0124] S810: Steps

[0125] S820: Steps

[0126] S830: Steps

[0127] S840: Steps

[0128] SIG CC1 ~SIG CCM Chip connection signal

[0129] SIG OP1 ~SIG OPN : Operation signal

[0130] SW1A: Switch

[0131] SW1B: Switch

[0132] V1: Through Silicon Via

[0133] VDD: Power supply voltage

[0134] VT: Voltage terminal Detailed Implementation

[0135] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0136] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0137] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0138] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0139] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term “substantially” may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0140] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0141] Figure 1 This is a schematic diagram illustrating a semiconductor element 10 according to an embodiment of the present disclosure. The semiconductor element 10 includes a substrate 12, solder operation structures 14A1-14AN, solder detection structures 16A1-16AM, and a semiconductor chip 100, where N and M are positive integers. In some embodiments, N and M may be 1, and the semiconductor element 10 may include an solder operation structure 14A1 and a solder detection structure 16A1. The solder operation structures 14A1-14AN can receive an operation signal SIG. OP1 ~SIG OPNFurthermore, the solder structure detection 16A1~16AM can receive the chip connection signal SIG. CC1 ~SIG CCM .

[0142] like Figure 1 As shown, the operating solder structures 14A1-14AN and the detecting solder structures 16A1-16AM are disposed on a first surface A1 of the substrate 12, and the semiconductor chip 100 is disposed on a second surface A2 of the substrate 12. In this embodiment, the substrate 12 includes a plurality of inner conductive layers CL (or a plurality of redistribution layers) to couple the semiconductor chip 100 to the operating solder structures 14A1-14AN and the detecting solder structures 16A1-16AM, so that the semiconductor chip 100 can receive an operation signal SIG in response to each corresponding operation. OP1 ~SIG OPN and the chip connection signal SIG CC1 ~SIG CCM That is, the substrate 12 can be a packaging carrier, and the operating solder structures 14A1 to 14AN and the detecting solder structures 16A1 to 16AM can be solder bumps, solder balls or other types of solder structures, so that the semiconductor device 10 can be mounted to a printed circuit board by soldering.

[0143] Figure 2 This is a circuit diagram illustrating an embodiment of the present disclosure. Figure 1 The semiconductor chip 100 includes operational electrical contacts 110A1 to 110AN, a memory circuit 120, electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN, detection electrical contacts 140A1 to 140AM, and logic circuitry 150. In some embodiments, N and M may be positive integers, such as 4, 6, or 8. However, this disclosure is not limited thereto. In some embodiments, N and M may be 1. In this example, the semiconductor chip 100 includes an operational electrical contact 110A1, an electrostatic discharge protection unit 130A1, an electrostatic discharge protection unit 130B1, and a detection electrical contact 140A1.

[0144] The operational electrical contacts 110A1–110AN and the detection electrical contacts 140A1–140AM can be pins, solder pads, micro bumps, or other types of contacts for external connections. Furthermore, such as Figure 1As shown, each operational electrical contact 110A1 to 110AN can be coupled to a corresponding operational solder structure 14A1 to 14AN via substrate 12 to receive an operational signal, and each detection electrical contact 140A1 to 140AM can be coupled to a corresponding detection solder structure 16A1 to 16AM via substrate 120 to receive a chip connection signal.

[0145] The memory circuit 120 can perform multiple operations based on the multiple signals received by the operating electrical contacts 110A1 to 110AN. For example, the memory circuit 120 can be a dynamic random access memory (DRAM) circuit. In this example, the operating electrical contacts 110A1 to 110AN can receive multiple read / write commands and multiple addresses or data based on the multiple commands, and the memory circuit 120 can perform multiple read operations or multiple write operations based on the multiple commands, and transfer the required data accordingly.

[0146] Since the operating electrical contacts 110A1 to 110AN are used for external connections, electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN are coupled to the operating electrical contacts 110A1 to 110AN to provide multiple discharge paths at the electrical contacts 110A1 to 110AN, thereby preventing discharge current from damaging the memory circuit 120. For example... Figure 2 As shown, each electrostatic discharge (ESD) protection unit 130A1 to 130AN is coupled to a corresponding electrical contact among the operating electrical contacts 110A1 to 110AN and ground GND, and each ESD protection unit 130B1 to 130BN is coupled to a corresponding electrical contact among the operating electrical contacts 110A1 to 110AN and power supply voltage VDD. For example, ESD protection unit 130AN is coupled between the operating electrical contact 110AN and ground GND, while ESD protection unit 130BN is coupled between the operating electrical contact 110AN and power supply voltage VDD. However, this disclosure is not limited thereto. In some embodiments, the semiconductor chip 100 may omit some ESD protection units 130A1 to 130AN and 130B1 to 130BN as needed by the system. For example, the semiconductor chip 100 may omit electrostatic discharge protection units 130A1 to 130AN, electrostatic discharge protection units 130B1 to 130BN, or omit some electrostatic discharge protection units 130A1 to 130AN and some electrostatic discharge protection units 130B1 to 130BN.

[0147] Since the electrostatic discharge protection units 130A1-130AN and 130B1-13BN are capacitive, the operating signal SIG received by the operating electrical contacts 110A1-110AN is used before the memory circuit 120 can correctly sense the multiple signals. OP1 ~SIC OPN The equivalent capacitors or parasitic capacitors of the electrostatic discharge protection units 130A1-130AN and 130B1-130BN need to be charged or discharged. That is, due to the capacitance values ​​of the electrostatic discharge protection units 130A1-130AN and 130B1-130BN, the multiple signals will be distorted. Furthermore, in some embodiments, the semiconductor chip 100 can be coupled to other semiconductor chips and can receive the same multiple signals as those semiconductor chips to perform the multiple operations in parallel. For example, if the semiconductor chip 100 is coupled to other semiconductor chips (e.g., other semiconductor wafers disposed in a semiconductor element or...) Figure 1 If other semiconductor chips (not shown) in the configuration correspond to different sequences in the same memory system, then semiconductor chip 100 and those other semiconductor chips will receive the same signals and perform multiple read / write operations in parallel. In this example, the multiple signals transmitted to the multiple electrical contacts of semiconductor chip 100 and other semiconductor chips will have to charge the equivalent capacitors of the multiple electrostatic discharge protection units of all semiconductor chips. Therefore, the distortion of these multiple signals becomes more severe.

[0148] To mitigate this distortion, when semiconductor chip 100 is coupled to other semiconductor chips, semiconductor chip 100 can receive the multiple chip connection signals SIG via detecting electrical contacts 140A1 to 104AM. CC1 ~SIG CCM This allows the semiconductor chip 100 to notify of the presence of other connected chips. Therefore, the logic circuit 150 coupled to the detection electrical contacts 140A1-140AM can detect the multiple chip connection signals SIG received from the detection electrical contacts 140A1-140AM. CC1 ~SIG CCM The capacitance values ​​of the electrostatic discharge protection units 1301 to 130N are adjusted. That is, the logic circuit 150 can adjust the capacitance values ​​based on the SIG signals of the multiple chips. CC1 ~SIG CCMThe number of semiconductor chips coupled to semiconductor chip 100 is known, and the capacitance values ​​of electrostatic discharge protection elements 130A1 to 130AN are adjusted according to the number of semiconductor chips coupled to semiconductor chip 100. For example, in some embodiments, the signal can be used as M binary bits to represent the number of semiconductor chips coupled to semiconductor chip 100, and the logic circuit 150 can decode the chip connection signal SIG. CC1 ~SIG CCM To obtain the number of the plurality of semiconductor chips, and adjust the electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN accordingly.

[0149] Figure 3 This is a circuit diagram illustrating electrostatic discharge protection units 130A1 and 130B1 according to an embodiment of this disclosure. In this embodiment, electrostatic discharge protection units 130A1 to 130AN and 130B1 to 130BN may have the same structure. Figure 3 As shown, the electrostatic discharge protection unit 130A1 includes a first electrostatic discharge protection element 132A, a second electrostatic discharge protection element 134A, and a control circuit 136A.

[0150] The first electrostatic discharge protection element 132A is coupled between the operating electrical contact 110A1 and ground GND, while the second electrostatic discharge protection element 134A is coupled between the operating electrical contact 110A1 and ground GND. Figure 3 As shown, the first electrostatic discharge protection element 132A has a diode D1A. Diode D1A has an anode and a cathode, the anode being coupled to ground GND and the cathode being coupled to the operating electrical contact 110A1. Similarly, the second electrostatic discharge protection element 134A also has a diode D2A, having an anode and a cathode, the anode being coupled to ground GND and the cathode being coupled to the operating electrical contact 110A1.

[0151] In some embodiments, the first electrostatic discharge (ESD) protection element 132A has a first capacitance value, while the second ESD protection element 134A has a second capacitance value. Since the first ESD protection element 132A and the second ESD protection element 134A are connected in parallel between the operating electrical contact 110A1 and ground (GND), the equivalent capacitance of the ESD protection unit 130A1 is approximately the sum of the first capacitance value of the first ESD protection element 132A and the second capacitance value of the second ESD protection element 134A. In this embodiment, to allow the logic circuit 150 to adjust the capacitance value of the ESD protection unit 130A1, the control circuit 136A may be connected in series with the second ESD protection element 134A between the operating electrical contact 110A1 and ground (GND). Figure 3 As shown, the control circuit 136A includes a switch SW1A. In this example, the logic circuit 150 can turn off the switch SW1A to disconnect the second electrostatic discharge protection element 134A from the operating electrical contact 110A1 or ground GND. Therefore, the second electrostatic discharge protection element 134A will no longer be used to provide multiple discharge paths between the operating electrical contact 110A1 and ground GND, and the capacitance value of the first electrostatic discharge protection unit 130A1 will be reduced. That is, by turning the switch SW1A on or off, the logic circuit 150 can adjust the capacitance value of the first electrostatic discharge protection unit 130A1 according to system requirements.

[0152] Similarly, the electrostatic discharge protection unit 130B1 has a first electrostatic discharge protection element 132B, a second electrostatic discharge protection element 134B, and a control circuit 136B. The first electrostatic discharge protection element 132B is coupled between the operating electrical contact 110A1 and the power supply voltage VDD, and the second electrostatic discharge protection element 134B is connected in series with the control circuit 136B between the operating electrical contact 110A1 and the power supply voltage VDD. Figure 3 As shown, the first electrostatic discharge (ESD) protection element 132B has a diode D1B, and the second ESD protection element 134A. The anodes of diodes D1 and D2 are coupled to the operating electrical contact 110A1, and the cathodes of diodes D1 and D2 are coupled to the power supply voltage VDD. That is, ESD protection elements 132B and 134B can be used to provide a discharge path between the operating electrical contact 110A1 and the power supply voltage VDD. Furthermore, the logic circuit 150 can turn the switch SW1B of the control circuit 136B on or off according to system requirements to adjust the capacitance value of the ESD protection unit 130B1.

[0153] In some embodiments, in electrostatic discharge protection units 130A1 and 130B1, diodes D1A and D1B may have the same dimensions as diodes D2A and D2B. In this example, the first capacitance value of the first electrostatic discharge protection element 132A may be approximately equal to the second capacitance value of the second electrostatic discharge protection element 134A. However, this disclosure is not limited thereto. In some other embodiments, diodes D1A and D2A may have different dimensions, and the first capacitance value of the first electrostatic discharge protection element 132A may be different from the second capacitance value of the second electrostatic discharge protection element 134A. Furthermore, in some other embodiments, the first electrostatic discharge protection elements 132A, 134A, 132B, and 134B may include other types of components, such as capacitors, resistors, and / or transistors.

[0154] Figure 4 This is a circuit diagram illustrating an electrostatic discharge (ESD) protection unit 230 in other embodiments of this disclosure. In some embodiments, the ESD protection unit 230 can be used to replace ESD protection units 130A1-130AN and 130B1-130BN in the semiconductor chip 100. Figure 4 As shown, the electrostatic discharge (ESD) protection unit 230 includes a first ESD protection element 232, a second ESD protection element 234, a first control circuit 236, and a second control circuit 238. The first control circuit 236 is connected in series with the first ESD protection element 232 between an operating electrical contact 210 and a voltage terminal VT. In some embodiments, the voltage terminal VT may be coupled to ground GND or a power supply voltage VDD. The second control circuit 238 is connected in series with the second ESD protection element 234 between the operating electrical contact 210 and the voltage terminal VT. Furthermore, the capacitance values ​​of the first ESD protection element 232 and the second ESD protection element 234 may be different. In this example, where each ESD protection unit 130A1 to 130AN and 130B1 to 130BN is replaced by the ESD protection unit 230, the manufacturer can decide, based on requirements, to turn off switch SW1 of the first control circuit 236 or switch SW2 of the second control circuit 238 to provide ESD protection with the desired capacitance value. In some embodiments, the electrostatic discharge protection unit 230 may also include more electrostatic discharge protection elements and control circuitry to provide more options for capacitance values.

[0155] Figure 5 This is a circuit structure diagram illustrating an electrostatic discharge (ESD) protection unit 330 in another embodiment of this disclosure. In this embodiment, the ESD protection unit 330 can be used to implement ESD protection units 130A1 to 130AN and 130B1 to 130BN of the semiconductor chip 100. Figure 5As shown, the electrostatic discharge (ESD) protection unit 330 includes multiple ESD protection elements 332 and multiple control circuits 336. Each ESD protection element 332 is connected in series with a control circuit 336 between the operating electrical contact 310 and the voltage terminal VT. In this example, by turning on different numbers of switches SW of the multiple control circuits 336, the ESD protection unit 330 can be adjusted to have different capacitance values. That is, by having more ESD protection elements 332 and control circuits 336, it allows the ESD protection unit 330 to provide a wider selection of different capacitance values.

[0156] In some embodiments, the control circuit may include a switch that can be turned on or off. However, this disclosure is not limited thereto. In some embodiments, the control circuit may include multiple fuses. Figure 6 This is a circuit diagram illustrating an electrostatic discharge (ESD) protection unit 430 in another embodiment of this disclosure. In this embodiment, the ESD protection unit 430 can be used to implement ESD protection units 130A1 to 130AN and 130B1 to 130BN of the semiconductor chip 100. Figure 6 As shown, the electrostatic discharge protection unit 430 includes a plurality of electrostatic discharge protection elements 432 and a plurality of control circuits 436. Each electrostatic discharge protection element 432 is connected in series with a control circuit 436 between the operating electrical contact 410 and the voltage terminal VT. In this example, by blowing different numbers of fuses F1 of the plurality of control circuits 436, the electrostatic discharge protection unit 430 can be adjusted to have different capacitance values. In some embodiments, the semiconductor chip 100 may also include other circuits or components ( Figure 6 (Not shown) to control each fuse F1 of the plurality of control circuits 436 so that the plurality of fuses F1 can be melted without damaging other components in the semiconductor chip 100.

[0157] Figure 7 This is a schematic diagram illustrating a semiconductor element 50 according to an embodiment of the present disclosure. The semiconductor element 50 includes a substrate 52, solder operation structures 54A1-54AN, solder detection structures 56A1-56AM, a first semiconductor chip 500A, and a second semiconductor chip 500B. The solder operation structures 54A1-54AN can receive an operation signal SIG. OP1 ~SIG OPN Furthermore, the solder structure detection system 56A1~56AM can receive the chip connection signal SIG. CC1 ~SIG CCMFurthermore, the first operating electrical contacts 510A1 to 510AN of the first semiconductor chip 500A and the second operating electrical contacts 510B1 to 510BN of the second semiconductor chip 500B can be coupled to the operating solder structures 54A1 to 54AN to receive the operating signal SIG. OP1 ~SIG OPN Furthermore, the first detection electrical contacts 540A1-540AM of the first semiconductor chip 500A and the second detection electrical contacts 540B1-540BM of the second semiconductor chip 500B can be coupled to the detection solder structures 56A1-56AM to receive the chip connection signal SIG. CC1 ~SIG CCM .

[0158] Furthermore, such as Figure 7 As shown, a first semiconductor chip 500A is disposed on a substrate 52, and a second semiconductor chip 500B is stacked on the first semiconductor chip 500A. In this embodiment, each of the second operational electrostatic discharge protection units 530B1 to 530BN can be coupled to one of the corresponding second operational electrical contacts 510A1 to 510AN via a through-silicon via (TSV) V1. However, this disclosure is not limited thereto. For example, in some other embodiments, the second semiconductor chip 500B can be stacked on the first semiconductor chip 500A without covering the first operational electrical contacts 510A1 to 510AN, so the second operational electrical contacts 510B1 to 510BN can be coupled to the first operational electrical contacts 510A1 to 510AN via wire bonding. However, this disclosure is not limited to the stacking of the first semiconductor chip 500A and the second semiconductor chip 500B. In some other embodiments, the first semiconductor chip 500A and the second semiconductor chip 500B may be disposed laterally adjacent to each other on the same surface of a substrate.

[0159] Figure 8 This is a circuit diagram illustrating semiconductor chip 500A and semiconductor chip 500B according to an embodiment of this disclosure. In this embodiment, semiconductor chips 500A and 500B may have the same structure. For example, such as Figure 8As shown, the first semiconductor chip 500A includes first operating electrical contacts 510A1 to 510AN, a first memory circuit 520A, first electrostatic discharge protection units 530A1 to 530AN, first detection electrical contacts 540A1 to 540AN, and a first logic circuit 550A. Furthermore, the second semiconductor chip 500B includes second operating electrical contacts 510B1 to 510BN, a second memory circuit 520B, second electrostatic discharge protection units 530B1 to 530BN, second detection electrical contacts 540B1 to 540BM, and a second logic circuit 550B.

[0160] In this embodiment, the semiconductor element 50 may be a memory element, and the first memory circuit 520A and the second memory circuit 520B may be DRAM circuits, which are combined to provide the semiconductor element 50 with a wider bandwidth and a larger memory space. In this example, the first operating electrical contacts 510A1 to 510AN and the second operating electrical contacts 510B1 to 510BN can be used to receive the plurality of identical operating signals SIG. OP1 ~SIG OPN Furthermore, memory circuits 520A and 520B can operate based on the SIG signal. OP1 ~SIG OPN Parallel operation. Furthermore, since the first electrostatic discharge protection unit 530A1 and the second electrostatic discharge protection unit 530B1 are capacitive, the SIG signal... OP1 The signal SIG needs to be detectable by the first memory circuit 520A and the second memory circuit 520B. OP1 Before the actual voltage, the SIG signal OP1 The equivalent capacitors or parasitic capacitors of the first electrostatic discharge protection unit 530A1 and the second electrostatic discharge unit 530B1 need to be charged. Therefore, due to the capacitance values ​​of the first electrostatic discharge protection unit 530A1 and the second electrostatic discharge unit 530B1, the signal SIG... OP1 It will be distorted.

[0161] To mitigate the SIG signal OP1 The distortion can be adjusted by changing the capacitance values ​​of the first electrostatic discharge protection unit 530A1 and the second electrostatic discharge protection unit 530B1. For example, the first electrostatic discharge protection unit 530A1 and the second electrostatic discharge protection unit 530B1 may have the same capacitance values ​​as shown in the figure. Figure 3The structure of the electrostatic discharge protection unit 130A1 is shown. In this example, because logic circuit 550A can turn off the switch in the first electrostatic discharge protection unit 530A1 and logic circuit 550B can turn off the switch in the second electrostatic discharge protection unit 530B1, the capacitance value of each of the first electrostatic discharge protection unit 530A1 and the second electrostatic discharge protection unit 530B1 can be reduced. In some embodiments, the chip connection signal SIG CC1 ~SIG CCM Logic circuits 520A and 520B can be used to notify the total number of multiple semiconductor chips coupled together to operate in parallel. This is due to the operation signal SIG. OP1 ~SIG OPN The distortion is related to the total number of semiconductor chips coupled together and operating in parallel, so logic circuits 520A and 520B can be based on the chip connection signal SIG. CC1 ~SIG CCM Adjust the capacitance values ​​of the electrostatic discharge protection units 530A1~530AN and 530B1~530BN.

[0162] Furthermore, this disclosure does not limit the scope of application. Figure 3 The electrostatic discharge protection unit 130A1 shown implements the first electrostatic discharge protection units 530A1 to 530AN and the second electrostatic discharge protection units 530B1 to 530BN. In some other embodiments, such as Figure 4 The electrostatic discharge protection unit 230 shown is as follows: Figure 5 The electrostatic discharge protection unit 330 shown, or as... Figure 6 The electrostatic discharge (ESD) protection unit 430 shown implements the first ESD protection units 530A1 to 530AN and the second ESD protection units 530B1 to 530BN. Furthermore, to provide multiple discharge paths to ground GND and power supply voltage VDD, the first semiconductor chip 500A and the second semiconductor chip 500B may include more ESD protection units, such that each electrical contact point 510A1 to 510AN and 510B1 to 510BN can be protected by two ESD protection units, one coupled to ground GND and the other coupled to the power supply voltage VDD, similar to... Figure 2 The semiconductor chip 100 shown.

[0163] In some embodiments, in addition to semiconductor chips 500A and 500B, semiconductor element 50 may include more semiconductor chips as needed by the system. Furthermore, in some embodiments, different semiconductor elements may be coupled together so that the plurality of semiconductor chips in different semiconductor elements can receive the same operating signals and operate in parallel.

[0164] Figure 9 This is a schematic diagram illustrating an electronic system 6 according to another embodiment of this disclosure. The electronic system 6 includes a circuit board B1, a first semiconductor element 60A, and a second semiconductor element 60B. The second semiconductor element 60B can be coupled to the first semiconductor element 60A via the circuit board B1. Figure 9 As shown, a first semiconductor element 60A is disposed on a first surface of circuit board B1, and a second semiconductor element 60B is disposed on a second surface of circuit board B1. That is, the first semiconductor element 60A and the second semiconductor element 60B can be mounted to circuit board B1 in a back-to-back manner. However, this disclosure is not limited thereto. In some embodiments, the first semiconductor element 60A and the second semiconductor element 60B may be disposed laterally on the same surface of circuit board B1.

[0165] In this embodiment, the first semiconductor element 60A and the second semiconductor element 60B may have the same structure. For example, semiconductor elements 60A and 60B may be implemented using semiconductor element 10. For example, the first semiconductor element 60A includes a first substrate 62A, first operating solder structures 64A1-64AN, first detection solder structures 66A1-66AM, and a first semiconductor chip 600A. The first operating solder structures 64A1-64AN and the first detection solder structures 66A1-66AM are disposed on a first surface of the first substrate 62A, and the first semiconductor chip 600A is disposed on a second surface of the first substrate 62A. Moreover, the second semiconductor element 60B includes a second substrate 62B, second operating solder structures 64B1-64BN, second detection solder structures 66B1-66BM, and a second semiconductor chip 600B. The second operational solder structures 64B1 to 64BN and the second detection solder structures 66B1 to 66BM are disposed on a first surface of the second substrate 62B, and the second semiconductor chip 600B is disposed on a second surface of the second substrate 62B.

[0166] In this embodiment, each of the first operating solder structures 64A1 to 64AN can be coupled to a corresponding second operating solder structure 64B1 to 64BN to receive the same operating signal SIG. OP1 ~SIG OPN Therefore, each circuit in the first semiconductor element 60A and the second semiconductor element 60B can perform multiple operations in parallel. Figure 10 This is a circuit diagram illustrating semiconductor chip 600A in the first semiconductor element 60A and semiconductor chip 600B in the second semiconductor element 60B. In this embodiment, semiconductor chips 600A and 600B have the following characteristics: Figure 8The semiconductor chip 500A shown has the same structure. In this example, the operating electrical contacts 610A1 to 610AN of semiconductor chip 600A are coupled to the operating electrical contacts 610B1 to 610BN of semiconductor chip 600B via operating solder structures 64A1 to 64AN and 64B1 to 64BN, respectively, so that semiconductor chips 600A and 600B can receive the same operating signal SIG. OP1 ~SIG OPN Therefore, the memory circuit 620A of semiconductor chip 600A and the memory circuit 620B of semiconductor chip 600B can perform multiple operations in parallel. In this example, the operation signal SIG OP1 ~SIG OPN The equivalent capacitance or parasitic capacitance of the electrostatic discharge protection units 630A1 to 630AN in semiconductor chips 600A1 and 600B1 must be charged or discharged, which causes distortion.

[0167] To mitigate distortion caused by the capacitance values ​​of the electrostatic discharge protection units 630A1 to 630AN, the logic circuit 650A can adjust the signal based on the chip connection signal SIG. CC1 ~SIG CCM The capacitance values ​​of the electrostatic discharge protection units 630A1 to 630AN of the semiconductor chip 600A are adjusted, and the chip connection signal SIG is... CC1 ~SIG CCM It is received by detecting the solder structure 66A1-66AM and the electrical contacts 640A1-640AM. Similarly, the logic circuit 650B can detect the chip connection signal SIG. CC1 ~SIG CCM Adjusting the capacitance values ​​of the electrostatic discharge protection units 630B1 to 630BN of the semiconductor chip 600B, and connecting the chip to the SIG signal... CC1 ~SIG CCM It is received by detecting electrical contacts 640B1-640BM via detecting solder structures 66B1-66BM. In some embodiments, the chip connection signal SIG CC1 ~SIG CCM It can be transmitted to semiconductor elements 60A and 60B via circuit board B1, and can be controlled by a control circuit or a processor of electronic system 6. Figure 9 (Not shown in the figure) generated by.

[0168] Figure 11 This is a schematic diagram illustrating an electronic system 7 according to another embodiment of this disclosure. Electronic system 7 has a similar structure to electronic system 6. However, electronic system 7 further includes a third semiconductor element 60C. When the semiconductor chips 600A and 600B of semiconductor elements 60A and 60B have such... Figure 10In the memory circuits 620A and 620B shown, the third semiconductor element 60C has a memory controller MC1 to control the memory circuits 620A and 620B in the semiconductor chips 600A and 600B. Figure 11 As shown, the memory controller MC1 can be formed within the semiconductor chip 600C in the third semiconductor element 60C. In this example, since the memory controller MC1 must know the total number of semiconductor chips 600A and 600B coupled together to operate in parallel, the memory controller MC1 can also be used to generate the chip connection signal SIG. CC1 ~SIG CCM .like Figure 11 As shown, the third semiconductor element 60C can be coupled to the first semiconductor element 60A and the second semiconductor element 60B via the circuit board B2, so the first semiconductor element 60A and the second semiconductor element 60B can receive the operation signal SIG transmitted by the third semiconductor element 60C. OP1 ~SIG OPN and the chip connection signal SIG CC1 ~SIG CCM This allows for the execution of multiple operations and the adjustment of the capacitance values ​​of the electrostatic discharge protection units 630A1 to 630AN and 630B1 to 630AN accordingly.

[0169] In some embodiments, electronic components 60A and 60B may include multiple semiconductor chips. For example, such as... Figure 7 The electronic component 50 shown replaces electronic components 60A and / or 60B. In this example, since the memory controller MC1 still knows the total number of semiconductor chips in the electronic system 7 coupled together to operate in parallel, the memory controller MC1 can generate a chip connection signal SIG accordingly. CC1 ~SIG CCM To further reduce the electrostatic discharge protection units 630A1~630AN and 630B1~630BN.

[0170] Furthermore, such as Figure 11As shown, the third semiconductor element 60C and the first semiconductor element 60A are laterally disposed on a first surface of the circuit board B2, while the second semiconductor element 60B is disposed on a second surface of the circuit board B2. However, in some other embodiments, the electronic system 7 includes a different number of semiconductor elements, and those semiconductor elements can be configured in different ways. For example, in some embodiments, the second semiconductor element 60B may be omitted from the electronic system 7, and the third semiconductor element 60C may be disposed on the second surface of the circuit board B2. That is, the third semiconductor element 60C and the first semiconductor element 60A can be coupled back-to-back via the circuit board B2. Furthermore, in this example, since the number of the plurality of semiconductor chips coupled together to operate in parallel is reduced, the chip connection signal SIG generated by the memory controller MC1 of the third semiconductor element 60C is less. CC1 ~SIG CCM It may also differ from the aforementioned examples. Figure 11 As shown in the embodiment, the logic circuit 650A can adjust the capacitance values ​​of the electrostatic discharge protection units 630A1 to 630AN according to the actual state of the chip connection.

[0171] Figure 12 This is a flowchart illustrating an electrostatic discharge (ESD) protection method 800 for a semiconductor device according to an embodiment of this disclosure. In some embodiments, the ESD protection method 800 can be applied to, for example... Figure 9 and Figure 10 The semiconductor element 60A is shown. For example, in step S810, electrostatic discharge protection units 630A1 to 630AN can be formed in the semiconductor chip 600A of the semiconductor element 60A. Figure 10 As shown, each electrostatic discharge protection unit 630A1 to 630AN is coupled between a voltage terminal VT and a corresponding operating electrical contact 610A1 to 610AN. The voltage terminal VT can be coupled to a grounding point GND or a power supply voltage VDD. In some embodiments, the electrostatic discharge protection units 630A1 to 630AN can be coupled using methods such as... Figure 3 The electrostatic discharge protection unit 130A1 or 130B1 shown is used. However, in some other embodiments, the electrostatic discharge protection units 6301 to 630AN can be implemented by adopting, for example, […]. Figure 4 The electrostatic discharge protection unit 230 shown is as follows: Figure 5 The electrostatic discharge protection unit 330 shown is or is as follows Figure 6 The electrostatic discharge protection unit 430 shown is implemented as described.

[0172] Furthermore, in step S820, the first semiconductor element 60A can be coupled to, for example... Figure 9The circuit board B1 is shown, so the first semiconductor element 60A can be coupled to the second semiconductor element 60B via the circuit board B1. In some embodiments, the first semiconductor element 60A and the second semiconductor element 60B may include memory circuits with different arrangements. In this example, in step S830, the operation signal SIG... OP1 ~SIG OPN The signal can be transmitted to the first semiconductor element 60A and the second semiconductor element 60B via the circuit board B1, and the first semiconductor element 60A and the second semiconductor element 60B can respond to the operation signal SIG. OP1 ~SIG OPN Multiple operations can be executed in parallel.

[0173] Furthermore, in step S840, the capacitance values ​​of the electrostatic discharge protection units 630A1 to 630AN of the semiconductor chip 600A can be determined based on the received operation signal SIG. OP1 ~SIG OPN The total number of the multiple semiconductor chips operating in parallel can be adjusted. For example, if each electrostatic discharge (ESD) protection unit 630A1-630AN includes multiple ESD protection elements coupled between a voltage terminal VT and a corresponding operating electrical contact 610A1-610AN, then the logic circuit 650A can disconnect at least one ESD protection element from the corresponding operating electrical contact or voltage terminal VT by turning off some switches in the ESD protection units 630A1-630AN or by blowing some fuses in the ESD protection units 630A1-630AN. Therefore, the capacitance values ​​of the ESD protection units 630A1-630AN and 630B1-630BN of the semiconductor chip 600A can be adjusted.

[0174] Furthermore, in this embodiment, the operation signal SIG is received. OP1 ~SIG OPN Furthermore, the semiconductor chip operating in parallel with the first semiconductor chip 600A is in the second semiconductor element 60B, and is connected via, as shown in... Figure 9 The circuit board B1 shown is coupled to the first semiconductor element 60A. However, in some embodiments, the semiconductor element 60A may include more than one semiconductor chip. In this example, when calculating the received operation signal SIG... OP1 ~SIG OPN Furthermore, the total number of the multiple semiconductor chips operating in parallel will be included in all of the multiple semiconductor chips in semiconductor element 60A.

[0175] In summary, the electrostatic discharge (ESD) protection method for the semiconductor chip, the semiconductor element, and the semiconductor element can adjust the capacitance values ​​of the plurality of ESD protection units according to system requirements. Therefore, when multiple semiconductor chips are stacked or coupled together for parallel operation, signal distortion caused by the capacitance values ​​of the plurality of ESD protection units of those semiconductor chips can be reduced, thereby shortening the rise time and fall time of the plurality of signals and improving the transmission quality of the plurality of signals.

[0176] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0177] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One base; An operating solder structure is disposed on a first surface of the substrate and configured to receive an operating signal; A solder detection structure is disposed on the first surface of the substrate and configured to receive a chip connection signal; as well as A first semiconductor chip is disposed on a second surface of the substrate and includes: A first operational electrical contact is coupled to the operational solder structure via the substrate; A first detection electrical contact point is coupled to the detection solder structure via the substrate; A first electrostatic discharge protection unit is coupled to the first operating electrical contact; and A first logic circuit is coupled to the first detection electrical contact and configured to adjust the capacitance value of the first electrostatic discharge protection unit according to the chip connection signal. The first electrostatic discharge protection unit includes: A first electrostatic discharge protection element is coupled between the first operating electrical contact and a voltage terminal; A second electrostatic discharge protection element; and A control circuit is connected in series with the second electrostatic discharge protection element and coupled between the first operating electrical contact and the voltage terminal; The voltage terminal is coupled to a ground or a power supply voltage.

2. The semiconductor element of claim 1, wherein the first semiconductor chip further includes a memory circuit configured to perform a plurality of operations in accordance with at least the operation signal.

3. The semiconductor device of claim 1, wherein the control circuit includes a switch, and the first logic circuit is configured to turn the switch on or off, thereby adjusting the capacitance value of the first electrostatic discharge protection unit.

4. The semiconductor device of claim 1, wherein the control circuit includes a fuse, and the first logic circuit is configured to blow the fuse, thereby reducing the capacitance value of the first electrostatic discharge protection unit.

5. The semiconductor element of claim 1, further comprising a second semiconductor chip, laterally adjacent to the first semiconductor chip and disposed on the second surface of the substrate or stacked on the first semiconductor chip, wherein the second semiconductor chip comprises: A second operational electrical contact is coupled to the operational solder structure; A second electrical contact point is coupled to the solder structure for testing; A second electrostatic discharge protection unit is coupled to the second operating electrical contact point; as well as A second logic circuit is coupled to the second detection electrical contact and configured to adjust the capacitance value of the second electrostatic discharge protection unit according to the chip connection signal.

6. An electronic system, comprising: A circuit board; as well as A first semiconductor element, coupled to the circuit board, includes: A first base; A first operating solder structure is disposed on a first surface of the first substrate and configured to receive a first operating signal; A first solder detection structure is disposed on the first surface of the first substrate and configured to receive a first chip connection signal; and A first semiconductor chip is disposed on a second surface of the first substrate and includes: A first operating electrical contact point is coupled to the first operating solder structure; A first detection electrical contact point is coupled to the first detection solder structure; A first electrostatic discharge protection unit is coupled to the first operating electrical contact; and A first logic circuit is coupled to the first detection electrical contact and configured to adjust the capacitance value of the first electrostatic discharge protection unit according to a signal connected by at least the first chip; wherein the first electrostatic discharge protection unit includes: A first electrostatic discharge protection element is coupled between the first operating electrical contact and a voltage terminal, wherein the voltage terminal is coupled to a ground or a power supply voltage. A second electrostatic discharge protection element; and A control circuit is connected in series with the second electrostatic discharge protection element and coupled between the first operating electrical contact and the voltage terminal.

7. The electronic system of claim 6, wherein the first semiconductor element further comprises a second semiconductor chip, laterally adjacent to the first semiconductor chip and disposed on the second surface of the first substrate or stacked on the first semiconductor substrate, wherein the second semiconductor chip comprises: A second operational electrical contact is coupled to the first operational solder structure; A second detection electrical contact point is coupled to the first detection solder structure; A second electrostatic discharge protection unit is coupled to the second operating electrical contact point; as well as A second logic circuit is coupled to the second detection electrical contact and configured to adjust the capacitance value of the second electrostatic discharge protection unit according to the first chip connection signal.

8. The electronic system of claim 6, further comprising a second semiconductor element coupled to the first semiconductor element via the circuit board, wherein: The structure of the second semiconductor element is the same as that of the first semiconductor element; The second semiconductor element and the first semiconductor element receive the first operation signal and perform multiple operations in parallel accordingly; as well as A second logic circuit of a second semiconductor chip in the second semiconductor element is configured to adjust the capacitance value of a second electrostatic discharge protection unit of the second semiconductor chip according to the first chip connection signal.

9. The electronic system of claim 8, wherein: The first semiconductor element is disposed on a first surface of the circuit board, and the second semiconductor element is disposed on a second surface of the circuit board; and The first semiconductor element and the second semiconductor element are laterally disposed on the same surface of the circuit board.

10. The electronic system of claim 6, wherein the first semiconductor chip further comprises: A memory circuit configured to perform a plurality of operations in response to at least the first operation signal.

11. The electronic system of claim 10, further comprising a third semiconductor element coupled to the first semiconductor element via the circuit board, wherein the third semiconductor element includes a memory controller configured to control the memory circuitry in the first semiconductor chip and generate the first chip connection signal.

12. The electronic system of claim 11, wherein: The first semiconductor element is disposed on a first surface of the circuit board, and the second semiconductor element is disposed on a second surface of the circuit board; Or The first semiconductor element and the second semiconductor element are laterally disposed on the same surface of the circuit board.

13. The electronic system of claim 6, wherein the control circuit includes a switch, and the first logic circuit is configured to turn the switch on or off, thereby adjusting the capacitance value of the first electrostatic discharge protection unit.

14. The electronic system of claim 6, wherein the control circuit includes a fuse, and the first logic circuit is configured to blow the fuse, thereby reducing the capacitance value of the first electrostatic discharge protection unit.

15. A method for electrostatic discharge protection of a first semiconductor device, wherein the first semiconductor device includes a substrate; and an operational solder structure disposed on a first surface of the substrate; And a first semiconductor chip, disposed on a second surface of the substrate; Furthermore, this electrostatic discharge protection method includes: An electrostatic discharge protection unit is formed in the first semiconductor chip, wherein the electrostatic discharge protection unit is coupled between a voltage terminal and an operating electrical contact of the first semiconductor chip via the substrate to the operating solder structure, and the voltage terminal is coupled to a ground or a power supply voltage. The first semiconductor element is coupled to a circuit board; An operation signal is transmitted to the operation solder structure via the circuit board; and The capacitance values ​​of the multiple electrostatic discharge protection units are adjusted based on the total number of multiple first semiconductor chips that transmit the operation signal and operate in parallel with the first semiconductor chip.

16. The electrostatic discharge protection method of claim 15, wherein the electrostatic discharge protection unit comprises a plurality of electrostatic discharge protection elements coupled between the operating electrical contact and the voltage terminal, and transmitting the operating signal and adjusting the capacitance value of the plurality of electrostatic discharge protection units by a total number of a plurality of first semiconductor chips operating in parallel with the first semiconductor chip, comprising: Disconnect at least one electrostatic discharge protection element from the operating electrical contact or the voltage terminal.

17. The electrostatic discharge protection method of claim 15, wherein one of the semiconductor chips that transmits the operation signal and operates in parallel with the first semiconductor chip is in the first semiconductor element or in a second semiconductor element coupled to the first semiconductor element via the circuit board.

18. The electrostatic discharge protection method of claim 17, wherein the first semiconductor element and the second semiconductor element comprise memory circuits arranged in different orders.

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