Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composite barrier layer. The buffer layer is on the substrate. The channel layer is on the buffer layer. The barrier layer is on the channel layer. The doped compound semiconductor layer is on the barrier layer. The composite barrier layer is on the doped compound semiconductor layer, the composite barrier layer and the barrier layer include the same group III element, and an atomic percentage of the same group III element in the composite barrier layer increases as the composite barrier layer moves away from the doped compound semiconductor layer.

Description

Technical Field

[0001] The present invention relates to semiconductor structures, and more particularly to semiconductor structures having a composite barrier layer. Background Technology

[0002] Gallium nitride (GaN)-based semiconductor materials possess many excellent material properties, such as high heat resistance, wide bandgap, high electron saturation velocity, and good heat dissipation. GaN-based semiconductor materials are suitable for high-frequency operation and high-temperature environments. In recent years, GaN-based semiconductor materials have been applied to fast-charging devices, power supply modules for wireless communication base stations, electric vehicle components, and other devices with heterogeneous interface structures for high electron mobility transistors (HEMTs).

[0003] High electron mobility transistors (HFETs), also known as heterostructure field-effect transistors or modulation-doped field-effect transistors (MODFETs), involve semiconductor materials with different energy gaps, creating a two-dimensional electron gas (2DEG) layer at the interface between adjacent semiconductor materials. During fabrication, HFETs can be affected by process techniques (such as doping or etching), leading to deterioration in electrical performance or uniformity. Therefore, developing structures that further improve the performance and reliability of HFET devices remains a key research focus in the industry. Summary of the Invention

[0004] This invention provides a semiconductor structure comprising: a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on the barrier layer; and a composite barrier layer on the doped compound semiconductor layer, wherein the composite barrier layer and the barrier layer contain the same Group 3 element, and the atomic percentage of the same Group 3 element in the composite barrier layer increases with distance from the doped compound semiconductor layer.

[0005] In some embodiments, the composite barrier layer includes a first barrier layer and a second barrier layer located on the first barrier layer.

[0006] In some embodiments, the composite barrier layer further includes a third barrier layer located between the first barrier layer and the second barrier layer.

[0007] In some embodiments, the second barrier layer comprises AlN or Al x Ga(1-x) N, where 0 <x<1。

[0008] In some embodiments, the first barrier layer, the second barrier layer, and the third barrier layer are each p-type doped or undoped.

[0009] The semiconductor structure provided in this embodiment of the invention includes a composite barrier layer, which can prevent the memory effect of dopants in the doped compound semiconductor layer and prevent carriers therein from migrating to adjacent components, thereby avoiding leakage current and carrier trapping. The composite barrier layer in this embodiment of the invention can also serve as a protective layer and an etch stop layer. In some embodiments, the semiconductor structure further includes a capping layer disposed on the composite barrier layer, which can improve the stacking quality of the overlying film layers. Attached Figure Description

[0010] The embodiments of the invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the invention.

[0011] Figures 1-4 The present invention provides some embodiments thereof, which illustrate cross-sectional views of a semiconductor structure.

[0012] Figures 5-9 This is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

[0013] Figure 10 Cross-sectional views of a semiconductor structure are shown in some other embodiments of the present invention.

[0014] Attached icon number

[0015] 10, 20, 30: Semiconductor Structure

[0016] 100:Substrate

[0017] 100a: Ceramic substrate

[0018] 100b: Substrate barrier layer

[0019] 101: Nucleation layer

[0020] 102: Buffer layer

[0021] 102a: Ceramic substrate

[0022] 102b: Substrate barrier layer

[0023] 104: Channel Layer

[0024] 106: Barrier Layer

[0025] 108: Doped compound semiconductor layer

[0026] 110: Composite barrier layer

[0027] 110a: First barrier layer

[0028] 110b: Second barrier layer

[0029] 110c: Third barrier layer

[0030] 112: Cap layer

[0031] 112a: First nitride layer

[0032] 112b: Second nitride layer

[0033] 114: Source / Drain Components

[0034] 116: Passivation layer

[0035] 118: Gate component Detailed Implementation

[0036] The following description provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, embodiments of the invention may use repeated element symbols in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0037] Furthermore, in some embodiments of the present invention, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Moreover, these terms regarding joining and connecting may also include cases where both structures are movable or both structures are fixed.

[0038] Furthermore, spatially relative terms may be used, such as "below," "under," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0039] The terms "about," "approximately," and "roughly" as used herein generally indicate within ±20%, preferably ±10%, and even more preferably ±5%, or ±3%, or ±2%, or ±1%, or 0.5%, of a given value. For example, the term "about 5nm" can cover a size range from 4.5nm to 5.5nm. The values ​​given in this text are approximate, meaning that unless specifically stated otherwise, these given values ​​may imply the meaning of "about," "approximately," or "roughly."

[0040] The following describes some embodiments of the invention, in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. The semiconductor structure of the embodiments of the invention may have additional components added. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0041] Some embodiments of the present invention provide semiconductor structures with composite barrier layers, which can avoid the adverse effects of doping, etching, or other processes on the semiconductor structure and further improve electrical performance. Furthermore, in some embodiments, the semiconductor structure has a capping layer, which, in addition to protecting other components, allows for adjustments to the configuration of the capping layer according to different process or design requirements.

[0042] Figure 1This is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present invention. The semiconductor structure 10 includes a substrate 100, a buffer layer 102, a channel layer 104, a barrier layer 106, a doped compound semiconductor layer 108, and a composite blocking layer 110. The substrate 100 may include: elemental (single element) semiconductors, such as silicon (Si) or germanium (Ge); compound semiconductors, such as silicon carbide, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP).

[0043] In some embodiments, substrate 100 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina (Al2O3) substrate (or sapphire substrate), a glass substrate, or other similar substrates. In some embodiments, substrate 100 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may contain a ceramic material, and the ceramic material may contain a metallic inorganic material. For example, the ceramic substrate may contain: silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina. In other embodiments, substrate 100 may be a semiconductor-on-insulator (SGOI) substrate, such as: silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI).

[0044] In semiconductor structures, the lattice structure, coefficient of thermal expansion, or other material properties of the substrate may differ from those of the components above it (e.g., channel layer 104 or other components). Therefore, strain may occur at or near the interface between the substrate and the components above it, leading to defects such as cracks or warping. In some embodiments, a buffer layer 102 is disposed on the substrate 100 to mitigate strain in the components (e.g., channel layer 104) formed above the buffer layer 102, thereby preventing defect formation. The material of the buffer layer 102 may include AlN, GaN, Al... x Ga 1-xN (where 0 < x < 1), the aforementioned combination, or other similar materials. The buffer layer 102 can be formed by an epitaxial growth process, such as: metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), the aforementioned combination, or other methods.

[0045] In some embodiments, the channel layer 104 is disposed on the buffer layer 102, and the material of the channel layer 104 includes one or more group III-V compound semiconductor materials, such as group III nitrides. For example, the material of the channel layer 104 can include: GaN, AlGaN, AlInN, InGaN, InAlGaN, other suitable materials, or the aforementioned combination. In some embodiments, the channel layer 104 can be doped with an n-type dopant or a p-type dopant. The channel layer 104 can be formed by metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), atomic layer deposition (ALD), other suitable methods, or the aforementioned combination.

[0046] In some embodiments using a GaN layer as the channel layer, the breakdown voltage of the high electron mobility transistor mainly depends on the thickness of the GaN layer. For example, increasing the thickness of the GaN layer can effectively increase the breakdown voltage of the high electron mobility transistor. In such embodiments, in order to deposit GaN material on the substrate during the process of forming the GaN layer, a substrate with high thermal conductivity and high mechanical strength is required, otherwise the substrate may bend or even break. For example, compared with a silicon (Si) substrate, an AlN substrate has higher thermal conductivity and mechanical strength, so a thicker GaN layer can be formed on the AlN substrate to avoid substrate bending or breaking. It should be noted that the foregoing use of an AlN substrate and forming a GaN layer thereon is only an example and does not limit the substrate or the material of the channel layer used in the embodiments of the present invention. According to different process conditions and design requirements, a GaN layer or a channel layer including other materials can be formed on other substrates.

[0047] In some embodiments, a barrier layer 106 is disposed on the channel layer 104, and the material of the barrier layer 106 includes a ternary III-V compound semiconductor, such as a group III nitride. For example, the material of the barrier layer 106 may be AlGaN, AlInN, or a combination thereof. In other embodiments, the material of the barrier layer 106 includes GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable group III-V materials, or a combination thereof. In some embodiments, the barrier layer 106 may be doped, for example, with n-type or p-type dopant. The barrier layer 106 may be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, a combination thereof, or other methods.

[0048] According to some embodiments of the present invention, the channel layer 104 and the barrier layer 106 are made of different materials, and their interface is a heterojunction. Therefore, the lattice mismatch between the channel layer 104 and the barrier layer 106 may generate stress, leading to piezoelectric polarization. Furthermore, the strong ionicity of the bond between group III metals (e.g., Al, Ga, or In) and nitrogen results in spontaneous polarization. Due to the different energy gaps between the channel layer 104 and the barrier layer 106, and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown) is formed at the heterojunction between the channel layer 104 and the barrier layer 106. In some embodiments, the semiconductor structure includes a high electron mobility transistor (HEMT) utilizing the two-dimensional electron gas (2DEG) as a conductive carrier.

[0049] Reference Figure 1In some embodiments, the semiconductor structure 10 includes a multilayer stack (or multilayer mesa) formed by a doped compound semiconductor layer 108 disposed on a barrier layer 106 and a composite barrier layer 110 disposed on the doped compound semiconductor layer 108. In some embodiments, the doped compound semiconductor layer 108 includes a p-type doped III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or other III-V semiconductors. In other embodiments, the doped compound semiconductor layer 108 includes a p-type doped II-VI semiconductor, such as CdS, CdTe, ZnS, or other II-VI semiconductors. The doped compound semiconductor layer 108 may be formed by metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, a combination of the foregoing, or other methods. In some embodiments, the doped compound semiconductor layer 108 may be doped, for example, with dopants including magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), carbon (C), silver (Ag), gold (Au), lithium (Li), or sodium (Na), to make the doped compound semiconductor layer 108 p-type doped. In some embodiments, the doping concentration of the doped compound semiconductor layer 108 is approximately 1E19 cm⁻¹. -3 Approximately 4E19cm -3 For example, approximately 2.8E19cm -3 .

[0050] In semiconductor structures, carriers in doped components may migrate to neighboring components due to potential energy differences between different components, applied voltages during operation, or other process / operational conditions, causing adverse effects. For example, carriers in a doped compound semiconductor layer may migrate to the subsequently formed gate component due to the aforementioned effects, leading to leakage and carrier trapping. Furthermore, dopants in doped components may diffuse to neighboring components, causing the aforementioned adverse effects, such as leakage and carrier trapping. During gate switching, trapped carriers cause a threshold voltage shift (V0). TThis can reduce gate switching efficiency, potentially increasing the time required for device turn-on and causing gate lag. Generally, the doping concentration of a doped compound semiconductor layer is positively correlated with the concentration of carriers affected by its migration to and diffusion into neighboring components. However, the predetermined critical voltage of the device depends primarily on the doping concentration of the doped compound semiconductor layer. Adjusting the doping concentration of the doped compound semiconductor layer to avoid leakage and carrier trapping will alter the predetermined critical voltage. This will prevent the device from achieving the performance required by its design. On the other hand, if the doping concentration of the doped compound semiconductor layer is relatively high, such as 2.8E19cm⁻¹, the gate switching efficiency will be reduced. -3 Although it can achieve the required critical voltage (Vt), it is also prone to high gate leakage current and gate delay. Therefore, a composite doped compound semiconductor layer is needed to eliminate this side effect.

[0051] According to some embodiments of the present invention, a composite barrier layer 110 disposed on a doped compound semiconductor layer 108 can suppress gate leakage current caused by high concentrations of dopants (e.g., high concentrations of magnesium or other p-type dopants). In some embodiments, the composite barrier layer 110 and the barrier layer 106 contain the same Group III element (or Group III element), and the atomic percentage of the same Group III element in the composite barrier layer 110 increases with distance from the doped compound semiconductor layer 108. In other words, the composite barrier layer 110 has an increasing Group III element concentration gradient in the direction away from the doped compound semiconductor layer 108. The composite barrier layer 110 can be formed by metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or combinations thereof. In one embodiment, the composite barrier layer 110 is grown in situ in the process chamber for metal-organic chemical vapor deposition of the doped compound semiconductor layer 108. In some embodiments, the process of forming the doped compound semiconductor layer 108 and the composite barrier layer 110 includes: sequentially depositing a doped compound semiconductor material layer and a composite barrier material layer on the barrier layer 106, and patterning the doped compound semiconductor material layer and the composite barrier material layer to expose the barrier layer 106, thereby forming a multilayer stack or multilayer platform of the doped compound semiconductor layer 108 and the composite barrier layer 110. The patterning process includes (but is not limited to): photolithography and etching. In some embodiments, the photolithography process may include photoresist coating, soft baking, hard baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying, or other suitable processes. In some embodiments, the etching process may include dry etching, wet etching, or a combination thereof. For example, the dry etching process may include reactive ion etching (RIE) or plasma etching, etc. In some embodiments where the doped compound semiconductor layer 108 is doped with magnesium or other p-type dopants, the composite barrier layer 110 can interrupt the growth of magnesium or other p-type dopants (i.e., effectively block dopant diffusion) and block the memory effect of magnesium or other dopants, thereby effectively achieving a lower doping concentration of magnesium or other p-type dopants than that of the doped compound semiconductor layer to improve electrical performance. In some embodiments, the doping concentration of the doped compound semiconductor layer 108 is approximately 1E19 cm⁻¹. -3 Approximately 4E19cm -3 For example, approximately 2.8E19cm -3, the doping concentration of the composite barrier layer 110 is about 5E17 cm -3 to about 5E18 cm -3 , for example, about 2E18 cm -3 .

[0052] Figures 2-4 FIG. is a cross-sectional view of the composite barrier layer 110 according to some embodiments of the present invention. In these embodiments, the composite barrier layer 110 includes at least two layers and respectively contains group III elements. For example, the group III elements may include boron (B), aluminum (Al), gallium (Ga), or indium (In), or other group III elements. Referring to Figure 2 , in some embodiments, the composite barrier layer 110 includes a first barrier layer 110a and a second barrier layer 110b thereon. The first barrier layer 110a and the second barrier layer 110b can be sequentially formed by metalorganic chemical vapor deposition, hydride vapor epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or a combination of the foregoing. In some embodiments, the atomic percentage of the group III element in the second barrier layer 110b increases as it moves away from the doped compound semiconductor layer 108. In some embodiments, the first barrier layer 110a can be an AlGaN layer and the second barrier layer 110b can be an AlN layer or an Al x Ga (1-x) N layer (0 < x < 1). In some embodiments, the value of x representing the aluminum content in the Al x Ga (1-x) N layer can be a variable, and the value of x increases in the direction away from the doped compound semiconductor layer 108 (the range of the x value is still between 0 and 1, that is, 0 < x < 1). In other words, Al x Ga (1-x)The N-layer has an aluminum concentration gradient. In some embodiments, the composite barrier layer 110, having an aluminum (or other Group III element) concentration gradient, can provide a stress buffer between the layers above and below it to mitigate or prevent cracking at the interface between the layers due to differences in materials, lattice, or other factors between the layers above and below; it can also eliminate polarization between the barrier layer and the doped compound semiconductor layer, preventing additional carrier trapping. In some embodiments, the composite barrier layer 110 is p-type doped or undoped. For example, the first barrier layer 110a may be p-type doped or undoped, and the second barrier layer 110b may be p-type doped or undoped. In embodiments where the composite barrier layer 110 is p-type doped, the doping concentration of the composite barrier layer 110 is much smaller than the doping concentration of the doped compound semiconductor layer 108; for example, the doping concentration of the composite barrier layer 110 is one to two orders of magnitude smaller than the doping concentration of the doped compound semiconductor layer 108. In these embodiments, the doping concentration of the first barrier layer 110a is approximately 5E17 cm⁻¹. -3 Approximately 5E18cm -3 For example, approximately 2E18cm -3 The doping concentration of the second barrier layer 110b is approximately 2E17cm. -3 Approximately 2E18cm -3 (e.g., approximately 8E17cm) -3 (or approximately 5E16cm) -3 Approximately 5E17cm -3 (for example, approximately 2E17cm) -3 It should be noted that in some embodiments, the term "undoped component" refers to a component that has not been doped using diffusion or ion implantation processes. However, during subsequent processes, dopants may inadvertently diffuse into the component, resulting in a low or negligible doping concentration.

[0053] Reference Figure 3 In some embodiments, the composite barrier layer 110 includes a first barrier layer 110a, a third barrier layer 110c on the first barrier layer 110a, and a second barrier layer 110b on the third barrier layer 110c. In these embodiments, the third barrier layer 110c is located between the first barrier layer 110a and the second barrier layer 110b. The first barrier layer 110a, the third barrier layer 110c, and the second barrier layer 110b can be formed sequentially by metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or combinations thereof. In some embodiments, overall, Figure 3The atomic percentage of one of the group III elements in the composite barrier layer 110 increases as it moves away from the doped compound semiconductor layer 108, thereby providing a stress buffer between the film layers. For example, in some embodiments, the first barrier layer 110a is an AlGaN layer, the third barrier layer 110b is an Al x Ga (1-x) N layer (where 0 < x < 1), and the second barrier layer 110b is an AlN layer, where the Al x Ga (1-x) N layer (0 < x < 1) has an increasing x value in the direction away from the doped compound semiconductor layer 108, and the Al concentration (percentage) of the Al x Ga (1-x) N layer is higher than that of the AlGaN layer to provide stress buffering. Additionally, in some embodiments, the second barrier layer 110b (such as an AlN layer or a layer with other group III elements) can more effectively interrupt the growth of magnesium or other p-type dopants, blocking the memory effect of magnesium or other dopants to achieve better electrical performance. In some embodiments, the first barrier layer 110a, the second barrier layer 110b, and the third barrier layer 110c are each p-type doped or undoped. In some embodiments, the doping concentration of the first barrier layer 110a can be from about 5E17 cm -3 to about 5E18 cm -3 , such as about 2E18 cm -3 , the doping concentration of the third barrier layer 110c is from about 5E16 cm -3 to about 5E17 cm -3 , such as about 2E17 cm -3 , the doping concentration of the second barrier layer 110b can be from about 2E17 cm -3 to about 2E18 cm -3 , such as about 8E17 cm -3 . In some embodiments, the atomic percentage of one of the group III elements in the third barrier layer 110c is higher than that of this group III element in the first barrier layer 110a.

[0054] Referring to Figure 4 , in some embodiments, the composite barrier layer 110 includes the first barrier layer 110a and the third barrier layer 110c thereon. In some embodiments, the first barrier layer 110a and the third barrier layer 110c can be sequentially formed by metal-organic chemical vapor deposition, hydride vapor epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or a combination of the foregoing. In some embodiments, the first barrier layer 110a can provide stress buffering between the third barrier layer 110c and the doped compound semiconductor layer 108. According to some embodiments, the first barrier layer 110a is an AlGaN layer and the third barrier layer 110c is an Alx Ga (1-x) an N layer (where 0 < x < 1). In some embodiments, the composite barrier layer 110 is p-type doped or undoped. For example, the first barrier layer 110a can be p-type doped or undoped and the third barrier layer 110c can be p-type doped or undoped. In an embodiment where the first barrier layer 110a is p-type doped, its doping concentration is about 5E17 cm -3 to about 5E18 cm -3 , such as about 2E18 cm -3 . In an embodiment where the third barrier layer 110c is p-type doped, its doping concentration is about 5E16 cm -3 to about 5E17 cm -3 , such as about 2E17 cm -3 . Compared with a barrier layer composed of a single layer or a single material, the composite barrier layer in some embodiments of the present invention can better block the memory effect of dopants and can better prevent carriers from moving from the doped compound semiconductor layer to adjacent components, resulting in leakage and carrier capture.

[0055] Figure 5 FIG. is a cross-sectional view showing a semiconductor structure 20 according to other embodiments of the present invention. The semiconductor structure 20 is similar to Figure 1 the semiconductor structure 10, and the semiconductor structure 20 further includes a cap layer 112 disposed on the composite barrier layer 110. The cap layer 112 can include one or more nitride layers. In some embodiments, the cap layer 112 includes a p-type doped or undoped gallium nitride (GaN) layer, which can improve the surface morphology of the semiconductor structure 20. For example, the GaN layer can be disposed on the top surface of the composite barrier layer 110 (such as on the second barrier layer 110b or the third barrier layer 110c), reducing the surface roughness of the semiconductor structure 20 to improve the quality of the film stack formed thereon subsequently. In some embodiments, the cap layer 112 includes a p-type doped or undoped silicon nitride (SiN) layer, and the SiN layer can be disposed on the top surface of the composite barrier layer 110 (such as on the second barrier layer 110b or the third barrier layer 110c) to passivate the surface of the composite barrier layer 110. According to some embodiments, the cap layer 112 includes a first nitride layer 112a and a second nitride layer 112b on the first nitride layer 112a. For example, the first nitride layer 112a includes GaN and the second nitride layer 112b includes SiN. In some embodiments, the cap layer 112 includes a p-type doped or undoped first nitride layer 112a and a p-type doped or undoped second nitride layer 112b on the first nitride layer 112a, as Figure 6As shown. For example, the material of the first nitride layer 112a may include GaN or other suitable materials; the material of the second nitride layer 112b may include SiN or other suitable materials. In some embodiments, the thickness of the first nitride layer 112a is about 1 nm to 10 nm, and the thickness of the second nitride layer 112b is about 2 nm to 20 nm.

[0056] Figures 7-8 This is a cross-sectional view of the buffer layer 102 according to other embodiments of the present invention. In these embodiments, the buffer layer 102 includes at least one superlattice layer. (Refer to...) Figure 7 In some embodiments, the buffer layer 102 includes a first superlattice layer 102a and a second superlattice layer 102b, wherein the first superlattice layer 102a and the second superlattice layer 102b have different periods, which can further alleviate the lattice difference between the substrate 100 and other films formed thereon, thereby avoiding defects such as warpage or cracks caused by lattice mismatch during the formation of these films. According to some embodiments, the buffer layer 102 includes a first superlattice layer 102a and a second superlattice layer 102b stacked in pairs, the first superlattice layer 102a having tensile stress and the second superlattice layer 102b having compressive stress. In some embodiments, the first superlattice layer 102a and the second superlattice layer 102b are stacked along a direction perpendicular to the main surface S of the substrate 100. It should be noted that the number of superlattice layers shown in the figures is only an example; depending on the film material above the substrate 100 and / or the process of forming these materials, the number of superlattice layers can be one or more. (Refer to...) Figure 8 In some embodiments, the buffer layer 102 further includes an impedance layer 102c disposed on the superlattice layer. In these embodiments, the impedance layer 102c serves as an electrically impedance layer to reduce leakage current. In some embodiments, the impedance layer 102c is a binary or ternary III-V compound. In some embodiments, the impedance layer 102c is a carbon- or iron-doped GaN layer with a doping concentration of approximately 6E18 cm⁻¹. -3 Approximately 6E19cm -3 For example, approximately 4E19cm -3 .

[0057] Figure 9This is a cross-sectional view of a semiconductor structure 20 according to another embodiment of the present invention, wherein a substrate 100 includes a ceramic substrate 100a and a pair of substrate barrier layers 100b respectively disposed on the upper and lower surfaces of the ceramic substrate 100a. In some embodiments, the substrate barrier layers 100b located on the upper and lower surfaces of the ceramic substrate 100a include a single or multiple layers of insulating material and / or other suitable material layers, such as semiconductor layers. The insulating material layer may be an oxide, nitride, oxynitride, or other suitable insulating material. The semiconductor layer may be polycrystalline silicon. The substrate barrier layers 100b prevent diffusion between the ceramic substrate 100a and other components, and may also prevent the ceramic substrate 100a from interacting with other film layers or process environments. In some embodiments, the substrate barrier layers 100b may also encapsulate the ceramic substrate 100a. In these embodiments, the substrate barrier layers 100b cover not only the upper and lower surfaces of 100a, but also the side surfaces of 100a.

[0058] Figure 10 This is a cross-sectional view of a semiconductor structure 30 according to some embodiments of the present invention. The semiconductor structure 30 includes: a substrate 100, a nucleation layer 101, a buffer layer 102, a channel layer 104, a barrier layer 106, a doped compound semiconductor layer 108, a recombination barrier layer 110, a gate component 118, and a source / drain component 114. The buffer layer 102 of the semiconductor structure 30 includes a first superlattice layer 102a, a second superlattice layer 102b, and an impedance layer 102c. The recombination barrier layer 110 of the semiconductor structure 30 includes a first barrier layer 110a and a third barrier layer 110c. It should be noted that, according to some embodiments of the present invention, the buffer layer 102 of the semiconductor structure 30 may also be as follows: Figure 7 The two layers shown or at least one layer described above; the composite barrier layer 110 of the semiconductor structure 30 may also be as follows Figure 2 or Figure 3The composite barrier layer is shown. A gate component 118 is disposed on the composite barrier layer 110, and source / drain components 114 are disposed on both sides of the gate component 118. The composite barrier layer 110 can achieve dopant growth interruption of the doped compound semiconductor layer 108, preventing dopant from diffusing to the gate component 118 (e.g., to the gate metal layer in the gate component 118) or other components, thereby achieving a zero or low dopant concentration surface in other components, which is beneficial for reducing leakage current and carrier trapping, thereby avoiding gate delay and improving electrical performance. In some embodiments, the source / drain components 114 extend through the barrier layer 106 into the channel layer 104. In some embodiments, the semiconductor structure 30 includes a passivation layer 116 disposed on the barrier layer 106 and the source / drain components 114. The material of the passivation layer 116 may include: SiO2, SiON, Al2O3, AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), other insulating materials, or combinations thereof. In some embodiments, the passivation layer 116 may be formed using metal-organic vapor deposition, chemical vapor deposition, spin coating, other suitable methods, or combinations thereof. In some embodiments, the process of forming the gate component 118 includes: etching through the passivation layer 116 to form an opening over the doped compound semiconductor layer 108, filling the opening with a gate metal material layer and / or other material layers, and removing excess material outside the opening. During the etching of the passivation layer 116, the composite barrier layer 110 may serve as an etch stop layer, and during the process of filling the material layer to the opening and in subsequent processes, the composite barrier layer 110 may protect the underlying doped compound semiconductor layer 108 and / or barrier layer 106.

[0059] In some embodiments, a nucleation layer 101 is disposed between the substrate 100 and the buffer layer 102. The nucleation layer 101 can alleviate lattice differences between the substrate 100 and the overly grown film layer, thereby improving crystal quality. The material of the nucleation layer may include: AlN, Al2O3, AlGaN, SiC, Al, combinations thereof, or other materials. The nucleation layer 101 can be formed into a single-layer or multi-layer structure by suitable processes, such as: chemical vapor deposition, atomic layer deposition, physical vapor deposition, other processes, or combinations thereof. In some embodiments, the material of the buffer layer 102 depends on the material of the nucleation layer 101 and the gas introduced during the epitaxial process.

[0060] The semiconductor structure provided in this embodiment of the invention includes a composite barrier layer, which can prevent the memory effect of dopants in the doped compound semiconductor layer and prevent carriers therein from migrating to adjacent components, thereby avoiding leakage current and carrier trapping. The composite barrier layer in this embodiment of the invention can also serve as a protective layer and an etch stop layer. In some embodiments, the semiconductor structure further includes a capping layer disposed on the composite barrier layer, which can improve the stacking quality of the overlying film layers.

[0061] The components of several embodiments are summarized above to enable those skilled in the art to more easily understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized by, include: One substrate; A buffer layer is located on the substrate; A channel layer is located on top of this buffer layer; A barrier layer is located above the channel layer; A doped compound semiconductor layer is located on the barrier layer; as well as A composite barrier layer is located on the doped compound semiconductor layer, wherein the composite barrier layer and the barrier layer contain at least one of the same group 3 elements, and the atomic percentage of the same group 3 element in the composite barrier layer increases with distance from the doped compound semiconductor layer.

2. The semiconductor structure of claim 1, wherein, The composite barrier layer includes a first barrier layer and a second barrier layer located on the first barrier layer.

3. The semiconductor structure of claim 2, wherein, The composite barrier layer further includes a third barrier layer located between the first barrier layer and the second barrier layer.

4. The semiconductor structure of claim 2, wherein, The second barrier layer comprises AlN or Al x Ga （1-x） N, where 0 < x < 1.

5. The semiconductor structure of claim 1, wherein, It also includes a capping layer located on the composite barrier layer.

6. The semiconductor structure of claim 5, wherein, The capping layer includes a first nitride layer and a second nitride layer located on the first nitride layer.

7. The semiconductor structure of claim 6, wherein, The first nitride layer comprises gallium nitride, and the second nitride layer comprises silicon nitride.

8. The semiconductor structure of claim 2, 3, or 6, wherein, The first barrier layer, the second barrier layer, the third barrier layer, the first nitride layer, or the second nitride layer are each p-type doped or undoped.

9. The semiconductor structure of claim 1, wherein, The buffer layer comprises a first superlattice layer and a second superlattice layer stacked in pairs, the first superlattice layer having tensile stress and the second superlattice layer having compressive stress.

10. The semiconductor structure of claim 1, wherein, Including: A gate component is located on the composite barrier layer; and A source component and a drain component are located on both sides of the gate component.

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