A soft start voltage circuit and control method, and a direct current conversion circuit

Abstract

The application relates to the technical field of circuit design, and discloses a soft-start voltage circuit and a control method and a direct-current conversion circuit. The soft-start voltage circuit comprises a capacitor charging circuit and a clamping circuit. The capacitor charging circuit comprises a current source, a first switch tube, a second switch tube and a charging capacitor. The current source, the first end of the first switch tube and the charging capacitor are sequentially connected. The other end of the current source is used for connecting a power supply voltage. The second switch tube is connected between the charging capacitor and a series connection node between the first end of the first switch tube. The control end of the first switch tube is used for inputting a square wave signal. The second switch tube is used for inputting an enable signal. The clamping circuit is connected between the current source and the series connection node between the first end of the first switch tube. The clamping circuit is used for voltage clamping of the first end of the first switch tube when the capacitor charging circuit charges the charging capacitor. The application makes the soft-start time more accurate.

Description

Technical Field

[0001] This application relates to the field of circuit design technology, and in particular to a soft-start voltage circuit and control method, and a DC-DC conversion circuit. Background Technology

[0002] In DC-DC systems, a soft-start circuit is generally required to prevent inductor current surges and output voltage overvoltage. However, soft-start circuits require a soft-start voltage. Due to the presence of parasitic capacitance, the soft-start voltage is inaccurate, resulting in inaccurate soft-start timing, which prevents the circuit from performing soft-start as expected. Summary of the Invention

[0003] In view of the above problems, this application proposes a soft-start voltage circuit and control method, and a DC-DC conversion circuit.

[0004] This application provides a soft-start voltage circuit, including: a capacitor charging circuit and a clamping circuit. The capacitor charging circuit includes a current source, a first switching transistor, a second switching transistor, and a charging capacitor. The current source, the first terminal of the first switching transistor, and the charging capacitor are connected in sequence. The other terminal of the current source is used to connect to the power supply voltage. The second switching transistor is connected to the series node between the charging capacitor and the second terminal of the first switching transistor. The control terminal of the first switching transistor is used to input a square wave signal, and the second switching transistor is used to receive an enable signal.

[0005] The clamping circuit is connected to the series node between the current source and the first terminal of the first switching transistor. The clamping circuit is used to clamp the voltage of the first terminal of the first switching transistor when the capacitor charging circuit charges the charging capacitor.

[0006] Furthermore, in the aforementioned soft-start voltage circuit, the clamping circuit includes a third switch transistor, the first terminal of which is connected to the first terminal of the first switch transistor, the second terminal of which is grounded, and the control terminal of the third switch transistor is used to input a signal opposite to the square wave signal input by the first switch transistor.

[0007] Furthermore, the soft-start voltage circuit described above also includes an inverter, the input of which is connected to the control terminal of the first switching transistor, and the output of which is connected to the control terminal of the third switching transistor.

[0008] Furthermore, in the soft-start voltage circuit described above, the clamping circuit also includes a resistor connected in series with the first or second terminal of the third switching transistor.

[0009] Furthermore, in the soft-start voltage circuit described above, the first switch and the third switch are both PMOS transistors, and the second switch is an NMOS transistor.

[0010] Furthermore, in the soft-start voltage circuit described above, the current source includes a fourth to an eighth MOS transistor. The sources of the fourth and seventh MOS transistors are respectively connected to the power supply voltage. The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor. The drain of the fifth MOS transistor is connected to the source of the sixth MOS transistor. The drain of the sixth MOS transistor is connected to the first switching transistor.

[0011] The gate of the seventh MOS transistor is connected to the gates of the fourth MOS transistor, the fifth MOS transistor, and the drain of the seventh MOS transistor; the drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor; the gate of the eighth MOS transistor is connected to the gate of the sixth MOS transistor and the drain of the eighth MOS transistor; the drain of the eighth MOS transistor is also grounded.

[0012] Another embodiment of this application also proposes a soft-start voltage circuit control method, applied to the soft-start voltage circuit as described above, the control method comprising:

[0013] When soft-start charging is required, the first switch is controlled to input the square wave signal, the second switch is controlled to input a low-level signal, and the third switch is controlled to input a signal that is completely opposite to the square wave signal.

[0014] Furthermore, in the aforementioned soft-start voltage circuit control method, the duty cycle of the low-level square wave signal is 1 / 16 to 1 / 14.

[0015] Furthermore, in the above-mentioned soft-start voltage circuit control method, when the square wave signal output is low, the first switch is turned on and the third switch is turned off, and the current source charges the charging capacitor.

[0016] When the square wave signal outputs a high level, the first switch is turned off and the third switch is turned on, and the current source stops charging the charging capacitor.

[0017] Another embodiment of this application also proposes a DC-DC conversion circuit, including the soft-start voltage circuit described above.

[0018] The embodiments of this application have the following beneficial effects:

[0019] This application proposes a soft-start voltage circuit. When the capacitor charging circuit charges the charging capacitor, the clamping circuit in the circuit clamps the voltage at the first terminal of the first switching transistor, thereby eliminating the influence of stray capacitance (parasitic capacitance) on the charging capacitor, thus improving the accuracy of the charging time of the charging capacitor, and thus improving the accuracy of the circuit soft start. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. In the various drawings, similar components are numbered similarly.

[0021] Figure 1 A schematic diagram of the first module of a soft-start voltage circuit according to some conventional implementations is shown;

[0022] Figure 2 A schematic diagram of a current source module in a soft-start voltage circuit of some conventional implementations is shown;

[0023] Figure 3 A schematic diagram of a first module of a soft-start voltage circuit according to some embodiments of this application is shown;

[0024] Figure 4 A schematic diagram of the second module of a soft-start voltage circuit according to some embodiments of this application is shown;

[0025] Figure 5 A schematic diagram of an inverter module in a soft-start voltage circuit according to some embodiments of this application is shown. Detailed Implementation

[0026] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0027] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0028] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0029] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0030] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0031] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] Typically, a common circuit for generating soft-start voltage involves charging capacitor C through a current source Ichg, generating a soft-start voltage VSS across the capacitor. VSS = Ichg * t / C. For example, if we want a 4ms soft-start time and the system reference voltage VREF = 1.25V, and Ichg = 50nA, then C = 160pF, which is too large a capacitor. By using clock logic to generate a square wave signal with a small duty cycle, if the duty cycle of the square wave signal is 1 / 16, then for only 1 / 16 of the entire 4ms time, the current charges capacitor C; the other time the switch is open and no charging occurs. This reduces the required capacitor C to 10pF, significantly reducing the cost of capacitor C.

[0033] However, the circuit described above that generates the soft-start voltage VSS through switch control has a certain flaw, resulting in inaccurate soft-start time TSS. A detailed analysis follows:

[0034] like Figure 1As shown, the current source Ichg = 50nA, and its generation circuit is generally generated by other current mirrors (0.5uA is mirrored 10:1 to generate Ichg = 50nA). The source of Q1 is connected to VDD, so its threshold voltage will be relatively large due to the body effect, plus the threshold voltage of Q1, vth = 1.6V. When CLK = 0V, Q1 is turned on, and Ichg charges CSS. Each charge lasts 500ns, and the voltage on CSS rises by about 2.5mV. At this time, the voltage of D1 remains unchanged at 1.6V. The gate is used to receive pulse signals. When CLK = VDD (generally 5V, etc.), Q1 is not turned on, and Ichg charges the parasitic capacitance Cd1 of node D1 to VDD. When CLK = 0V again, the voltage of D1 suddenly changes from VDD to 1.6V, and the capacitance of Cd1 will discharge to CSS, causing an additional charge on the capacitor CSS, which will cause the TSS time to deviate significantly from our design value. For example, assuming Cd1 = 8fF and CSS = 10pF, the voltage on Cd1 suddenly changes to VDD - 1.6V = 3.4V. This charge on Cd1 is then completely discharged onto CSS, causing the voltage on CSS to increase to 3.4V * 8fF / 10pF = 2.72mV, which is about 109% of 2.5mV. That is, CSS is charged by 2.5mV + 2.72mV per cycle, making the TSS almost half the value of our design, resulting in inaccurate soft-start time.

[0035] like Figure 2 As shown in the diagram, for the Ichg circuit, the drain nodes D3, D2, and D1 of Q4, Q5, and Q6 all contribute to the equivalent capacitance value of D1 in the above calculation. The calculation shows that even an equivalent node capacitance of only 8fF on D1 will reduce the TSS time by more than half. Furthermore, the layout and wiring of Q4, Q5, and Q6, as well as parasitic effects on other wiring (such as Q7, Q8, etc.), and the influence of changes in signals from other wiring, can easily cause a deviation of 5 to 10fF. This results in a large variation in the soft-start time during actual chip operation, and it may even change with changes in signals within the circuit.

[0036] Therefore, this application proposes a soft-start voltage circuit to solve the above problems.

[0037] Please refer to Figure 3 This is a schematic diagram of the module structure of a soft-start voltage circuit according to an embodiment of this application. Exemplarily, this soft-start voltage circuit is applied in a DC-DC module.

[0038] In some implementations, such as Figure 3As shown, a soft-start voltage circuit may include: a capacitor charging circuit 110 and a clamping circuit 120. The capacitor charging circuit 110 includes a current source I, a first switch Q1, a second switch Q2 and a charging capacitor C. The current source I, the first terminal of the first switch Q1 and the charging capacitor C are connected in sequence. The other terminal of the current source I is used to connect to the power supply voltage. The second switch Q2 is connected to the series node between the charging capacitor C and the second terminal of the first switch Q1.

[0039] Specifically, the control terminal of the first switch Q1 is used to input a square wave signal, and the second switch Q2 is used to input an enable signal. The clamping circuit 120 is connected to the series node between the current source I and the first terminal of the first switch Q1. The clamping circuit 120 is used to clamp the voltage of the first terminal of the first switch Q1 when the capacitor charging circuit 110 charges the charging capacitor C.

[0040] In some implementations, such as Figure 4 As shown, the clamping circuit 120 in the soft-start voltage circuit includes a third switch Q3. The first terminal of the third switch Q3 is connected to the first terminal of the first switch Q1, the second terminal of the third switch Q3 is grounded, and the control terminal of the third switch Q3 is used to input a signal that is opposite to the square wave signal input by the first switch Q1.

[0041] Specifically, such as Figure 4As shown, when the square wave signal of CLK is enabled, the control terminal of the second switch Q2 is input with a low level, and the soft-start circuit starts working. When CLK = 0, the first switch Q1 is turned on. Since the signal input to the control terminal of the third switch Q3 is opposite to the signal input to the control terminal of the first switch Q1, the signal input to the third switch Q3 at this time is VCC, and the third switch Q3 is turned off. If the time of CLK = 0 in each cycle is ton, then the current source I supplies the charging capacitor C. Let the current source I be Ichg and the capacitance be Css. The charging voltage is: ΔV1 = Ichg * ton / Css. The center node of the first switch Q1 and the current source I connected in series is SS_CALMP. Let the equivalent capacitance of its center node be Cd. Each time CLK = 0, the equivalent capacitance and the charging capacitor C are turned on, generating a charge sharing. The voltage change of this charging capacitor C is: ΔV2 = ΔVSS_CLAMP * Cd / Css. When CLK = VDD, the first switch Q1 is turned off, and the voltage of the charging capacitor C remains unchanged until the next cycle when CLK = 0, at which point the charging process of the previous cycle is repeated. Therefore, it can be deduced that the voltage at which the charging capacitor C is charged in each cycle is ΔV1 + ΔV2. For cases with long soft-start times, and where the soft-start voltage needs to be as linear as possible, a large step in the soft-start voltage may cause system surge voltage. Therefore, the step voltage of each cycle of the soft-start voltage is relatively small, typically only a few mV. As mentioned above, the voltage rise of a charging capacitor C is 2.5 mV, and ΔV2 is also around a few mV. Furthermore, it is affected by layout and interference from nearby signals, resulting in an inaccurate soft-start time in actual system operation, with variations exceeding 50%.

[0042] In this embodiment, the voltage of node SS_CLAMP remains constant. Due to the body effect, the threshold voltage VTH of the first switch Q1 and the third switch Q3 is very large, generally greater than 1.5V. SS_CLAMP is clamped at the VTH voltage throughout the entire cycle, so ΔV2 = 0. Therefore, the soft-start voltage is only ΔV1, which makes the soft-start voltage more accurate.

[0043] Optionally, the first switch Q1 and the third switch Q3 are both PMOS transistors, and the second switch Q2 is an NMOS transistor. Of course, the first switch Q1 to the third switch Q3 can also be other types, such as IGBT, silicon carbide, gallium nitride, etc., which are not limited here.

[0044] In some implementations, such as Figure 5 As shown, the soft-start voltage circuit also includes an inverter. The input terminal of the inverter is connected to the control terminal of the first switching transistor Q1, and the output terminal is connected to the control terminal of the third switching transistor Q3.

[0045] Specifically, in order to reduce the number of signal sources, the first switch Q1 and the third switch Q3 can share the same signal source. Since the two switches require opposite signals, only one inverter needs to be added.

[0046] In some implementations, such as Figure 4 As shown, the clamping circuit 120 in the soft-start voltage circuit also includes a resistor R, which is connected in series with the first or second terminal of the third switch Q3.

[0047] Alternatively, resistor R can be removed, or it can be replaced with a low-voltage bias circuit, etc., which is not limited here.

[0048] In some implementations, such as Figure 2 As shown, current source I includes MOSFETs Q4 through Q8. The sources of MOSFETs Q4 and Q7 are connected to the supply voltage. The drain of MOSFET Q4 is connected to the source of MOSFET Q5, the drain of MOSFET Q5 is connected to the source of MOSFET Q6, and the drain of MOSFET Q6 is connected to the first switch Q1. The gate of MOSFET Q7 is connected to the gates of MOSFETs Q4 and Q5, and the drain of MOSFET Q7. The drain of MOSFET Q7 is connected to the source of MOSFET Q8, the gate of MOSFET Q8 is connected to the gate of MOSFET Q6, and the drain of MOSFET Q8. The drain of MOSFET Q8 is also grounded.

[0049] This application provides a soft-start voltage circuit. When the capacitor charging circuit 110 charges the charging capacitor C, the clamping circuit 120 in the circuit clamps the voltage of the first terminal of the first switch Q1, thereby eliminating the influence of parasitic capacitance on the charging capacitor C, thereby improving the accuracy of the charging time of the charging capacitor C, and thus improving the accuracy of the circuit soft start.

[0050] Another embodiment of this application also proposes a soft-start voltage circuit control method, applied to the aforementioned soft-start voltage circuit, the control method comprising:

[0051] When soft-start charging is required, the first switch Q1 is controlled to input a square wave signal, the second switch Q2 is controlled to input a low-level signal, and the third switch Q3 is controlled to input a signal that is completely opposite to the square wave signal.

[0052] Optionally, the duty cycle for the low level in the square wave signal can be 1 / 16 to 1 / 14. Of course, the duty cycle is not limited to this and can be other values, depending on the actual situation. There are no restrictions here.

[0053] In some implementations of the soft-start voltage circuit control method, when the square wave signal output is low, the first switch Q1 is turned on and the third switch Q3 is turned off, and the current source I charges the charging capacitor C. When the square wave signal output is high, the first switch Q1 is turned off and the third switch Q3 is turned on, and the current source I stops charging the charging capacitor C.

[0054] Another embodiment of this application also proposes a DC-DC conversion circuit, including the soft-start voltage circuit described above.

[0055] It is understood that the method steps of this embodiment correspond to the soft-start voltage circuit in the above embodiments. The options of the soft-start voltage circuit described above are also applicable to this embodiment, and will not be described again here.

[0056] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0057] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0058] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0059] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A soft-start voltage circuit, characterized in that, include: A capacitor charging circuit and a clamping circuit are provided. The capacitor charging circuit includes a current source, a first switching transistor, a second switching transistor, and a charging capacitor. The current source, the first terminal of the first switching transistor, and the charging capacitor are connected in sequence. The other terminal of the current source is used to connect to the power supply voltage. The second switching transistor is connected to the series node between the charging capacitor and the second terminal of the first switching transistor. The control terminal of the first switching transistor is used to input a square wave signal, and the second switching transistor is used to receive an enable signal. The current source includes a fourth to an eighth MOS transistor. The sources of the fourth and seventh MOS transistors are respectively connected to the power supply voltage. The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor. The drain of the fifth MOS transistor is connected to the source of the sixth MOS transistor. The drain of the sixth MOS transistor is connected to the first switching transistor. The gate of the seventh MOS transistor is connected to the gates of the fourth MOS transistor, the fifth MOS transistor, and the drain of the seventh MOS transistor; the drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor; the gate of the eighth MOS transistor is connected to the gate of the sixth MOS transistor and the drain of the eighth MOS transistor; the drain of the eighth MOS transistor is also grounded. The clamping circuit includes a third switch transistor, the first end of which is connected to the first end of the first switch transistor, the second end of which is grounded, and the control terminal of the third switch transistor is used to input a signal that is opposite to the square wave signal input by the first switch transistor. The first switch and the third switch are both PMOS transistors, and the second switch is an NMOS transistor; The clamping circuit is connected to the series node between the current source and the first terminal of the first switching transistor. The clamping circuit is used to clamp the first terminal of the first switching transistor based on the threshold voltage of the PMOS transistor body effect when the capacitor charging circuit charges the charging capacitor.

2. The soft-start voltage circuit according to claim 1, characterized in that, It also includes an inverter, the input of which is connected to the control terminal of the first switching transistor, and the output of which is connected to the control terminal of the third switching transistor.

3. The soft-start voltage circuit according to claim 1, characterized in that, The clamping circuit also includes a resistor connected in series with the first or second terminal of the third switching transistor.

4. A soft-start voltage circuit control method, characterized in that, The control method, applied to the soft-start voltage circuit as described in any one of claims 1 to 3, comprises: When soft-start charging is required, the first switch is controlled to input the square wave signal, the second switch is controlled to input a low-level signal, and the third switch is controlled to input a signal that is completely opposite to the square wave signal.

5. The soft-start voltage circuit control method according to claim 4, characterized in that, The duty cycle of the low-level square wave signal is 1 / 16 to 1 / 14.

6. The soft-start voltage circuit control method according to claim 4, characterized in that, When the square wave signal output is low, the first switch is turned on and the third switch is turned off, and the current source charges the charging capacitor. When the square wave signal outputs a high level, the first switch is turned off and the third switch is turned on, and the current source stops charging the charging capacitor.

7. A DC-DC converter circuit, characterized in that, include: The soft-start voltage circuit according to any one of claims 1 to 3.

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