A quantizer structure applied to an incremental delta-sigma analog-to-digital converter

Abstract

The application discloses a quantizer structure applied to an incremental Delta_Sigma analog-digital converter, and comprises a double quantizer, a passive circuit, an inverter and a logic circuit. The passive circuit is used for reducing the kickback noise of the circuit; the inverter is used for deflecting according to the input signal and adjusting the feedback circuit through the logic circuit. The application has the beneficial effect that the low-frequency signal can be measured more accurately.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and in particular to a quantizer structure for use in incremental Delta_Sigma analog-to-digital converters. Background Technology

[0002] Currently, Delta-Sigma analog-to-digital converters (ADCs) offer advantages such as high precision and low power consumption, making them widely used in low-frequency signal detection. Incremental Delta-Sigma ADCs, compared to traditional Delta-Sigma ADCs, are primarily used for high-precision narrowband signals, such as near-DC low-frequency signals in instrument measurements and temperature / humidity sensors, requiring accurate absolute values. During operation, incremental Delta-Sigma ADCs sample the input signal within a fixed conversion time and convert it into digital code.

[0003] In existing technologies, the quantizer is located at the very end of an incremental Delta-Sigma ADC. Its function is to convert the integrator's output signal into a low-precision digital code stream, which is then sent to the digital decimation filter and simultaneously fed back to the integrator. The quantizer structure is typically a dynamic comparator with a pre-amplifier. Traditional latches, when the voltage across their regeneration node changes, are easily coupled to the comparator's input via the parasitic capacitance of the MOSFET, thus reducing the accuracy of the analog-to-digital converter (ADC). This also results in low measurement accuracy for low-frequency signals.

[0004] For example, a Chinese patent document discloses "A Compressed Sampling Analog-to-Digital Converter Using a Sampling and Quantization Circuit", publication number: CN105720987A, application date: January 18, 2016. This invention inputs all analog sampling and integration results sequentially into the same quantizer, effectively reducing the mismatch problem in the multi-channel quantization process and reducing the complexity of the compressed sampling analog-to-digital converter system implementation. The modular design of the sampling and quantization circuit improves the independence and versatility of each module design. However, it has the problem of low measurement accuracy of low-frequency signals. Summary of the Invention

[0005] To address the shortcomings of existing technologies in measuring low-frequency signals with low accuracy, this invention proposes a quantizer structure for incremental Delta-Sigma analog-to-digital converters, which can measure low-frequency signals more accurately.

[0006] The following is the technical solution of the present invention: a quantizer structure applied to an incremental Delta_Sigma analog-to-digital converter, comprising:

[0007] A dual quantizer is used to output signals to logic circuits;

[0008] Passive circuitry used to reduce back-kickback noise in circuits;

[0009] An inverter is used to deflect an input signal and adjust the feedback circuit through logic circuitry.

[0010] In this scheme, the dual quantizer can improve the accuracy of low-frequency signals within the measured time. The quantizer circuit has a simple structure and reduces back-kickback noise through passive circuitry. Compared with comparators with pre-amplification structures, it significantly reduces power consumption and lowers the power supply voltage requirements. When the inverter is working, it deflects accordingly based on the different input signals. The comparison result is used to adjust the feedback circuit through logic circuitry.

[0011] Preferably, the positive input of the first quantizer is connected to the negative output of the switched-capacitor integrator, and the negative input of the first quantizer is connected to the positive output of the switched-capacitor integrator. The positive input of the second quantizer is connected to the positive output of the switched-capacitor integrator, and the negative input of the second quantizer is connected to the negative output of the switched-capacitor integrator. The outputs of the first and second quantizers are used as inputs to the logic circuit.

[0012] In this scheme, two quantizers are used and their outputs are used as inputs to a logic circuit, which allows for comparison of the outputs of the two quantizers. The quantizer circuit has a simple structure, and the dual quantizers can improve the accuracy of low-frequency signals within the measured time.

[0013] Preferably, the left plate of capacitor C1 is connected to the positive input of the comparator, and the right plate of capacitor C1 is connected to the left plates of capacitors C3 and C5. The right plate of capacitor C1 is connected to the common-mode voltage V via switch K1. CM The right plate of capacitor C3 is connected via switch K2 and reference voltage V. ref1 The right plate of capacitor C3 is connected to ground via switch K1, and the right plate of capacitor C5 is connected to the reference voltage V via switch K2. ref1 The right electrode of capacitor C5 is connected via switch K1 and V. ref2 The right plate of capacitor C2 is connected to the negative input of the comparator, and the left plate of capacitor C2 is connected to the right plates of capacitors C4 and C6. The left plate of capacitor C2 is connected to the common-mode voltage V via switch K1. CM The left plate of capacitor C4 is connected via switch K1 and reference voltage V. ref1 The left plate of capacitor C4 is connected to ground via switch K2, and the left plate of capacitor C6 is connected to the reference voltage V via switch K1. ref1 The left plate of capacitor C6 is connected via switch K2 and reference voltage V. ref2 Connected.

[0014] In this solution, to address the shortcomings of traditional latches, an isolation circuit composed of switches and capacitors is used to effectively reduce the impact of comparator regeneration node kickback noise. Compared to latches with preamplifier structures, power consumption is reduced.

[0015] As a preferred option, the switching transistor M P1 and switching transistor M P2 The source is connected to the power supply, and the switching transistor M P1 The drain connection of the switching transistor M P3 The source of the switch M P2 The drain connection of the switching transistor M P4 The source of the switch M P3 The drain and switching transistor M n3 The drain and switching transistor M P2 Gate and switch M n2 The gates of the switching transistor M are connected together as an input / output port. P4 The drain and switching transistor M n4 The drain and switching transistor M P1 Gate and switch M n1 The gates of the transistors are connected together as another input / output port, and the switching transistor M... n3 The source of the switch M is connected to the source. n1 The drain of the switching transistor M n4 The source of the switch M is connected to the source. n2 The drain of the switching transistor M n1 and switching transistor M n2 The source of the transistor is grounded, and the switching transistor M p3 and switching transistor M P4 The gate is controlled by the first switch Control, switching transistor M n3 and switching transistor M n4 The gate is controlled by a second switch. control.

[0016] Preferably, when switch S1 is closed and switch S2 is open, the input signal V is measured. inp Input signal V inn When switch S1 is open and switch S2 is closed, the input signal V is measured. inn Input signal V inp .

[0017] In this scheme, to more accurately measure low-frequency signals, a single conversion process includes two sub-processes, which can improve the accuracy of the signal within the measurement time. When switch S1 is closed and switch S2 is open, the input signal V is measured. inp Input signal V inn When switch S1 is open and switch S2 is closed, the input signal V is measured. inn Input signal Vinp A dual-channel quantizer is used to reduce device manufacturing process errors.

[0018] Preferably, the right plate of capacitor C1 and the left plate of capacitor C2 are connected by a first switch. Connect cross-coupled inverters.

[0019] As a preferred option, the switching transistor M P3 The drain and switching transistor M n3 The drain of the circuit is connected to the input of the inverter as the output.

[0020] In this scheme, the switching transistor M P3 The drain and switching transistor M n3 The drain of the first quantizer is connected to the input of the inverter as the output. The output B0 of the first quantizer and the output B1 of the second quantizer are the comparison results of the two quantizers.

[0021] Preferably, capacitors C1 and C2 have the same capacitance, capacitors C3 and C4 have the same capacitance, capacitors C5 and C6 have the same capacitance, and capacitors C1, C3, and C5 have different capacitances.

[0022] In this scheme, capacitor C1 = capacitor C2 = 1C, capacitor C3 = capacitor C4 = mC, and capacitor C5 = capacitor C6 = nC, which facilitates the improvement of signal measurement accuracy.

[0023] Preferably, when switch K1 or switch K2 is turned on, the first switch... It is in a closed state.

[0024] In this scheme, the first switch The inverter is closed during the period when either switch K1 or K2 is on, so the input of the cross-coupled inverter is always the same as V. o+ and V o- Maintain consistency.

[0025] As a preferred option, the first switch Close, second switch Disconnected, the two cross-coupled inverters do not work; first switch Disconnect, second switch When closed, the two cross-coupled inverters begin to work.

[0026] In this scheme, the first switch Close, second switch Disconnect, switch M P3 Switching transistor M P4 Switching transistor M n3 and switching transistor M n4When switched off, the two cross-coupled inverters cease operation, reducing unnecessary power consumption. Simultaneously, the outputs of the first and second quantizers retain their original comparison results. When the first switch... Disconnect, second switch When the circuit is turned on, that is, before switch K1 is closed and after switch K2 is turned off, the mutually coupled inverters start to work, and deflect accordingly according to different input signals. The comparison result is used to adjust the feedback circuit through the logic circuit.

[0027] The beneficial effects of this invention are: it can improve the accuracy of low-frequency signals within the measured time; it reduces back-kickback noise of the circuit through passive circuitry, and significantly reduces power consumption and power supply voltage requirements compared to comparators with pre-amplification structures. Attached Figure Description

[0028] Figure 1 This invention provides a schematic diagram of a quantizer structure applied to an incremental Delta-Sigma analog-to-digital converter.

[0029] Figure 2 The present invention provides a schematic diagram of a quantizer structure for use in an incremental Delta-Sigma analog-to-digital converter.

[0030] Figure 3 This invention relates to a timing diagram of switches in a circuit of a quantizer structure applied to an incremental Delta-Sigma analog-to-digital converter. Detailed Implementation

[0031] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0032] Example: Figure 1 As shown, a quantizer structure for an incremental Delta_Sigma analog-to-digital converter includes: a dual quantizer, a passive circuit, and an inverter.

[0033] The dual quantizer is a first-order, one-bit incremental Delta_Sigma ADC dual quantizer structure, using two quantizers. The positive input of the first quantizer is connected to the negative output of the switched-capacitor integrator, and the negative input of the first quantizer is connected to the positive output of the switched-capacitor integrator. The positive input of the second quantizer is connected to the positive output of the switched-capacitor integrator, and the negative input of the second quantizer is connected to the negative output of the switched-capacitor integrator. The outputs B0 of the first quantizer and B1 of the second quantizer are used as inputs to the logic circuit.

[0034] like Figure 2As shown, the passive circuit is the passive circuit of the quantizer, including capacitors C1, C2, C3, C4, C5, and C6, switch K1, switch K2, and reference voltage V. ref1 Reference voltage V ref2 and common-mode voltage V CM The left plate of capacitor C1 is connected to the positive input of the comparator, and the right plate of capacitor C1 is connected to the left plates of capacitors C3 and C5. The right plate of capacitor C1 is connected to the common-mode voltage V through switch K1. CM The right plate of capacitor C3 is connected via switch K2 and reference voltage V. ref1 The right plate of capacitor C3 is connected to ground via switch K1, and the right plate of capacitor C5 is connected to the reference voltage V via switch K2. ref1 The right electrode of capacitor C5 is connected via switch K1 and V. ref2 The right plate of capacitor C2 is connected to the negative input of the comparator, and the left plate of capacitor C2 is connected to the right plates of capacitors C4 and C6. The left plate of capacitor C2 is connected to the common-mode voltage V via switch K1. CM The left plate of capacitor C4 is connected via switch K1 and reference voltage V. ref1 The left plate of capacitor C4 is connected to ground via switch K2, and the left plate of capacitor C6 is connected to the reference voltage V via switch K1. ref1 The left plate of capacitor C6 is connected via switch K2 and reference voltage V. ref2 Connected.

[0035] like Figure 2 As shown, the inverters are mutually coupled, including switching transistors M. P1 Switching transistor M P2 Switching transistor M n1 Switching transistor M n2 Switching transistor M P3 Switching transistor M P4 Switching transistor M n3 and switching transistor M n4 Switching transistor M P1 and switching transistor M P2 The source of each transistor is connected to the power supply, and the switching transistor M is connected to the power supply. P1 The drain connection of the switching transistor M P3 The source of the switch M P2 The drain connection of the switching transistor M P4 The source of the switch M P3 The drain and switching transistor M n3 The drain and switching transistor M P2 Gate and switch M n2 The gates of the switching transistor M are connected together as an input / output port. P4 The drain and switching transistor M n4 The drain and switching transistor MP1 Gate and switch M n1 The gates of the transistors are connected together as another input / output port, and the switching transistor M... n3 The source of the switch M is connected to the source. n1 The drain of the switching transistor M n4 The source of the switch M is connected to the source. n2 The drain of the switching transistor M n1 and switching transistor M n2 The source of the transistor is grounded, and the switching transistor M p3 and switching transistor M P4 The gate is controlled by the first switch Control, switching transistor M n3 and switching transistor M n4 The gate is controlled by a second switch. control.

[0036] like Figure 1 As shown, to more accurately measure low-frequency signals, a single conversion process includes two sub-processes, which can improve the accuracy of the signal within the measurement time. When switch S1 is closed and switch S2 is open, the input signal V is measured. inp Input signal V inn When switch S1 is open and switch S2 is closed, the input signal V is measured. inn Input signal V inp A dual-channel quantizer is used to reduce device manufacturing process errors.

[0037] To address the shortcomings of traditional latches, this invention proposes an improved latch as the quantizer for an incremental Delta_Sigma ADC. The improved latch utilizes an isolation circuit composed of switches and capacitors to effectively reduce the impact of comparator regeneration node kickback noise. Compared to latches with preamplifier structures, it reduces power consumption. The structural diagram is shown below. Figure 2 As shown: The output of the switched capacitor integrator serves as the input of the comparator, and the left plate of capacitor C1 and V... i+ Connect the right plate of capacitor C1 (i.e., V). o+ The left plates of capacitors C3 and C5 are connected via a switch and a common-mode voltage V. CM The right plate of capacitor C3 is connected via switch K2 and reference voltage V. ref1 The right plate of capacitor C3 is connected to ground via switch K1, and the right plate of capacitor C5 is connected to the reference voltage V via switch K2. ref1 The right electrode of capacitor C5 is connected via switch K1 and V. ref2 Connected, the right plate of capacitor C2 and V i- Connect the left plate of capacitor C2 (i.e., V). o- The right plates of capacitors C4 and C6 are connected to the left plate of capacitor C2, and the left plate of capacitor C2 is connected to the common-mode voltage V via switch K1. CMThe left plate of capacitor C4 is connected via switch K1 and reference voltage V. ref1 The capacitor C4 is connected to ground via switch K2, and the left plate of capacitor C6 is connected to the reference voltage V via switch K1. ref1 The left plate of capacitor C6 is connected via switch K2 and V. ref2 Connected. V o+ and V o- Through the first switch respectively It is connected to a cross-coupled inverter. The internal circuit diagram of the inverter (INV) is shown below. Figure 2 As shown, the switching transistor M p3 Switching transistor M P4 Switching transistor M n3 Switching transistor M n4 and the switching transistor M respectively P1 Switching transistor M P2 Switching transistor M n1 Switching transistor M n2 Connected, switch M P3 The drain and switching transistor M n3 The drains of the two quantizers are connected together as the output and then connected to the input of the inverter. The output B0 of the first quantizer and the output B1 of the second quantizer are the comparison results of the two quantizers. The capacitances are: C1 = C2 = 1C, C3 = C4 = mC, C5 = C6 = nC. This means that the capacitances of C1 and C2 are equal, the capacitances of C3 and C4 are equal, and the capacitances of C5 and C6 are equal. The capacitances of C1, C3, and C5 are not equal.

[0038] like Figure 3 As shown, the proposed quantizer's working process and principle are as follows: When switch K1 is closed, the switched capacitor integrator is in sampling mode. The sampling capacitor CS samples and stores the input analog signal. The amplifier's input and output are short-circuited. At this time, the comparator's V... i+(n) =V i-(n) =V CM V o+(n) =V o-(n) =V CM First switch Close, second switch Disconnect, switch M P3 M P4 M n3 M n4 When switched off, the two cross-coupled inverters are inactive, reducing unnecessary power consumption, and the outputs B0 and B1 remain unchanged from their original comparison results. When switch K2 is closed, the switched capacitor integrator is in integration mode, and the integration result is obtained from the output of the switched capacitor. Due to the difference between the input signal and the feedback quantity, V... i+(n+1) ≠Vi-(n+1) ≠V CM Assuming V in the quantizer o+ and V o- The new states are V o+(n+1) and V o-(n+1) Applying the law of conservation of charge to these two processes, we obtain the following two equations:

[0039]

[0040]

[0041] Due to the first switch Since the inverter is closed during the conduction of either switch K1 or K2, the input of the cross-coupled inverter is always connected to V. o+ and V o- Maintain consistency. When the first switch... Disconnect, second switch When the circuit is turned on, that is, before switch K1 is closed and after switch K2 is turned off, the mutually coupled inverters start to work, and deflect accordingly according to different input signals. The comparison result is used to adjust the feedback circuit through the logic circuit.

[0042] The first-order, one-bit incremental Delta-Sigma ADC consists of two sub-processes in one conversion, which can improve the accuracy of low-frequency signals within the measurement time. The quantizer circuit has a simple structure. The passive circuit reduces the back kickback noise of the circuit, and the power consumption in the circuit is significantly reduced compared with comparators with pre-amplification structures, thus reducing the power supply voltage requirements.

Claims

1. A quantizer structure for use in an incremental Delta-Sigma analog-to-digital converter, characterized in that, include: A dual quantizer is used to output signals to logic circuits; The passive circuit, which is the passive circuit of the quantizer and connected to the inverter, is used to reduce the back kick noise of the circuit: the isolation circuit composed of switches and capacitors reduces the influence of the back kick noise of the comparator regeneration node. An inverter, the inverter of a quantizer, is used to deflect the input signal and adjust the feedback circuit through logic circuitry.

2. The quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 1, characterized in that, The positive input of the first quantizer is connected to the negative output of the switched-capacitor integrator, and the negative input of the first quantizer is connected to the positive output of the switched-capacitor integrator. The positive input of the second quantizer is connected to the positive output of the switched-capacitor integrator, and the negative input of the second quantizer is connected to the negative output of the switched-capacitor integrator. The outputs of the first and second quantizers are used as inputs to the logic circuit.

3. The quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 1, characterized in that, The passive circuit includes the left plate of capacitor C1 connected to the positive input of the comparator, the right plate of capacitor C1 connected to the left plates of capacitors C3 and C5, and the right plate of capacitor C1 connected to the common-mode voltage V via switch K1. CM The right plate of capacitor C3 is connected via switch K2 and reference voltage V. ref1 The right plate of capacitor C3 is connected to ground via switch K1, and the right plate of capacitor C5 is connected to the reference voltage V via switch K2. ref1 The right electrode of capacitor C5 is connected via switch K1 and V. ref2 The right plate of capacitor C2 is connected to the negative input of the comparator, and the left plate of capacitor C2 is connected to the right plates of capacitors C4 and C6. The left plate of capacitor C2 is connected to the common-mode voltage V via switch K1. CM The left plate of capacitor C4 is connected via switch K1 and reference voltage V. ref1 The left plate of capacitor C4 is connected to ground via switch K2, and the left plate of capacitor C6 is connected to the reference voltage V via switch K1. ref1 The left plate of capacitor C6 is connected via switch K2 and reference voltage V. ref2 Connected.

4. The quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 1, characterized in that, The inverter includes a switching transistor M P1 and switching transistor M P2 The source is connected to the power supply, and the switching transistor M... P1 The drain connection of the switching transistor M P3 The source of the switch M P2 The drain connection of the switching transistor M P4 The source of the switch M P3 The drain and switching transistor M n3 The drain and switching transistor M P2 Gate and switch M n2 The gates of the switching transistor M are connected together as an input / output port. P4 The drain and switching transistor M n4 The drain and switching transistor M P1 Gate and switch M n1 The gates of the transistors are connected together as another input / output port, and the switching transistor M... n3 The source of the switch M is connected to the source. n1 The drain of the switching transistor M n4 The source of the switch M is connected to the source. n2 The drain of the switching transistor M n1 and switching transistor M n2 The source of the transistor is grounded, and the switching transistor M p3 and switching transistor M P4 The gate is controlled by the first switch Control, switching transistor M n3 and switching transistor M n4 The gate is controlled by a second switch. control.

5. The quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 1, characterized in that, When switch S1 is closed and switch S2 is open, the input signal V is measured. inp Input signal V inn When switch S1 is open and switch S2 is closed, the input signal V is measured. inn Input signal V inp .

6. The quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 3, characterized in that, The right plate of capacitor C1 and the left plate of capacitor C2 are connected by the first switch. Connect cross-coupled inverters.

7. The quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 4, characterized in that, Switching transistor M P3 The drain and switching transistor M n3 The drain of the circuit is connected to the input of the inverter as the output.

8. A quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 3 or 6, characterized in that, The capacitances of capacitors C1 and C2 are equal, the capacitances of capacitors C3 and C4 are equal, the capacitances of capacitors C5 and C6 are equal, and the capacitances of capacitors C1, C3, and C5 are not equal.

9. A quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 6, characterized in that, When switch K1 or switch K2 is turned on, the first switch It is in a closed state.

10. A quantizer structure for an incremental Delta-Sigma analog-to-digital converter according to claim 4 or 7, characterized in that, First switch Close, second switch Disconnected, the two cross-coupled inverters do not work; first switch Disconnect, second switch When closed, the two cross-coupled inverters begin to work.

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