Display panel, display terminal and manufacturing method of display panel

Abstract

The application discloses a display panel, a display terminal and a manufacturing method of the display panel. The display panel comprises an array substrate, a counter substrate and a display medium layer arranged between the array substrate and the counter substrate. The display medium layer is a plurality of micro liquid capsules, which are used for forming an image under the driving of an electric field to perform image display. The array substrate comprises a plurality of thin film transistors arranged in an array. The thin film transistor comprises a gate, a semiconductor layer arranged in a stack with the gate, and a source and a drain arranged on both sides of the semiconductor layer. A channel region is arranged between the source and the drain. The counter substrate further comprises a light shielding layer and a color filter layer. The color filter layer is opposite to the pixel electrode. The projection of the light shielding layer on the array substrate covers the channel region, and is used for blocking external light from transmitting to the channel region through the white particles and the black particles of the counter substrate. The light shielding layer can effectively avoid the irradiation of external light on the channel region, so that the leakage current is not large.

Description

Display panel, display terminal, and display panel manufacturing method Technical Field

[0001] This application relates to the field of display technology, and more particularly to display panels, display terminals, and methods for manufacturing display panels. Background Technology

[0002] Electronic paper display (EPD) is a new technology that utilizes ambient light for display. Its display principle involves encapsulating black and white charged particles in a microcapsule structure. An external electric field controls the rise and fall of these particles, creating a monochrome display effect. Under the influence of the electric field, the black and white ink droplets move continuously. When a white droplet rises to the top surface, all ambient light is completely reflected, resulting in a white appearance. By mixing the two different ink droplets in proportion, different colors, including black, white, and shades of gray, can be formed.

[0003] However, in the structure of electronic paper displays, the channels of thin-film transistors are exposed to ambient light transmitted through electrophoretic particles, resulting in a large leakage current. This causes crosstalk during display and reduces the contrast of electronic paper displays. Summary of the Invention

[0004] In view of the shortcomings of the prior art, this application proposes a display panel, a display terminal, and a method for manufacturing the display panel that can effectively prevent the thin-film transistor channel from being irradiated by ambient light.

[0005] A display panel includes an array substrate, a counter substrate, and a display medium layer sandwiched between the array substrate and the counter substrate. The display medium layer comprises a plurality of micro-liquid capsules, each of which is a sealed sphere encapsulated with white particles, black particles, and a transparent dispersion medium inside. The white particles and the black particles carry different charges and are immersed in the transparent dispersion medium, allowing them to move freely. The array substrate includes a plurality of thin-film transistors arranged in an array. The thin-film transistors are used to drive the white particles and the black particles to move according to a data signal, causing the micro-liquid capsules to jointly form an image on one side of the counter substrate to perform image display. The thin-film transistor includes a gate, a semiconductor layer stacked with the gate, and a source and a drain disposed on both sides of the semiconductor layer. A channel region is disposed between the source and the drain. The opposing substrate also includes a light-shielding layer and a color filter layer. The color filter layer is used to transmit light of different colors. The projection of the light-shielding layer on the array substrate covers the channel region, which is used to block external light from being transmitted through the white particles and the black particles to the channel region via the opposing substrate.

[0006] Optionally, the array substrate further includes multiple scan lines, multiple data lines, and multiple pixel electrodes. The drain of the thin-film transistor is connected to the pixel electrode. The opposing substrate further includes a transparent electrode. Under the control of the scan signal, the thin-film transistor receives the data signal and transmits the data signal to the pixel electrode. The pixel electrode forms an electric field with the transparent electrode according to the data signal to drive the micro liquid capsule to emit light of a preset gray level, thereby performing image display.

[0007] Optionally, the color filter layer includes multiple first color resist layers, multiple second color resist layers, and multiple third color resist layers. The first color resist layer, the second color resist layer, and the third color resist layer are respectively used to transmit three different colors of light. Any color resist layer and a light-shielding layer are arranged adjacent to each other to form a sub-pixel. The three sub-pixels of different colors are arranged adjacent to each other to form a pixel unit. The pixel unit is used to receive the light emitted from the micro liquid capsule and transmit the light of the corresponding color, thereby displaying an image.

[0008] Optionally, the light-shielding layer includes any two of the first color resist, the second color resist, and the third color resist, with the two different colors of resist stacked in any order to shield the channel area from light.

[0009] Optionally, the light-shielding layer includes a first color resist, a second color resist, and a third color resist, which are stacked in any order to shield the channel area from light.

[0010] Optionally, the display panel further includes a planarization layer sandwiched between the transparent electrode, the color filter layer, and the light-shielding layer. The light-shielding layer includes a first light-shielding portion and a second light-shielding portion. The first light-shielding portion has the same thickness as the color filter layer and is flush with the color filter layer. The second light-shielding portion is adjacent to the first light-shielding portion and protrudes to one side of the planarization layer to penetrate through the planarization layer.

[0011] Optionally, the first light-shielding portion includes a first color resist and a third color resist, which are stacked together, with the third color resist disposed adjacent to the planarization layer; the second light-shielding portion includes the first color resist and the third color resist, which are flush with the color filter layer, with the third color resist penetrating through the planarization layer.

[0012] Optionally, in the first light-shielding part, the first color resist and the second color resist have the same thickness, which is a first thickness; in the second light-shielding part, the first color resist and the second color resist have the same thickness, which is a second thickness, and the second thickness is twice the first thickness.

[0013] This application also discloses a display terminal, including a power module and the aforementioned display panel, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.

[0014] This application also discloses a method for manufacturing a display panel, comprising: providing an array substrate, the array substrate including a plurality of thin-film transistors arranged in an array, each thin-film transistor including a gate, a semiconductor layer stacked with the gate, and source and drain electrodes disposed on both sides of the semiconductor layer, with a channel region disposed between the source and drain electrodes. A substrate is provided, and a plurality of light-shielding layers spaced at predetermined distances are formed on the substrate using a photomask, and a color filter layer is disposed between two adjacent light-shielding layers to form a facing substrate, the light-shielding layers being used to shield the channel region from light, the color filter layers being used to transmit light of different colors, and the projection of the light-shielding layers on the array substrate covering the channel region. A plurality of micro-liquid capsules are disposed between the array substrate and the opposing substrate to form a display medium layer. The micro-liquid capsules are sealed spheres and encapsulate white particles, black particles and a transparent dispersion medium inside. The white particles and the black particles carry different charges. The white particles and the black particles are immersed in the transparent dispersion medium and can move freely. The array substrate includes a plurality of thin-film transistors arranged in an array. The light-shielding layer is used to block external light from being transmitted through the opposing substrate to the channel region via the white particles and the black particles. The thin-film transistors are used to drive the white particles and the black particles to move according to data signals, so that the micro-liquid capsules together form an image on one side of the opposing substrate to perform image display.

[0015] Optionally, the step of “providing a substrate, forming a plurality of light-shielding layers spaced at a predetermined distance on the substrate by means of a photomask, and laying a color filter layer between the light-shielding layers to form an opposing substrate” includes: the light-shielding layer includes a first light-shielding part and a second light-shielding part, the first light-shielding part is flush with the color filter layer, the second light-shielding part protrudes to the side away from the substrate, and a transparent material is filled between any two adjacent second light-shielding parts to form a flat layer, the flat layer being flush with the second light-shielding part.

[0016] Optionally, a photomask is used to etch a first color resist and a third color resist to form a first light-shielding portion and a second light-shielding portion formed by stacking the first color resist and the third color resist. In the first light-shielding portion, the thickness of the first color resist and the third color resist is a first thickness, and in the second light-shielding portion, the thickness of the first color resist and the third color resist is a second thickness.

[0017] The light-shielding layer effectively prevents external light from illuminating the channel area, thus avoiding increased leakage current in the thin-film transistor. This prevents crosstalk, reduced contrast, poor display quality, and even display errors in electronic ink displays. The light-shielding layer includes a first light-shielding part and a second light-shielding part. The first light-shielding part is used to prevent vertical ambient light from illuminating the channel area, and the second light-shielding part is used to prevent oblique ambient light from illuminating the channel area. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of the structure of a display terminal provided in an embodiment of this application;

[0020] Figure 2 is a schematic diagram of the side layout of the display panel in Figure 1;

[0021] Figure 3 is a schematic diagram of the planar layout of the array substrate in the display panel shown in Figure 2;

[0022] Figure 4 is a schematic diagram of the structure of the dielectric layer shown in Figure 2;

[0023] Figure 5 is a cross-sectional view of the display panel in Figure 2;

[0024] Figure 6 is a schematic diagram of the structure of the opposing substrates in Figure 5;

[0025] Figure 7 is a schematic diagram of the planar layout of the opposing substrates in Figure 6;

[0026] Figure 8 is a schematic diagram of the structure of an opposing substrate as shown in Figure 5, provided in the second embodiment of this application;

[0027] Figure 9 is a schematic diagram of the structure of an opposing substrate as shown in Figure 5, provided in the third embodiment of this application;

[0028] Figure 10 is a cross-sectional structural diagram of a display panel provided in the fourth embodiment of this application;

[0029] Figure 11 is a schematic diagram of the side layout of the substrate facing each other in Figure 10;

[0030] Figure 12 is a side view of the array substrate as shown in Figure 10, provided in the fifth embodiment of this application;

[0031] Figure 13 is a flowchart of a method for manufacturing a display panel according to the sixth embodiment of this application;

[0032] Figure 14 is a schematic diagram of the fabrication process of the opposing substrate;

[0033] Figure 15 is a schematic diagram of another type of opposing substrate fabrication process.

[0034] Reference numerals: Display terminal-1, Display panel-10, Power module-20, Display area-10a, Non-display area-10b, m data lines-S1~Sm, n scan lines-G1~Gn, Pixel unit-P, Array substrate-110, Timing control circuit-11, Data driving circuit-12, Scan driving circuit-13, Opposing substrate-120, Display dielectric layer-130, White particles-a, Black particles-b, Transparent dispersion medium-c, Micro liquid capsule-131, Substrate-111, Thin film transistor-112, Gate -112a, Semiconductor layer -112b, Source electrode -112c, Drain electrode -112d, Pixel electrode -113, Channel region -112e, Gate insulating layer -112f, Common electrode -114, Protective layer -115, Transparent electrode -121, Color resist layer -122, Light-shielding layer -123, Planarization layer -124, First color resist layer -122A, Second color resist layer -122B, Third color resist layer -122C, Photomask - Mask, First light-shielding part -1231, Second light-shielding part -1232, First thickness -d1, Second thickness -d2. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0036] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0038] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0040] Please refer to Figure 1, which is a schematic diagram of the structure of a display terminal 1 provided in an embodiment of this application. As shown in Figure 1, the display terminal 1 includes a display panel 10 and a power module 20. The display panel 10 is used for image display, and the power module 20 is used to provide driving power to the display panel 10 when displaying images. In this embodiment, the display terminal 1 can be a device that uses electronic ink for display.

[0041] Please refer to Figure 2, which is a schematic diagram of the side layout of the terminal shown in Figure 1.

[0042] As shown in Figure 2, the display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used for image display, and the non-display area 10b is disposed around the display area 10a to house other auxiliary components or modules. Specifically, the display panel 10 includes an array substrate (AS) 110 and a counter substrate 120, and a display medium layer 130 sandwiched between the array substrate 110 and the counter substrate 120. Driving elements are disposed on the array substrate 110 and the counter substrate 120 to generate corresponding electric fields according to data signals, thereby driving light of corresponding grayscale to be transmitted through the display medium layer 130 to perform image display.

[0043] Please refer to Figure 3, which is a schematic diagram of the planar layout of the array substrate in the display panel shown in Figure 2. As shown in Figure 3, the corresponding image display area 10a in the array substrate 110 includes multiple m*n pixel units P arranged in a matrix, m data lines S1 to Sm, and n scan lines G1 to Gn, where m and n are natural numbers greater than 1.

[0044] The n scan lines G1 to Gn extend along the first direction F1 and are mutually insulated and arranged in parallel along the second direction F2. The m data lines S1 to Sm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other.

[0045] Corresponding to the non-display area 10b of the display panel 10 (FIG. 2), the display terminal 100 further includes a timing control circuit 11 for driving pixel units to display images, a data driving circuit 12, and a scanning driving circuit 13 disposed on the array substrate 110.

[0046] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13. It is used to control the working timing of the data driving circuit 12 and the scan driving circuit 13, that is, to output the corresponding timing control signal to the data driving circuit 12 and the scan driving circuit 13 to control when to output the corresponding scan signal and data signal.

[0047] The data driving circuit 12 is electrically connected to the m data lines S1 to Sm, and is used to transmit the data signal (Data) to be displayed to the plurality of pixel units P in the form of data voltage through the m data lines S1 to Sm.

[0048] The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and outputs scan signals through the n scan lines G1 to Gn to control when the pixel unit P receives data signals. Specifically, the scan driving circuit 13 outputs scan signals from the n scan lines G1 to Gn in sequence according to their positional arrangement and in accordance with the scan cycle.

[0049] In this embodiment, the circuit elements in the scanning drive circuit 13 and the pixel units P in the array substrate 110 are fabricated in the array substrate 110 using the same process, which is the GOA (Gate Driver on Array) technology.

[0050] Please refer to Figure 4, which is a schematic diagram of the structure of the dielectric layer shown in Figure 2.

[0051] As shown in Figure 4, the display dielectric layer 130 is an electronic paper film comprising multiple micro-liquid capsules 131. Each micro-liquid capsule 131 is a sealed sphere, encapsulating white particles a, black particles b, and a transparent dispersion medium c. The white particles a and black particles b are two types of particles with different charges. For example, white particles a are positively charged and black particles b are negatively charged, or white particles a are negatively charged and black particles b are positively charged. The white particles a and black particles b are completely immersed in the transparent dispersion medium c and can move freely within it. When an electric field is formed at the electrodes at both ends of the micro-liquid capsules 131, the positively charged white particles a and the negatively charged black particles b move accordingly under the influence of the electric field. Each micro-liquid capsule 131 will appear black or white to a certain degree on the side facing the opposing substrate 120. Finally, all the micro-liquid capsules 131 together form a certain image on the side facing the opposing substrate 120.

[0052] Please refer to Figure 5, which is a cross-sectional view of the display panel in Figure 2.

[0053] As shown in Figure 5, the array substrate 110 includes a substrate 111 and a plurality of thin film transistors (TFTs) 112 and pixel electrodes 113 arranged in an array. The TFTs 112 include a gate 112a, a semiconductor layer 112b, and source electrodes 112c and drain electrodes 112d disposed on both sides of the semiconductor layer 112b. The middle region of the semiconductor layer 112b is a channel region 112e, and the drain electrode 112d of the TFTs 112 is connected to the pixel electrodes 113.

[0054] The gate electrode 112a is stacked on the substrate 111, and the semiconductor layer 112b is disposed on the side of the gate electrode 112a away from the substrate 111. The array substrate 110 also includes a gate insulating layer 112f disposed between the gate electrode 112a and the semiconductor layer 112b. The gate insulating layer 112f serves to insulate and planarize the gate electrode 112a and the semiconductor layer 112b. The source electrode 112c and the drain electrode 112d are stacked at a predetermined distance on the side of the semiconductor layer 112b away from the gate insulating layer 112f.

[0055] The array substrate also includes a common electrode 114, which is stacked on the substrate 111 at a predetermined distance from the gate electrode 112a. The common electrode 114 and the gate electrode 112a are disposed on the same layer. The gate insulating layer 112f is stacked on the side of the common electrode 114 away from the substrate 111. The drain electrode 112d extends toward the common electrode 114 and is stacked on the side of the gate insulating layer 112f away from the common electrode 114.

[0056] The array substrate also includes a protective layer 115, which covers the semiconductor layer 112b, the source 112c and the drain 112d, and is used to protect the metal layer in the thin film transistor 112, namely the semiconductor layer 112b, the source 112c and the drain 112d, from scratches.

[0057] The pixel electrode 113 is stacked on the protective layer 115 on the side away from the metal layer and is electrically connected to the drain 112d through the protective layer 115. The projection of the pixel electrode 113 on the substrate 111 coincides with the common electrode 114. The pixel electrode 113 receives the data signal and forms a storage capacitor with the common electrode 114 to store the received data signal.

[0058] In an exemplary embodiment, the thin-film transistor 112 can be configured as a top-gate or bottom-gate type as needed, and the semiconductor layer 112b can be configured as an I-shaped or horseshoe-shaped type; this application does not impose any limitations on this. A plurality of scan lines G1-Gn and a plurality of data lines S1-Sm are also disposed on the substrate 111. The scan lines G1-Gn and the data lines S1-Sm intersect to form a plurality of pixel unit regions. Each pixel unit region is provided with at least one thin-film transistor 112, wherein the gate 112a is connected to the scan line, the source 112c is connected to the data line, and the drain 112d is connected to the pixel electrode 113. The source 11c and drain 112d are electrically connected via the semiconductor layer 112b under the control of the scan line to receive scan signals from the scan line, and the pixel electrode 113 receives data signals from the data line to drive the display medium layer 130 to perform image display.

[0059] The opposing substrate 120 includes a transparent electrode 121, a color filter layer 122, and a light-shielding layer 123. The transparent electrode 121 is stacked on the side of the display medium layer 130 away from the array substrate 110. The transparent electrode 121 is used to form an electric field with the pixel electrode 113 to drive the micro liquid capsules to emit white light of a preset gray level. The color filter layer 122 is used to filter the white light emitted by multiple micro liquid capsules into light of different colors, thereby displaying an image. The light-shielding layer 123 is made of an opaque material.

[0060] A color filter layer 122 and a light-shielding layer 123 are arranged side by side and stacked on the side of the transparent electrode 121 away from the display medium layer 130. The light-shielding layer 123 is made of an opaque material. The projection of the color filter layer 122 on the array substrate 110 covers the pixel electrode 113, and the projection of the light-shielding layer 123 on the array substrate 110 covers the channel region 112e of the thin-film transistor 112. The light-shielding layer 123 prevents external light from shining on the channel region 112e, which would cause the leakage current of the thin-film transistor 112 to increase. This avoids crosstalk, reduced contrast, deteriorated display effect, or even display errors in the electronic ink display.

[0061] Please refer to Figures 6 and 7 together. Figure 6 is a schematic diagram of the side structure of the opposing substrate in Figure 5, and Figure 7 is a schematic diagram of the planar layout of the opposing substrate in Figure 5.

[0062] As shown in Figure 6, the opposing substrate 120 includes multiple light-shielding layers 123, and the color filter layer 122 includes multiple color resist layers. Each light-shielding layer 123 and a color resist layer are arranged side by side to form a sub-pixel and correspondingly cover a thin film transistor 112. Three adjacent sub-pixels constitute a pixel unit P.

[0063] Specifically, as shown in Figure 7, the color filter layer 122 includes multiple first color resist layers 122A, multiple second color resist layers 122B, and multiple third color resist layers 122C. The first color resist layer 122A and a light-shielding layer 123 form a first color sub-pixel, the second color resist layer 122B and a light-shielding layer 123 form a second color sub-pixel, and the third color resist layer 122C and a light-shielding layer 123 form a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel form a pixel unit P. The pixel unit P is used to display an image under the drive of the thin-film transistor 112.

[0064] In an exemplary embodiment, the first color resist layer 122A can be a red color resist layer, the second color resist layer 122B can be a green color resist layer, and the third color resist layer 122C can be a blue color resist layer. The arrangement of different color resist layers can be set according to specific needs, and this application does not limit it.

[0065] Please refer to Figure 8, which is a schematic diagram of the structure of a counter substrate as shown in Figure 5 according to the second embodiment of this application. As shown in Figure 8, the counter substrate 120 includes a transparent electrode 121, a color filter layer 122, and a light-shielding layer 123. The transparent electrode 121 is stacked on the side of the display medium layer 130 away from the array substrate 110. The transparent electrode 121 is used to form an electric field with the pixel electrode 113 to drive the micro liquid capsule to emit light of a preset gray level, thereby performing image display.

[0066] A color filter layer 122 and a light-shielding layer 123 are arranged side by side and stacked on the side of the transparent electrode 121 away from the display medium layer 130. The projection of the color filter layer 122 on the array substrate 110 covers the pixel electrode 113, and the projection of the light-shielding layer 123 on the array substrate 110 covers the channel region 112e of the thin film transistor 112.

[0067] In one embodiment, the light-shielding layer 123 is composed of at least two color resist layer materials stacked together to achieve light shielding of the channel region 112e. For example, the light-shielding layer 123 includes a first color resist layer 122A and a third color resist layer 122C, with the first color resist layer 122A and the third color resist layer stacked together to form a light-shielding area, thereby shielding the channel region 112e from light. Of course, it can also be configured as a first color resist layer 122A and a second color resist layer 122B stacked together, or it can be configured as a second color resist layer 122B and a third color resist layer 122C stacked together, depending on specific needs, and this application does not impose any limitations.

[0068] Please refer to Figure 9, which is a schematic diagram of the structure of a counter substrate as shown in Figure 5 according to the third embodiment of this application. As shown in Figure 9, the counter substrate 120 includes a transparent electrode 121, a color filter layer 122, and a light-shielding layer 123. The transparent electrode 121 is stacked on the side of the display medium layer 130 away from the array substrate 110. The transparent electrode 121 is used to form an electric field with the pixel electrode 113 to drive the micro liquid capsule to emit light of a preset gray level, thereby performing image display.

[0069] A color filter layer 122 and a light-shielding layer 123 are arranged side-by-side and stacked on the side of the transparent electrode 121 away from the display medium layer 130. The projection of the color filter layer 122 onto the array substrate 110 covers the pixel electrode 113, and the projection of the light-shielding layer 123 onto the array substrate 110 covers the channel region 112e of the thin-film transistor 112. The light-shielding layer 123 is composed of three layers of color resist materials, thereby achieving light shielding of the channel region 112e. For example, the light-shielding layer 123 includes a first color resist layer 122A, a second color resist layer 122B, and a third color resist layer 122C. The first color resist layer 122A, the second color resist layer 122B, and the third color resist layer 122C are stacked to form a light-shielding region, thereby shielding the channel region 112e from light.

[0070] Please refer to Figure 10, which is a cross-sectional structural diagram of a display panel provided in the fourth embodiment of this application.

[0071] As shown in Figure 10, the array substrate 110 includes a substrate 111 and a plurality of thin film transistors (TFTs) 112 and pixel electrodes 113 arranged in an array. The TFTs 112 include a gate 112a, a semiconductor layer 112b, and source electrodes 112c and drain electrodes 112d disposed on both sides of the semiconductor layer 112b. The middle region of the semiconductor layer 112b is a channel region 112e, and the drain electrode 112d of the TFTs 112 is connected to the pixel electrodes 113.

[0072] The gate electrode 112a is stacked on the substrate 111, and the semiconductor layer 112b is disposed on the side of the gate electrode 112a away from the substrate 111. The array substrate 110 also includes a gate insulating layer 112f disposed between the gate electrode 112a and the semiconductor layer 112b. The gate insulating layer 112f serves to insulate and planarize the gate electrode 112a and the semiconductor layer 112b. The source electrode 112c and the drain electrode 112d are stacked at a predetermined distance on the side of the semiconductor layer 112b away from the gate insulating layer 112f.

[0073] The array substrate 110 also includes a common electrode 114, which is stacked on the substrate 111 at a predetermined distance from the gate electrode 112a. The common electrode 114 and the gate electrode 112a are disposed on the same layer. The gate insulating layer 112f is stacked on the side of the common electrode 114 away from the substrate 111. The drain electrode 112d extends toward the common electrode 114 and is stacked on the side of the gate insulating layer 112f away from the common electrode 114.

[0074] The array substrate also includes a protective layer 115, which covers the semiconductor layer 112b, the source 112c and the drain 112d, and is used to protect the metal layer in the thin film transistor 112, namely the semiconductor layer 112b, the source 112c and the drain 112d, from scratches.

[0075] The pixel electrode 113 is stacked on the protective layer 115 on the side away from the metal layer and is electrically connected to the drain 112d through the protective layer 115. The projection of the pixel electrode 113 on the substrate 111 coincides with the common electrode 114. The pixel electrode 113 receives the data signal and forms a storage capacitor with the common electrode 114 to store the received data signal.

[0076] In an exemplary embodiment, the thin-film transistor 112 can be configured as a top-gate or bottom-gate type as needed, and the semiconductor layer 112b can be configured as an I-shaped or horseshoe-shaped type; this application does not impose any limitations on this. A plurality of scan lines G1-Gn and a plurality of data lines S1-Sm are also disposed on the substrate 111. The scan lines G1-Gn and the data lines S1-Sm intersect to form a plurality of pixel unit regions. Each pixel unit region is provided with at least one thin-film transistor 112, wherein the gate 112a is connected to the scan line, the source 112c is connected to the data line, and the drain 112d is connected to the pixel electrode 113. The source 11c and drain 112d are electrically connected via the semiconductor layer 112b under the control of the scan line to receive scan signals from the scan line, and the pixel electrode 113 receives data signals from the data line to drive the display medium layer 130 to perform image display.

[0077] The opposing substrate 120 includes a transparent electrode 121, a color filter layer 122, a light-shielding layer 123, and a planarization layer 124. The transparent electrode 121 is stacked on the side of the display medium layer 130 away from the array substrate 110. The transparent electrode 121 is used to form an electric field with the pixel electrode 113 to drive the micro liquid capsules to emit white light of a preset gray level. The color filter layer 122 is used to filter the white light emitted by multiple micro liquid capsules into light of different colors, thereby displaying images.

[0078] The color filter layer 122 and the light-shielding layer 123 are disposed adjacent to each other and stacked on the side of the planarization layer 124 away from the transparent electrode 121. The planarization layer 124 is sandwiched between the transparent electrode 121, the color filter layer 122, and the light-shielding layer 123.

[0079] The light-shielding layer 123 is made of an opaque material and includes a first light-shielding part 1231 and a second light-shielding part 1232. The second light-shielding part 1232 is sandwiched between the first light-shielding part 1231 and the color filter layer 122. The first light-shielding part 1231 is stacked on the planarization layer 124, and the second light-shielding part 1232 is disposed through the planarization layer 124. The thickness of the first light-shielding part 1231 is a first thickness d1, and the thickness of the second light-shielding part 1232 is a second thickness d2, wherein the first thickness d1 is less than the second thickness d2.

[0080] In an exemplary embodiment, the first thickness d1 can be set to 800um-1000um, and the second thickness d2 can be set to 3500um-5000um. Of course, it can also be set according to specific needs, and this application does not impose any restrictions.

[0081] The projection of the color filter layer 122 onto the array substrate 110 covers the pixel electrode 113, and the projection of the light-shielding layer 123 onto the array substrate 110 covers the channel region 112e of the thin film transistor 112. The first light-shielding part 1231 is used to prevent vertical ambient light from irradiating the channel region 112e, and the second light-shielding part 1232 is used to prevent oblique ambient light from irradiating the channel region 112e. This effectively avoids the leakage current of the channel region 112e from increasing due to ambient light irradiation, thereby avoiding crosstalk, reduced contrast, deteriorated display effect, or even display errors in the electronic ink display.

[0082] Please refer to Figure 11, which is a schematic diagram of the side layout of the substrate facing Figure 10.

[0083] As shown in Figure 11, the opposing substrate 120 includes multiple light-shielding layers 123, and the color filter layer 122 includes multiple color resist layers. Each light-shielding layer 123 and a color resist layer are arranged side by side to form a sub-pixel and correspondingly cover a thin film transistor 112. Three adjacent sub-pixels constitute a pixel unit P.

[0084] Specifically, the color filter layer 122 includes multiple first color resist layers 122A, multiple second color resist layers 122B, and multiple third color resist layers 122C. The first color resist layer 122A and a light-shielding layer 123 form a first color sub-pixel, the second color resist layer 122B and a light-shielding layer 123 form a second color sub-pixel, and the third color resist layer 122C and a light-shielding layer 123 form a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel constitute a pixel unit P.

[0085] Please refer to Figure 12, which is a side view of the array substrate shown in Figure 10 provided in the fifth embodiment of this application.

[0086] As shown in Figure 12, the opposing substrate 120 includes a transparent electrode 121, a color filter layer 122, a light-shielding layer 123, and a planarization layer 124. The color filter layer 122 and the light-shielding layer 123 are arranged side by side and stacked on the side of the planarization layer 124 away from the transparent electrode 121. The projection of the color filter layer 122 onto the array substrate 110 covers the pixel electrode 113, and the projection of the light-shielding layer 123 onto the array substrate 110 covers the channel region 112e of the thin-film transistor 112.

[0087] In one embodiment, the light-shielding layer 123 is composed of at least two types of color resist materials stacked together to achieve light shading of the channel region 112e. For example, the light-shielding layer 123 includes a first color resist layer 122A and a third color resist layer 122C, which are stacked to form a light-shielding area, thereby shading the channel region 112e. The first color resist layer 122A is a red color resist layer, and the third color resist layer 122C is a blue color resist layer. The light-shielding layer formed by stacking the red and blue color resist layers has a better light-shielding effect.

[0088] Specifically, the light-shielding layer 123 includes a first light-shielding part 1231 and a second light-shielding part 1232. The second light-shielding part 1232 is sandwiched between the first light-shielding part 1231 and the color filter layer 122. The first light-shielding part 1231 is stacked on one side of the planarization layer 124, and the second light-shielding part 1232 is disposed through the planarization layer 124.

[0089] The first light-shielding part 1231 is composed of red and blue color resist stacked together, wherein the thickness of both the red and blue color resist is a first thickness d1.

[0090] The second light-shielding portion 1232 is composed of stacked red and blue color resists, wherein the thickness of both the red and blue color resists is a second thickness d2, which is twice the first thickness d1. The red color resist portion is flush with the adjacent color resist layer, while the blue color resist portion is disposed through the planarization layer 124.

[0091] Among them, the first color resist layer, namely the red color resist layer, can be laid simultaneously with the red color resist in the light-shielding layer 123 and formed as a single unit.

[0092] Of course, it can also be set to a red and green color resist layered configuration, or a green and blue color resist layered configuration. This application does not impose any restrictions on the specific settings required.

[0093] Please refer to Figure 13, which is a flowchart of a method for manufacturing a display panel according to the sixth embodiment of this application. As shown in Figure 13, the specific steps of the manufacturing method are as follows:

[0094] S101, an array substrate is provided. The array substrate includes a plurality of thin-film transistors arranged in an array. The thin-film transistors include a gate, a semiconductor layer stacked with the gate, and a source and a drain disposed on both sides of the semiconductor layer. A channel region is disposed between the source and the drain.

[0095] The array substrate 110 (FIG. 5) includes a substrate 111 and a plurality of thin-film transistors (TFTs) 112 and pixel electrodes 113 arranged in an array. The TFTs 112 include a gate 112a, a semiconductor layer 112b, and source electrodes 112c and drain electrodes 112d disposed on opposite sides of the semiconductor layer 112b. The middle region of the semiconductor layer 112b is a channel region 112e. The drain electrode 112d of the TFTs 112 is connected to the pixel electrodes 113.

[0096] The gate electrode 112a is stacked on the substrate 111, and the semiconductor layer 112b is disposed on the side of the gate electrode 112a away from the substrate 111. The array substrate 110 also includes a gate insulating layer 112f disposed between the gate electrode 112a and the semiconductor layer 112b. The gate insulating layer 112f serves to insulate and planarize the gate electrode 112a and the semiconductor layer 112b. The source electrode 112c and the drain electrode 112d are stacked at a predetermined distance on the side of the semiconductor layer 112b away from the gate insulating layer 112f.

[0097] The array substrate 110 also includes a common electrode 114, which is stacked on the substrate 111 at a predetermined distance from the gate electrode 112a. The common electrode 114 and the gate electrode 112a are disposed on the same layer. The gate insulating layer 112f is stacked on the side of the common electrode 114 away from the substrate 111. The drain electrode 112d extends toward the common electrode 114 and is stacked on the side of the gate insulating layer 112f away from the common electrode 114.

[0098] The array substrate also includes a protective layer 115, which covers the semiconductor layer 112b, the source 112c and the drain 112d, and is used to protect the metal layer in the thin film transistor 112, namely the semiconductor layer 112b, the source 112c and the drain 112d, from scratches.

[0099] The pixel electrode 113 is stacked on the protective layer 115 on the side away from the metal layer and is electrically connected to the drain 112d through the protective layer 115. The projection of the pixel electrode 113 on the substrate 111 coincides with the common electrode 114. The pixel electrode 113 receives the data signal and forms a storage capacitor with the common electrode 114 to store the received data signal.

[0100] S102, a substrate is provided, and multiple light-shielding layers spaced at a predetermined distance are formed on the substrate by a photomask, and a color filter layer is set between two adjacent light-shielding layers to form a facing substrate. The light-shielding layers are used to shield the channel area, and the color filter layer is used to transmit light of different colors. The projection of the light-shielding layers on the array substrate covers the channel area.

[0101] Please refer to Figure 14, which is a schematic diagram of the substrate fabrication process. As shown in Figure 14, a plurality of light-shielding layers 123 with a predetermined distance are formed on the substrate using a half-tone process and a photomask. The light-shielding layer 123 includes a first light-shielding portion 1231 and a second light-shielding portion 1232, wherein the thickness of the first light-shielding portion 1231 is a first thickness d1, and the thickness of the second light-shielding portion 1232 is a second thickness d2, and the first thickness d1 is less than the second thickness d2. A color filter layer 122 of the first thickness d1 is laid between any two adjacent light-shielding layers 123, wherein the color filter layer 122 includes a first color resist layer 122A, a second color resist layer 122B, and a third color resist layer 122C, and the three color resist layers are sequentially laid between two adjacent light-shielding layers 123.

[0102] In an exemplary embodiment, the first thickness d1 can be set to 800um-1000um, and the second thickness can be set to 3500um-5000um. Of course, it can also be set according to specific needs, and this application does not impose any restrictions.

[0103] Please refer to Figure 15, which is a schematic diagram of another facing substrate fabrication process. As shown in Figure 15, multiple light-shielding layers 123 and a first color resist layer 122A with predetermined spacing are formed on the substrate using a photomask. The first color resist layer 122A is disposed between two adjacent light-shielding layers 123. Both the light-shielding layers 123 and the first color resist layer 122A are made of a first color resist material. The light-shielding layer 123 includes a first light-shielding portion 1231 and a second light-shielding portion 1232. The thickness of the first light-shielding portion 1231 is a first thickness d1, and the thickness of the second light-shielding portion 1232 is a second thickness d2, which is twice the thickness of the first thickness d1. The thickness of the first color resist layer 122A is the second thickness d2.

[0104] Then, a second color resist and a third color resist layer are laid between adjacent light-shielding layers 123 to form a second color resist layer 122B and a third color resist layer 122C. A third color resist of first thickness d1 is laid at the position of the first light-shielding portion 1231, and a third color resist of second thickness d2 is laid at the position of the second light-shielding portion 1232, thereby forming a first light-shielding portion 1231 and a second light-shielding portion 1232 formed by stacking the first and third color resists. That is, a portion of the first light-shielding portion 1231 and a portion of the second light-shielding portion 1232 are formed by etching the first color resist using a photomask, and then the third color resist is stacked on top of the first and second light-shielding portions 1231 and 1232 respectively to form the first and second light-shielding portions 1231 and 1232.

[0105] Finally, a planarization layer 124 is formed between the protruding second light-shielding portions 1232 to form a facing substrate 120. The second light-shielding portions 1232 in the light-shielding layer 123 are flush with the planarization layer 124.

[0106] S103, a plurality of micro liquid capsules are disposed between the array substrate and the opposing substrate to form a display medium layer. The micro liquid capsules are sealed spheres and encapsulate white particles, black particles and a transparent dispersion medium inside. The white particles and black particles carry different charges. The white particles and black particles are immersed in the transparent dispersion medium and can move freely. The array substrate includes a plurality of thin film transistors arranged in an array. The light-shielding layer is used to block external light from being transmitted through the opposing substrate to the channel region via the white particles and black particles. The thin film transistors are used to drive the white particles and black particles to move according to the data signal and make the micro liquid capsules jointly form an image on the opposing substrate side to perform image display.

[0107] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A display panel, characterized in that, The system includes an array substrate, a counter substrate, and a display medium layer sandwiched between the array substrate and the counter substrate. The display medium layer comprises multiple micro-liquid capsules, each of which is a sealed sphere encapsulating white particles, black particles, and a transparent dispersion medium inside. The white and black particles carry different charges and are immersed in the transparent dispersion medium, allowing them to move freely. The array substrate includes multiple thin-film transistors arranged in an array. The thin-film transistors drive the white and black particles to move according to a data signal, causing the micro-liquid capsules to collectively form an image on one side of the counter substrate for image display. Each thin-film transistor includes a gate, a semiconductor layer stacked with the gate, and source and drain electrodes disposed on both sides of the semiconductor layer. A channel region is provided between the source and drain electrodes. The counter substrate further includes a light-shielding layer, a color filter layer, a planarization layer, and a transparent electrode. The color filter layer is used to transmit light of different colors. The projection of the light-shielding layer on the array substrate covers the channel area, which is used to block external light from being transmitted to the channel area through the white and black particles via the opposing substrate. The transparent electrode is disposed on the side of the display medium layer away from the array substrate. The transparent electrode is used to form an electric field with the pixel electrode on the array substrate to drive the micro liquid capsule to emit white light of a preset gray level. The color filter layer and the light-shielding layer are arranged side by side and stacked on the side of the transparent electrode away from the display medium layer. The planarization layer is sandwiched between the transparent electrode, the color filter layer, and the light-shielding layer. The light-shielding layer includes a first light-shielding part and a second light-shielding part. The first light-shielding part has the same thickness as the color filter layer and is flush with the color filter layer. The second light-shielding part is disposed adjacent to the first light-shielding part and protrudes to one side of the planarization layer to penetrate the planarization layer.

2. The display panel as described in claim 1, characterized in that, The light-shielding layer includes any two of the first color resist, the second color resist, and the third color resist. The two different colors of color resist are stacked in any order to shield the channel area from light.

3. The display panel as described in claim 2, characterized in that, The light-shielding layer includes a first color resist, a second color resist, and a third color resist, which are stacked in any order to shield the channel area from light.

4. The display panel as described in claim 3, characterized in that, The first light-shielding portion includes a first color resist and a third color resist, which are stacked together and the third color resist is disposed adjacent to the planarization layer; the second light-shielding portion includes the first color resist and the third color resist, which are disposed flush with the color filter layer and the third color resist is disposed through the planarization layer.

5. The display panel as described in claim 4, characterized in that, In the first light-shielding part, the first color resist and the second color resist have the same thickness, which is a first thickness. In the second light-shielding part, the first color resist and the second color resist have the same thickness, which is a second thickness, and the second thickness is twice the first thickness.

6. A display terminal, characterized in that, It includes a power module and a display panel as described in any one of claims 1-5, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.

7. A method for manufacturing a display panel, characterized in that, include: An array substrate is provided, comprising a plurality of thin-film transistors arranged in an array. Each thin-film transistor includes a gate, a semiconductor layer stacked with the gate, and source and drain electrodes disposed on opposite sides of the semiconductor layer, with a channel region between the source and drain electrodes. A substrate is also provided, on which a plurality of light-shielding layers spaced at predetermined intervals are formed using a photomask. A color filter layer is disposed between adjacent light-shielding layers to form a facing substrate. The light-shielding layers are used to shield the channel region from light, and the color filter layers are used to transmit light of different colors. The projection of the light-shielding layers onto the array substrate covers the channel region. Each light-shielding layer includes a first light-shielding portion and a second light-shielding portion. The first light-shielding portion is flush with the color filter layer, and the second light-shielding portion protrudes away from the substrate. A transparent material is filled between any two adjacent second light-shielding portions. A planarization layer is formed, which is flush with the second light-shielding portion. A plurality of micro-liquid capsules are disposed between the array substrate and the opposing substrate to form a display medium layer. Each micro-liquid capsule is a sealed sphere containing white particles, black particles, and a transparent dispersion medium. The white and black particles carry different charges and are immersed in the transparent dispersion medium, allowing them to move freely. The array substrate includes a plurality of thin-film transistors arranged in an array. The light-shielding layer blocks external light from passing through the opposing substrate and transmitting through the white and black particles to the channel region. The thin-film transistors drive the white and black particles to move according to a data signal, causing the micro-liquid capsules to collectively form an image on one side of the opposing substrate to perform image display.

8. The method for manufacturing a display panel as described in claim 7, characterized in that, A first light-shielding portion and a second light-shielding portion are formed by etching a first color resist and a third color resist using a photomask. In the first light-shielding portion, the thickness of the first color resist and the third color resist is a first thickness, and in the second light-shielding portion, the thickness of the first color resist and the third color resist is a second thickness.

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