Clock frequency adjustment system, method and electronic device

Abstract

The present application proposes a clock frequency adjustment system, method and electronic device, including a timing generator and a phase-locked loop, wherein the timing generator and the phase-locked loop are communicatively connected; the timing generator is used to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; wherein the number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset ratio threshold. Through multiple small-amplitude adjustments, loss of lock is avoided, thereby saving the time of frequency adjustment, and no additional hardware cost is added.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular, to a clock frequency adjustment system, method and electronic device. Background Art

[0002] Dynamic voltage and frequency scaling (DVFS) is a technology for optimizing chip power consumption. It dynamically adjusts the chip's operating frequency and voltage according to the different computing power requirements of the applications or load tasks running on the chip (for the same chip, the higher the frequency, the higher the required voltage). Specifically, by adjusting the chip's frequency and voltage, the chip can be at different performance levels when processing tasks with different loads, thereby achieving the purpose of energy saving.

[0003] How to achieve frequency regulation quickly and stably has become a difficult problem that technical personnel in this field continue to pay attention to. Summary of the invention

[0004] The purpose of the present application is to provide a clock frequency adjustment system, method and electronic device to at least partially improve the above-mentioned problems.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a clock frequency adjustment system, the adjustment system comprising a timing generator and a phase-locked loop, the timing generator and the phase-locked loop being communicatively connected;

[0007] The timing generator is used to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient;

[0008] Among them, the number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset proportional threshold.

[0009] Optionally, the timing generator is further configured to synchronously adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop for the i-th time according to the acquired fine adjustment amplitude, so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop to a target fine adjustment coefficient;

[0010] Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

[0011] Optionally, the timing generator includes a first configuration register, a second configuration register, a third configuration register, a fourth configuration register, an intermediate value register control state machine and a first output register, the first configuration register is used to store the target coarse adjustment coefficient, the second configuration register is used to store the single adjustment amplitude, the third configuration register is used to store the number of times to be adjusted, the fourth configuration register is used to store the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop, and the intermediate value register is used to store the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop;

[0012] The control state machine is used for writing the starting value into the intermediate value register as the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop when it is detected that the value in the first configuration register is modified;

[0013] The control state machine is further used to write the sum of the single adjustment amplitude and the current value into the first output register to transmit to the phase-locked loop, so that the phase-locked loop adjusts its frequency multiplication coarse adjustment coefficient according to the value in the first output register;

[0014] The control state machine is also used to write the value in the first output register into the intermediate value register to update the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop;

[0015] The control state machine is further used to record the number of adjustments after writing the single adjustment amplitude into the first output register each time;

[0016] The control state machine is further configured to repeatedly write the sum of the single adjustment amplitude and the current value into the first output register when the number of times adjusted is less than the number of times to be adjusted, until the number of times adjusted is equal to the number of times to be adjusted.

[0017] Optionally, the timing generator further includes a fifth configuration register and a second output register, wherein the fifth configuration register is used to store the fine-tuning amplitude;

[0018] The control state machine is also used to write the fine adjustment amplitude into the second output register when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop for the i-th time, so as to transmit it to the phase-locked loop, so that the phase-locked loop adjusts its frequency multiplication fine adjustment coefficient according to the fine adjustment amplitude;

[0019] Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

[0020] Optionally, the clock frequency adjustment system further comprises a processor, and the processor is communicatively connected with the timing generator;

[0021] The processor is used to determine the target coarse adjustment coefficient, the single adjustment amplitude, the number of times to be adjusted, the starting value and the fine adjustment amplitude according to the target frequency point and the starting frequency point of the phase-locked loop;

[0022] The processor is also used to write the target coarse adjustment coefficient, the single adjustment amplitude, the number of times to be adjusted and the starting value into the first configuration register, the second configuration register, the third configuration register, the fourth configuration register and the fifth configuration register respectively.

[0023] Optionally, the processor is further configured to match a corresponding target frequency point according to a current load task of the system.

[0024] Optionally, the clock frequency adjustment system further comprises a selector and a status register, wherein the selector is respectively connected to the timing generator, the status register, the phase-locked loop and the processor, and the processor is connected to the status register;

[0025] The processor is also used to determine whether it is necessary to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the target frequency point and the starting frequency point;

[0026] The processor is also used to control the selector to keep the communication link between the timing generator and the phase-locked loop unblocked when the frequency multiplication coarse adjustment coefficient of the phase-locked loop needs to be adjusted;

[0027] The processor is also used to control the selector to keep the communication link between the status register and the phase-locked loop open when there is no need to adjust the coarse frequency multiplication coefficient of the phase-locked loop, and write the fine-tuning amplitude and / or target division coefficient into the status register to adjust the fine-tuning coefficient and / or division coefficient of the phase-locked loop.

[0028] In a second aspect, an embodiment of the present application provides a clock frequency adjustment method, which is applied to an adjustment system, wherein the adjustment system includes a timing generator and a phase-locked loop, wherein the timing generator and the phase-locked loop are communicatively connected, and the method includes:

[0029] The timing generator adjusts the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient;

[0030] Among them, the number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset proportional threshold.

[0031] Optionally, the method further comprises:

[0032] The timing generator adjusts the frequency multiplication fine adjustment coefficient of the phase-locked loop synchronously when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop for the i-th time according to the acquired fine adjustment amplitude, so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop to the target fine adjustment coefficient;

[0033] Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

[0034] In a third aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned clock frequency adjustment system.

[0035] Compared with the prior art, a clock frequency adjustment system, method and electronic device provided by the embodiment of the present application include a timing generator and a phase-locked loop, wherein the timing generator and the phase-locked loop are communicatively connected; the timing generator is used to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to the target coarse adjustment coefficient; wherein the number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset ratio threshold. Through multiple small adjustments, loss of lock is avoided, thereby saving the time of frequency adjustment, and no additional hardware cost is added.

[0036] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 One of the structural schematic diagrams of the clock frequency adjustment system provided in the embodiment of the present application;

[0039] Figure 2 One of the structural schematic diagrams of the timing generator provided in the embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of the clock frequency adjustment system provided in the embodiment of the present application is provided in the second embodiment;

[0041] Figure 4 The structural schematic diagrams of the clock frequency adjustment system provided in the embodiment of the present application are as follows;

[0042] Figure 5 A flowchart of a clock frequency adjustment method provided in an embodiment of the present application.

[0043] In the figure: 10-timing generator; 20-phase-locked loop; 30-processor; 40-status register; 50-selector; 101-first configuration register; 102-second configuration register; 103-third configuration register; 104-fourth configuration register; 105-fifth configuration register; 106-control state machine; 107-intermediate value register; 108-first output register; 109-second output register. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0046] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0047] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0048] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0049] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0050] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0051] There are two possible ways to adjust the frequency using DVFS technology, namely, frequency divider adjustment and phase-locked loop adjustment. Phase-locked loop adjustment and frequency divider adjustment have their own advantages and disadvantages. For phase-locked loop adjustment, a long locking time is required from the beginning of adjustment to the final stabilization, and during this time, the clock signal output may cause execution errors. Therefore, in processors that use phase-locked loops to adjust the frequency, two phase-locked loops (PLLs) are generally used to implement it. The current PLL will switch to another standby PLL to provide the clock when adjusting the phase-locked loop, which increases the hardware cost and power consumption. Moreover, when the lock is lost, the locking time of the PLL is more than tens of microseconds. Therefore, when the phase-locked loop is used to adjust the frequency, it is not suitable for frequent adjustment, which also makes it unsuitable for fine-grained adjustment when designing the DVFS algorithm. Compared with the phase-locked loop to adjust the frequency, the frequency divider adjustment method is much faster. Moreover, there is no locking time, and it only takes a few clock cycles from receiving the signal to generating a stable output. Therefore, relatively fast frequency adjustment can be achieved, but this adjustment method is not suitable for all frequency point changes. Today, the DVFS adjustment granularity is getting finer and finer, and the difference between two adjacent DVFS frequency points is getting smaller and smaller, which cannot be achieved through a frequency divider. Even if it can be achieved, it is achieved by increasing the PLL phase-locked loop frequency, which increases the power consumption of the PLL.

[0052] In order to overcome the above problems, the embodiment of the present application provides a clock frequency adjustment system, which optimizes the DVFS implementation scheme, realizes relatively fast frequency adjustment without increasing the cost, and ensures the smooth implementation of fine-grainedness in the DVFS adjustment process.

[0053] Specifically, please refer to Figure 1 , Figure 1 This is one of the structural schematic diagrams of the clock frequency adjustment system provided in the embodiment of the present application.

[0054] like Figure 1 As shown, the regulation system includes a timing generator 10 (PLL sequencer) and a phase-locked loop 20 (PLL), and the timing generator 10 and the phase-locked loop 20 are communicatively connected.

[0055] The timing generator 10 is used to adjust the frequency multiplication coarse adjustment coefficient (FBDIV) of the phase-locked loop 20 according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 to a target coarse adjustment coefficient.

[0056] Among them, the number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 is equal to the product of a single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of a single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset proportional threshold.

[0057] For example, if the starting value is 50 and the target coarse adjustment coefficient is 100, the absolute value of the ratio of the single adjustment amplitude to the starting value (50) is less than the preset ratio threshold. If the starting value is 100 and the target coarse adjustment coefficient is 50, the absolute value of the ratio of the single adjustment amplitude to the target coarse adjustment coefficient (50) is less than the preset ratio threshold.

[0058] Optionally, the value of the ratio threshold may be, but is not limited to, 10%. When the single change of the FBDIV of the PLL is within the ratio threshold (eg, +-10%), the PLL will not lose lock and can be adjusted to the corresponding frequency within one reference clock.

[0059] It should be understood that if the coarse adjustment coefficient of the phase-locked loop is directly adjusted from the starting value to the target coarse adjustment coefficient, the phase-locked loop may be unlocked, and it will take a long time to complete the phase lock. In the present application, multiple small adjustments are made to avoid unlocking, thereby saving frequency adjustment time, and no two PLLs are required, which will not increase additional hardware costs.

[0060] In summary, the embodiment of the present application provides a clock frequency adjustment system, including a timing generator and a phase-locked loop, the timing generator and the phase-locked loop are communicatively connected; the timing generator is used to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; wherein the number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset ratio threshold. Through multiple small adjustments, loss of lock is avoided, thereby saving the time of frequency adjustment, and no additional hardware cost is added.

[0061] In an optional implementation, the timing generator 10 is further configured to synchronously adjust the frequency multiplication fine adjustment coefficient (FRAC) of the phase-locked loop 20 when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 for the i-th time according to the acquired fine adjustment amplitude, so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop 20 to the target fine adjustment coefficient;

[0062] Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop 20 is equal to the fine-tuning amplitude.

[0063] Optionally, each time the coarse frequency multiplication coefficient of the phase-locked loop 20 is adjusted, the fine frequency multiplication coefficient (FRAC) of the phase-locked loop 20 is adjusted synchronously. Alternatively, the fine frequency multiplication coefficient (FRAC) of the phase-locked loop 20 may be adjusted synchronously only when the coarse frequency multiplication coefficient of the phase-locked loop 20 is adjusted at a certain time. For example, the fine frequency multiplication coefficient (FRAC) of the phase-locked loop 20 is adjusted synchronously when the coarse frequency multiplication coefficient of the phase-locked loop 20 is adjusted for the last time (i=N).

[0064] It should be understood that by adjusting the frequency multiplication fine-tuning coefficient, it is further ensured that the frequency output by the phase-locked loop can accurately match the needs of the system.

[0065] Regarding the specific structure of the timing generator, the present application embodiment also provides a possible implementation method, please refer to Figure 2 , Figure 2 This is one of the structural schematic diagrams of the timing generator provided in the embodiment of the present application.

[0066] like Figure 2 As shown, the timing generator 10 includes a first configuration register 101 (target_FBDIV), a second configuration register 102 (step_size), a third configuration register 103 (step_count), a fourth configuration register 104 (start_FBDIV), an intermediate value register 107 (current_FBDIV) control state machine 106 and a first output register 108 (output_FBDIV). The first configuration register 101 is used to store the target coarse adjustment coefficient, the second configuration register 102 is used to store the single adjustment amplitude (FBDIV step), the third configuration register 103 is used to store the number of times to be adjusted (total step), the fourth configuration register 104 is used to store the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20, and the intermediate value register 107 is used to store the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20.

[0067] The starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 refers to the value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop before adjustment. The starting value and the target coarse adjustment coefficient can be, but are not limited to, written into the corresponding register by the processor 30 (MCU or CPU) described below.

[0068] Optionally, the control state machine 106 includes three states, namely, an initial (INIT) state, an execution (SEND) state, and a check (CHK) state. When no adjustment is required, the control state machine 106 is in the INIT state and monitors the first configuration register 101. When it is detected that the value in the first configuration register 101 is modified, the control state machine 106 jumps to the SEND state.

[0069] The control state machine 106 is used to write the initial value into the intermediate value register 107 as the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 when it is detected that the value in the first configuration register 101 is modified.

[0070] It should be understood that when it is detected that the value in the first configuration register 101 is modified, it means that the target coarse adjustment coefficient is written into the first configuration register 101, and the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 needs to be adjusted. The current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 is needed in the adjustment process, so the starting value is written into the intermediate value register 107 as the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20.

[0071] The control state machine 106 is further used to write the sum of the single adjustment amplitude and the current value into the first output register 108 for transmission to the phase-locked loop 20 , so that the phase-locked loop 20 adjusts its frequency multiplication coarse adjustment coefficient according to the value in the first output register 108 .

[0072] For example, assume that the starting value is 50 and the single adjustment amplitude is 10. After entering the SEND state, the control state machine 106 will write the starting value (50) in the fourth configuration register 104 into the intermediate value register 107, that is, the current value in the intermediate value register 107 is 50. The control state machine 106 will also obtain the sum (60) of the current value (50) in the intermediate value register 107 and the single adjustment amplitude (10). Then, the sum (60) is written into the first output register 108, and the sum (60) is sent to the phase-locked loop 20 through the first output register 108. The phase-locked loop 20 adjusts its frequency multiplication coarse adjustment coefficient from 50 to 60, and will not lose lock.

[0073] It should be understood that in the scheme of the present application, the adjustment of the frequency multiplication coarse adjustment coefficient is performed in multiple times. In order to facilitate the control state machine to obtain the current value of the phase-locked loop 20, the embodiment of the present application also provides a possible implementation method, please refer to the following.

[0074] The control state machine 106 is further used to write the value in the first output register 108 into the intermediate value register 107 to update the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 .

[0075] Please continue to refer to the above example. The control state machine 106 can also write the sum (60) into the intermediate value register 107 as the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20, so as to facilitate use in subsequent adjustments.

[0076] It should be understood that in order to ensure that the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 can be adjusted to the target coarse adjustment coefficient, it is necessary to manage and count the number of adjustments, and please refer to the following for details.

[0077] The control state machine 106 is further configured to record the number of adjustments after writing a single adjustment amplitude into the first output register 108 each time.

[0078] Optionally, the initial value of the adjusted number of times (step_number) may be 0. After the first adjustment, step_number+1 is executed, the adjusted number of times (step_number)=1, and so on, until the adjusted number of times (step_number)=the number to be adjusted.

[0079] In an optional implementation, after counting the number of adjustments (step_number), a check is required to confirm whether the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 has been adjusted to the target coarse adjustment coefficient. At this time, the control state machine 106 enters the CHK state, and then makes a judgment based on the number of adjustments. Please refer to the following for details.

[0080] The control state machine 106 is further configured to repeatedly write the sum of the single adjustment amplitude and the current value into the first output register 108 when the number of times adjusted is less than the number to be adjusted, until the number of times adjusted is equal to the number to be adjusted.

[0081] It should be understood that if the number of times adjusted is less than the number to be adjusted, it means that the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 has not been adjusted to the target coarse adjustment coefficient and further adjustment is required. At this time, the control state machine 106 jumps to the SEND state.

[0082] Continuing to refer to the above example, assume that the starting value is 50, the single adjustment amplitude is 10, the target coarse adjustment coefficient is 100, and the number of times to be adjusted is 5. At the second time, the sum of the single adjustment amplitude and the current value is 70, the third time corresponds to 80, the fourth time corresponds to 90, and the fifth time corresponds to 100. During the adjustment process, the value of the intermediate value register 107 is transformed along with the value of the first output register 108.

[0083] When the number of times adjusted is equal to the number to be adjusted, it means that the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 has been adjusted to the target coarse adjustment coefficient, so that the adjustment of the frequency multiplication coarse adjustment coefficient is completed.

[0084] Optionally, after the adjustment of the frequency multiplication coarse adjustment coefficient is completed, the control state machine 106 jumps to the INIT state, and the number of adjusted times (step_number) can be cleared.

[0085] Please continue to refer to Figure 2 In an optional implementation, the timing generator 10 further includes a fifth configuration register 105 (target_FRAC) and a second output register 109 (output_FRAC), and the fifth configuration register 105 is used to store the fine-tuning amplitude.

[0086] The control state machine 106 is also used to write the fine adjustment amplitude into the second output register 109 when adjusting the coarse frequency adjustment coefficient of the phase-locked loop 20 for the i-th time, so as to transmit it to the phase-locked loop 20, so that the phase-locked loop 20 adjusts its frequency adjustment coefficient according to the fine adjustment amplitude.

[0087] Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop 20 is equal to the fine-tuning amplitude.

[0088] It should be understood that the timing generator 10 is a hardware module that automatically performs PLL settings according to register configuration, and can make the PLL output the target frequency by setting the PLL once or multiple times in a short time, and the PLL remains locked during the entire adjustment period.

[0089] Please refer to Figure 3 , Figure 3 The following is a schematic diagram of the structure of the clock frequency adjustment system provided in the embodiment of the present application. Figure 3 As shown, the clock frequency adjustment system further includes a processor 30, which is communicatively connected to the timing generator 10. The processor 30 can write a value into a register in the timing generator 10.

[0090] Optionally, the processor 30 may be an integrated circuit chip having signal processing capability. The processor 30 may be a general-purpose processor, including a central processing unit (CPU), a microcontroller unit (MCU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components.

[0091] In an optional implementation, the processor 30 is used to determine a target coarse adjustment coefficient, a single adjustment amplitude, a number of times to be adjusted, a starting value, and a fine adjustment amplitude according to a target frequency point and a starting frequency point of the phase-locked loop 20 .

[0092] The starting frequency point is the clock frequency point of the phase-locked loop 20 before adjustment.

[0093] The processor 30 is further configured to write the target coarse adjustment coefficient, the single adjustment amplitude, the number of times to be adjusted and the starting value into the first configuration register 101 , the second configuration register 102 , the third configuration register 103 , the fourth configuration register 104 and the fifth configuration register 105 , respectively.

[0094] In an optional implementation, the processor 30 is further configured to match a corresponding target frequency point according to a current load task of the system.

[0095] As mentioned above, the operating frequency and voltage of the chip are dynamically adjusted according to the different computing power requirements of the applications or load tasks running on the chip.

[0096] Please refer to Figure 4 , Figure 4 The structural diagram of the clock frequency adjustment system provided in the embodiment of the present application is shown in FIG3. Figure 4 As shown, the clock frequency adjustment system further includes a selector 50 (MUX) and a state register 40 (PLL registers). The selector 50 is respectively connected to the timing generator 10 , the state register 40 , the phase-locked loop 20 and the processor 30 , and the processor 30 is connected to the state register 40 .

[0097] The processor 30 is further configured to determine whether the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 needs to be adjusted according to the target frequency point and the starting frequency point.

[0098] The processor 30 is also used to control the selector 50 to keep the communication link between the timing generator 10 and the phase-locked loop 20 open when the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 needs to be adjusted.

[0099] The processor 30 is also used to control the selector 50 to keep the communication link between the status register 40 and the phase-locked loop 20 open when there is no need to adjust the coarse frequency multiplication coefficient of the phase-locked loop 20, and write the fine-tuning amplitude and / or the target division coefficient into the status register 40 to adjust the fine-tuning coefficient and / or the division coefficient of the phase-locked loop 20.

[0100] Alternatively, if Figure 4 As shown, when performing DVFS modulation, the processor 30 selects to directly configure the PLL registers or the PLL sequencer according to the target frequency point and the starting frequency point. When the target frequency point can be reached only by changing the frequency divider (POSTDIV1 / POSTDIV2), the PLL registers path is selected, otherwise the PLL sequencer path is selected. The processor 30 switches the selector 50 to the corresponding path by configuring HW_SEL. When HW_SEL=1, the PLL sequencer path is selected to control the input of the PLL. When HW_SEL=0, the PLL registers output is selected to control the input of the PLL.

[0101] Please continue to refer to Figure 4 In a possible implementation, the clock frequency adjustment system further includes Retiming, which is arranged between the selector 50 and the phase-locked loop 20. Optionally, the Retiming in the clock frequency adjustment system is adaptively arranged according to the requirements of the phase-locked loop 20, which is not necessary.

[0102] The clock frequency adjustment system provided by the embodiment of the present application can quickly switch the frequency of DVFS. According to the actual CPU DVFS frequency range and PLL configuration parameters, in the worst case, the frequency switching only takes 250ns, which is significantly optimized compared to the dozens of us of the phase-locked loop adjustment method, and solves the slow speed problem of the phase-locked loop adjustment method. It is suitable for switching between all DVFS frequency points, and solves the problem of the small coverage frequency range of the divider adjustment method. The efficiency of DVFS is improved, thereby improving the energy efficiency ratio of the SOC.

[0103] The clock frequency adjustment method provided in the embodiment of the present application can be applied to, but not limited to, the above-mentioned clock frequency adjustment system. For the specific process, please refer to Figure 5 The clock frequency adjustment method includes: S1001, S1002 and S1003, which are described in detail below.

[0104] S1001, the timing generator obtains a single adjustment amplitude and a number of times to be adjusted.

[0105] S1002, the timing generator adjusts the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient.

[0106] Among them, the number of times to be adjusted represents the number of times the phase-locked loop's frequency multiplication coarse adjustment coefficient is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the phase-locked loop's frequency multiplication coarse adjustment coefficient is equal to the product of a single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of a single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset proportional threshold.

[0107] S1003, the timing generator adjusts the frequency multiplication fine adjustment coefficient of the phase-locked loop synchronously when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop for the i-th time according to the obtained fine adjustment amplitude, so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop to the target fine adjustment coefficient.

[0108] Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

[0109] It should be noted that the clock frequency adjustment method provided in this embodiment can perform the functions and uses shown in the above clock frequency adjustment system embodiment to achieve the corresponding technical effects. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above embodiments.

[0110] The embodiment of the present application also provides an electronic device, including the above-mentioned clock frequency adjustment system. The electronic device can be, but is not limited to, a terminal device such as a mobile phone, a computer, and a server.

[0111] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0112] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A clock frequency adjustment system, characterized in that: The regulation system comprises a timing generator and a phase-locked loop, wherein the timing generator and the phase-locked loop are communicatively connected; The timing generator is used to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; The number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset ratio threshold; The timing generator is also used to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop synchronously when the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted for the i-th time according to the acquired fine adjustment amplitude, so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop to the target fine adjustment coefficient; Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

2. The clock frequency adjustment system according to claim 1, characterized in that: The timing generator includes a first configuration register, a second configuration register, a third configuration register, a fourth configuration register, an intermediate value register, a control state machine and a first output register, the first configuration register is used to store the target coarse adjustment coefficient, the second configuration register is used to store the single adjustment amplitude, the third configuration register is used to store the number of times to be adjusted, the fourth configuration register is used to store the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop, and the intermediate value register is used to store the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop; The control state machine is used for writing the starting value into the intermediate value register as the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop when it is detected that the value in the first configuration register is modified; The control state machine is further used to write the sum of the single adjustment amplitude and the current value into the first output register to transmit to the phase-locked loop, so that the phase-locked loop adjusts its frequency multiplication coarse adjustment coefficient according to the value in the first output register; The control state machine is also used to write the value in the first output register into the intermediate value register to update the current value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop; The control state machine is further used to record the number of adjustments after writing the single adjustment amplitude into the first output register each time; The control state machine is further configured to repeatedly write the sum of the single adjustment amplitude and the current value into the first output register when the number of times adjusted is less than the number of times to be adjusted, until the number of times adjusted is equal to the number of times to be adjusted.

3. The clock frequency adjustment system according to claim 2, characterized in that: The timing generator further comprises a fifth configuration register and a second output register, wherein the fifth configuration register is used to store a fine adjustment amplitude; The control state machine is also used to write the fine adjustment amplitude into the second output register when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop for the i-th time, so as to transmit it to the phase-locked loop, so that the phase-locked loop adjusts its frequency multiplication fine adjustment coefficient according to the fine adjustment amplitude; Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

4. The clock frequency adjustment system according to claim 3, characterized in that: The clock frequency adjustment system further includes a processor, wherein the processor is communicatively connected to the timing generator; The processor is used to determine the target coarse adjustment coefficient, the single adjustment amplitude, the number of times to be adjusted, the starting value and the fine adjustment amplitude according to the target frequency point and the starting frequency point of the phase-locked loop; The processor is also used to write the target coarse adjustment coefficient, the single adjustment amplitude, the number of times to be adjusted and the starting value into the first configuration register, the second configuration register, the third configuration register, the fourth configuration register and the fifth configuration register respectively.

5. The clock frequency adjustment system according to claim 4, characterized in that: The processor is also used to match the corresponding target frequency point according to the current load task of the system.

6. The clock frequency adjustment system according to claim 4, characterized in that: The clock frequency adjustment system further comprises a selector and a status register, wherein the selector is respectively connected to the timing generator, the status register, the phase-locked loop and the processor, and the processor is connected to the status register; The processor is also used to determine whether it is necessary to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the target frequency point and the starting frequency point; The processor is also used to control the selector to keep the communication link between the timing generator and the phase-locked loop unblocked when the frequency multiplication coarse adjustment coefficient of the phase-locked loop needs to be adjusted; The processor is also used to control the selector to keep the communication link between the status register and the phase-locked loop open when there is no need to adjust the coarse frequency multiplication coefficient of the phase-locked loop, and write the fine-tuning amplitude and / or target division coefficient into the status register to adjust the fine-tuning coefficient and / or division coefficient of the phase-locked loop.

7. A clock frequency adjustment method, characterized in that: Applied to a regulation system, the regulation system includes a timing generator and a phase-locked loop, the timing generator and the phase-locked loop are communicatively connected, and the method includes: The timing generator adjusts the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the acquired single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; The number of times to be adjusted represents the number of times the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted, the difference between the target coarse adjustment coefficient and the starting value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the starting value and the target coarse adjustment coefficient is less than a preset ratio threshold; The timing generator adjusts the frequency multiplication fine adjustment coefficient of the phase-locked loop synchronously when adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop for the i-th time according to the acquired fine adjustment amplitude, so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop to the target fine adjustment coefficient; Wherein, 1≤i≤N, N represents the number of times to be adjusted, and the difference between the target fine-tuning coefficient and the starting value of the frequency multiplication fine-tuning coefficient of the phase-locked loop is equal to the fine-tuning amplitude.

8. An electronic device, characterized in that: A clock frequency adjustment system comprising any one of claims 1 to 6.

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