Shift register, gate drive circuit, array substrate and display device

Abstract

Embodiments of the present disclosure provide a shift register, a gate drive circuit, an array substrate and a display device. The shift register comprises: a pull-down module coupled with a second power supply end, a pull-up node, a pull-down node and a control node respectively, configured to provide a signal of the second power supply end to the pull-down node and the control node under the control of the pull-up node; a noise release module coupled with a first control power supply end, the control node and the pull-down node respectively, configured to provide a signal of the first control power supply end to the control node under the control of the first control power supply end, and provide a signal of the first control power supply end to the pull-down node under the control of the control node; and a bootstrap module coupled with the control node and the pull-down node. The technical solution of the present disclosure optimizes the noise release effect, improves the reliability screen problem of the display product, and improves the service life of the shift register and the product competitiveness.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, an array substrate, and a display device. Background Technology

[0002] As display technology matures, the demand for narrow bezels and high-frequency displays in small-sized display products is increasing. GOA (Gate on Array) technology integrates the gate switch driving circuit on the array substrate of the display panel, achieving narrow bezels and low cost, and has been widely used in small-sized display products.

[0003] In narrow-bezel display products, the limited space for GOA wiring causes some transistors to be smaller in size due to insufficient wiring space, resulting in reliable screen flickering issues and reducing product competitiveness. Summary of the Invention

[0004] This disclosure provides a shift register, a gate drive circuit, an array substrate, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the present disclosure, an embodiment of the present disclosure provides a shift register, including:

[0006] The pull-up module is coupled to the input signal terminal, the first power supply terminal and the pull-up node respectively, and is configured to provide the first power supply terminal signal to the pull-up node under the control of the input signal terminal.

[0007] The pull-down module is coupled to the second power supply terminal, the pull-up node, the pull-down node, and the control node, respectively, and is configured to provide the second power supply terminal signal to the pull-down node and the control node under the control of the pull-up node;

[0008] The noise reduction module is coupled to the first control power supply terminal, the control node and the pull-down node respectively. It is configured to provide the signal of the first control power supply terminal to the control node under the control of the first control power supply terminal, and to provide the signal of the first control power supply terminal to the pull-down node under the control of the control node.

[0009] The bootstrap module is coupled to both the control node and the drop-down node.

[0010] The output module is coupled to the clock signal terminal, the pull-up node, and the output signal terminal respectively, and is configured to provide the clock signal terminal to the output signal terminal under the control of the pull-up node.

[0011] The first reset module is coupled to the reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the reset signal terminal.

[0012] The reset control module is coupled to the pull-down node, the second power supply terminal, and the pull-up node respectively, and is configured to provide the signal of the second power supply terminal to the pull-up node under the control of the pull-down node;

[0013] The second reset module is coupled to the pull-down node, the second power supply terminal, and the output signal terminal, and is configured to provide the signal from the second power supply terminal to the output signal terminal under the control of the pull-down node.

[0014] In one embodiment, the bootstrap module includes a bootstrap capacitor, the first plate of which is coupled to a control node and a pull-down node, respectively.

[0015] In one embodiment, the noise reduction module includes a fifth transistor and a ninth transistor. The gate of the ninth transistor is coupled to a first control power supply terminal, and the first and second terminals of the ninth transistor are coupled to the first control power supply terminal and a control node, respectively. The gate of the fifth transistor is coupled to the control node, the first terminal of the fifth transistor is coupled to the first control power supply terminal, and the second terminal of the fifth transistor is coupled to a pull-down node.

[0016] In one embodiment, the bootstrap module includes a bootstrap capacitor, the first plate and the second plate of the bootstrap capacitor being coupled to a control node and a pull-down node, respectively. The first plate of the bootstrap capacitor includes the gate of a fifth transistor, and the second plate of the bootstrap capacitor includes the second electrode of the fifth transistor.

[0017] In one implementation, at least one of the following is included:

[0018] The pull-down module includes a sixth transistor and an eighth transistor. The gate of the sixth transistor is coupled to the pull-up node, and the first and second terminals of the sixth transistor are coupled to the pull-down node and the second power supply terminal, respectively. The gate of the eighth transistor is coupled to the pull-up node, and the first and second terminals of the eighth transistor are coupled to the control node and the second power supply terminal, respectively.

[0019] The pull-up module includes a first transistor, the gate of which is coupled to the input signal terminal, and the first and second terminals of the first transistor are coupled to the first power supply terminal and the pull-up node, respectively.

[0020] The output module includes a third transistor and a storage capacitor. The gate of the third transistor is coupled to a pull-up node. The first and second terminals of the third transistor are coupled to a clock signal terminal and an output signal terminal, respectively. The first and second terminals of the storage capacitor are coupled to a pull-up node and an output signal terminal, respectively.

[0021] The first reset module includes a second transistor, the gate of which is coupled to a reset signal terminal, and the first and second terminals of the second transistor are coupled to a third power supply terminal and a pull-up node, respectively.

[0022] The reset control module includes a tenth transistor, the gate of which is coupled to a pull-down node, and the first and second terminals of which are coupled to a second power supply terminal and a pull-up node, respectively.

[0023] The second reset module includes an eleventh transistor, the gate of which is coupled to a pull-down node, and the first and second terminals of which are coupled to a second power supply terminal and an output signal terminal, respectively.

[0024] In one embodiment, a frame reset module is further included. The frame reset module is coupled to the second control power supply terminal, the second power supply terminal, the pull-up node, and the output signal terminal, respectively, and is configured to provide the second power supply terminal signal to the pull-up node and the output signal terminal under the control of the second control power supply terminal.

[0025] In one embodiment, the frame reset module includes a fourth transistor and a seventh transistor. The gate of the fourth transistor is coupled to a second control power supply terminal, and the first and second terminals of the fourth transistor are coupled to the second power supply terminal and a pull-up node, respectively. The gate of the seventh transistor is coupled to the second control power supply terminal, and the first and second terminals of the seventh transistor are coupled to the second power supply terminal and an output signal terminal, respectively.

[0026] As a second aspect of the present disclosure, the present disclosure provides a gate driving circuit, including the shift register in any embodiment of the present disclosure.

[0027] As a third aspect of the present disclosure, the present disclosure provides an array substrate including a display area and a border area located outside the display area, and also includes a shift register as described in any embodiment of the present disclosure, the shift register being located in the border area.

[0028] In one embodiment, the array substrate includes:

[0029] Substrate;

[0030] The first metal layer, located on one side of the substrate, includes the gate of the fifth transistor;

[0031] The first insulating layer is located on the side of the first metal layer that is away from the substrate;

[0032] The second metal layer, located on the side of the first insulating layer away from the substrate, includes a first electrode and a second electrode of the fifth transistor. The second electrode of the fifth transistor includes an annular metal trace with an opening. The first electrode of the fifth transistor includes a first metal trace and a second metal trace. The first metal trace is located inside the annular metal trace. The second metal trace is connected to the first metal trace and extends from the opening to the outside of the annular metal trace.

[0033] In one embodiment, the ring-shaped metal trace is a rectangular ring-shaped metal trace, with an opening located on one rectangular side of the rectangular ring-shaped metal trace.

[0034] In one embodiment, the array substrate includes:

[0035] Substrate;

[0036] The first metal layer, located on one side of the substrate, includes the gate of the fifth transistor. The gate of the fifth transistor includes a third metal trace and a fourth metal trace. One end of the fourth metal trace is connected to one end of the third metal trace, and the fourth metal trace is not parallel to the third metal trace.

[0037] The first insulating layer is located on the side of the first metal layer that is away from the substrate;

[0038] The second metal layer, located on the side of the first insulating layer away from the substrate, includes the first and second electrodes of the fifth transistor. The second electrode of the fifth transistor includes a fifth metal trace and a sixth metal trace. One end of the sixth metal trace is connected to the fifth metal trace. The sixth metal trace is not parallel to the fifth metal trace. The first electrode of the fifth transistor includes a seventh metal trace. The seventh metal trace is parallel to the fifth metal trace. The orthogonal projections of the fifth, sixth, and seventh metal traces on the substrate are all located within the orthogonal projection of the third metal trace on the substrate.

[0039] In one embodiment, the device further includes a second insulating layer and an electrode pattern. The second insulating layer is located on the side of the second metal layer away from the substrate, and the electrode pattern is located on the side of the second insulating layer away from the substrate. The second electrode of the fifth transistor is provided with a via. The electrode pattern passes through the second insulating layer and the first insulating layer and passes through the via to connect to the gate of the fifth transistor. The electrode pattern and the orthogonal projection of the second electrode of the fifth transistor on the substrate have an overlapping area. The first electrode of the bootstrap capacitor also includes an electrode pattern.

[0040] As a fourth aspect of the present disclosure, the present disclosure provides a display device including the array substrate described in the present disclosure.

[0041] The technical solutions of the embodiments disclosed herein optimize the noise reduction effect, improve the reliability of display products and the flicker problem, and enhance the lifespan of shift registers and product competitiveness.

[0042] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0043] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0044] Figure 1 This is a schematic diagram of the structure of a shift register in related technologies;

[0045] Figure 2 for Figure 1 A schematic diagram of the signal for shift register reliability testing;

[0046] Figure 3 This is a schematic diagram of the structure of a shift register in one embodiment of the present disclosure;

[0047] Figure 4 This is a schematic diagram of the shift register structure in another embodiment of the present disclosure;

[0048] Figure 5 for Figure 4 The timing diagram of the shift register shown is for one frame.

[0049] Figure 6 This is a schematic diagram of the shift register structure in another embodiment of the present disclosure;

[0050] Figure 7 This is a schematic diagram of a gate drive circuit in one embodiment of the present disclosure;

[0051] Figure 8 This is a planar schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0052] Figure 9A for Figure 8 An enlarged schematic diagram of part A in one embodiment of the array substrate shown;

[0053] Figure 9B for Figure 9A A schematic diagram of the structure of the first metal layer in the middle;

[0054] Figure 10A for Figure 9A An enlarged schematic diagram of the fifth transistor in the image;

[0055] Figure 10B for Figure 10A Schematic diagram of the BB section in the diagram;

[0056] Figure 11 This is an enlarged schematic diagram of the fifth transistor in another embodiment of this disclosure;

[0057] Figure 12A for Figure 8An enlarged schematic diagram of part A in one embodiment of the array substrate shown;

[0058] Figure 12B for Figure 12A A schematic diagram of the structure of the first metal layer in the middle;

[0059] Figure 13A for Figure 12A An enlarged schematic diagram of the fifth transistor in the image;

[0060] Figure 13B for Figure 13A Schematic diagram of the CC section in the diagram;

[0061] Figure 14A This is an enlarged schematic diagram of the fifth transistor in another embodiment of this disclosure;

[0062] Figure 14B for Figure 14A A schematic diagram of the DD section.

[0063] Explanation of reference numerals in the attached figures:

[0064] 11. Pull-up module; 12. Pull-down module; 13. Noise reduction module; 14. Bootstrap module; 15. Output module; 16. First reset module; 17. Reset control module; 18. Second reset module; 19. Frame reset module. Detailed Implementation

[0065] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0066] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the gate (also called the gate electrode), the signal input terminal as the source, and the signal output terminal as the drain. The switching transistors used in these embodiments can be P-type or N-type switching transistors. P-type switching transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal and do not imply that the first potential or the second potential has a specific numerical value throughout the text. In this embodiment of the invention, the first potential is used as an example for illustration.

[0067] The coupling can include direct physical contact between the two ends or indirect connection between the two ends (such as establishing a connection between the two ends through a signal line). This embodiment of the invention does not limit the coupling method between the two ends.

[0068] Figure 1 This is a schematic diagram of a shift register in related technologies. The shift register uses an 11T1C structure. In narrow-bezel, high-frequency display products, the dimensions of the first transistor M1 and the third transistor M3 must be prioritized. Due to limited bezel wiring space, the fifth transistor M5 and the ninth transistor M9 are smaller in size due to insufficient wiring space, causing the pull-down node PD to take a longer time to rise to the normal high level, resulting in poor noise reduction performance.

[0069] Figure 2 for Figure 1 A schematic diagram of the signal for shift register reliability testing. (Example) Figure 2 As shown, before the reliability test, after the pull-up node PU is reset to a low level, the pull-down node PD can smoothly rise to a normal high level. After a long period of reliability testing, due to transistor characteristic drift and product characteristics, the potential of the pull-down node PD experiences a sudden drop during the rise process, causing the pull-up node to rise, resulting in a weakened noise reduction effect and causing the display product to exhibit a reliability flickering problem.

[0070] Figure 3 This is a schematic diagram of the structure of a shift register according to one embodiment of the present disclosure. In one embodiment, such as... Figure 3As shown, the shift register includes a pull-up module 11, a pull-down module 12, a noise reduction module 13, a bootstrap module 14, an output module 15, a first reset module 16, a reset control module 17, and a second reset module 18.

[0071] In one embodiment, such as Figure 3 As shown, the pull-up module 11 is coupled to the input signal terminal INPUT, the first power supply terminal VDD, and the pull-up node PU, respectively, and is configured to provide the first power supply terminal VDD signal to the pull-up node PU under the control of the input signal terminal INPUT.

[0072] In one embodiment, such as Figure 3 As shown, the pull-down module 12 is coupled to the second power supply terminal VGL, the pull-up node PU, the pull-down node PD, and the control node PD_CN, respectively, and is configured to provide the signal of the second power supply terminal VGL to the pull-up node PD and the control node PD_CN under the control of the pull-up node PU.

[0073] In one embodiment, such as Figure 3 As shown, the noise reduction module 13 is coupled to the first control power terminal GCH, the control node PD_CN and the pull-down node PD, respectively. It is configured to provide the signal of the first control power terminal GCH to the control node PD_CN under the control of the first control power terminal GCH, and to provide the signal of the first control power terminal GCH to the pull-down node PD under the control of the control node PD_CN.

[0074] In one embodiment, such as Figure 3 As shown, the bootstrap module 14 is coupled to the control node PD_CN and the pull-down node PD, respectively.

[0075] In one embodiment, such as Figure 3 As shown, the output module 15 is coupled to the clock signal terminal CLK, the pull-up node PU, and the output signal terminal OUTPUT, respectively, and is configured to provide the clock signal terminal CLK to the output signal terminal OUTPUT under the control of the pull-up node PU.

[0076] In one embodiment, such as Figure 3 As shown, the first reset module 16 is coupled to the reset signal terminal RST, the third power supply terminal VSS, and the pull-up node PU, and is configured to provide the signal of the third power supply terminal VSS to the pull-up node PU under the control of the reset signal terminal RST.

[0077] In one embodiment, such as Figure 3 As shown, the reset control module 17 is coupled to the pull-down node PD, the second power supply terminal VGL, and the pull-up node PU, and is configured to provide the signal of the second power supply terminal VGL to the pull-up node PU under the control of the pull-down node PD.

[0078] In one embodiment, such as Figure 3 As shown, the second reset module 18 is coupled to the pull-down node PD, the second power supply terminal VGL, and the output signal terminal OUTPUT, respectively, and is configured to provide the signal of the second power supply terminal VGL to the output signal terminal OUTPUT under the control of the pull-down node PD.

[0079] In this embodiment, under the control of the reset signal terminal RST, the first reset module 16 provides the third power terminal VSS signal to the pull-up node PU, thereby resetting the pull-up node PU. The noise reduction module 13, under the control of the first control power terminal GCH, provides the first control power terminal GCH signal to the control node PD_CN, and under the control of the control node PD_CN, provides the first control power terminal GCH signal to the pull-down node PD. Therefore, during the potential rise of the pull-down node PD, the potential rise of the control node PD_CN takes precedence over the potential rise of the pull-down node PD. Under the bootstrap action of the bootstrap module 14, the higher potential of the control node PD_CN causes the potential of the pull-down node PD to rise rapidly, increasing the rise speed of the pull-down node PD potential and allowing the pull-down node PD to quickly rise to the normal high level, avoiding a potential drop point in the pull-down node PD during the rise process after the reliability test. Therefore, under the control of the high-level signal of the pull-down node PD, the reset control module 17 provides the second power supply terminal VGL signal to the pull-up node PU, avoiding the potential rise phenomenon of the pull-up node PU, optimizing the noise reduction effect, improving the reliability of the display product and the flicker problem, and improving the life of the shift register and the product competitiveness.

[0080] The shift register of this embodiment is located in the border area of ​​the array substrate when applied in the array substrate. The shift register of this embodiment optimizes noise reduction, eliminates the need for dual pull-down nodes (PDs), saves wiring space, and facilitates the achievement of narrow bezels in display products.

[0081] In one implementation, the first power supply terminal VDD is a high-level signal. The second power supply terminal VGL can be a low-level signal. The third power supply terminal VSS can be a low-level signal. The first control power supply terminal GCH can be a high-level signal.

[0082] It should be noted that although the first power supply terminal VDD and the first control power supply terminal GCH are both high-level signals, this does not mean that the voltage of the first power supply terminal VDD is the same as the voltage of the first control power supply terminal GCH. The voltage of the first power supply terminal VDD and the voltage of the first control power supply terminal GCH can be the same or different, and the specific voltage values ​​of the first power supply terminal VDD and the first control power supply terminal GCH can be set as needed. Similarly, although the second power supply terminal VGL and the third power supply terminal VSS are both low-level signals, this does not mean that the voltage of the second power supply terminal VGL is the same as the voltage of the third power supply terminal VSS. The voltage of the second power supply terminal VGL and the voltage of the third power supply terminal VSS can be the same or different, and the specific voltage values ​​of the second power supply terminal VGL and the third power supply terminal VSS can be set as needed.

[0083] In one implementation, such as Figure 3 As shown, the bootstrap module 14 may include a bootstrap capacitor C2. The first and second plates of the bootstrap capacitor C2 can be coupled to the control node PD_CN and the pull-down node PD, respectively. This bootstrap module 14 has a simple structure. It is understood that the structure of the bootstrap module 14 is not limited to the bootstrap capacitor C2; other circuits with bootstrap functionality can also be used. The capacitance value of the bootstrap capacitor C2 can be set according to actual needs and is not specifically limited here.

[0084] Figure 4 This is a schematic diagram of the structure of a shift register according to another embodiment of this disclosure. In one embodiment, such as... Figure 4 As shown, the noise reduction module 13 may include a fifth transistor M5 and a ninth transistor M9. The gate of the ninth transistor M9 is coupled to the first control power supply terminal GCH, and the first and second terminals of the ninth transistor M9 can be coupled to the first control power supply terminal GCH and the control node PD_CN, respectively. Therefore, when the first control power supply terminal GCH is active, the ninth transistor M9 can provide the signal of the first control power supply terminal GCH to the control node PD_CN under the control of the active level of the first control power supply terminal GCH. The gate of the fifth transistor M5 is coupled to the control node PD_CN, the first terminal of the fifth transistor M5 is coupled to the first control power supply terminal GCH, and the second terminal of the fifth transistor M5 is coupled to the pull-down node PD. When the signal of the control node PD_CN is active, the fifth transistor M5 can provide the signal of the first control power supply terminal GCH to the pull-down node PD under the control of the active level of the control node PD_CN.

[0085] For example, the fifth transistor M5 and the ninth transistor M9 can be of the same type. For instance, both the fifth transistor M5 and the ninth transistor M9 can be NMOS.

[0086] It should be noted that, Figure 4 The circuit structure of the noise reduction module 13 is illustrated by way of example, but the noise reduction module 13 is not limited to this. Figure 4 The noise reduction module 13 can be any other circuit, as long as it can achieve the function of the noise reduction module 13.

[0087] In one embodiment, the first plate of the bootstrap capacitor C2 may include the gate of the fifth transistor M5, and the second plate of the bootstrap capacitor C2 may include the second electrode of the fifth transistor M5. For example, the first plate of the bootstrap capacitor C2 can be the gate of the fifth transistor M5, and the second plate of the bootstrap capacitor C2 can be the second electrode of the fifth transistor M5. This arrangement allows the capacitance formed between the gate and the second electrode of the fifth transistor M5 to be used as the bootstrap capacitor C2, eliminating the need for a separate plate, reducing component placement, and simplifying wiring. The capacitance value of the bootstrap capacitor C2 can be set by configuring the shape and size of the gate and the second electrode of the fifth transistor M5.

[0088] In one implementation, such as Figure 4 As shown, the pull-down module 12 may include a sixth transistor M6 and an eighth transistor M8. The gate of the sixth transistor M6 is coupled to the pull-up node PU, and the first and second terminals of the sixth transistor M6 are coupled to the pull-down node PD and the second power supply terminal VGL, respectively. The gate of the eighth transistor M8 is coupled to the pull-up node PU, and the first and second terminals of the eighth transistor M8 are coupled to the control node PD_CN and the second power supply terminal VGL, respectively. Therefore, when the pull-up node PU is an active level signal, the sixth transistor M6, under the control of the active level signal of the pull-up node PU, provides the second power supply terminal VGL signal to the pull-down node PD, pulling down the pull-down node PD; the eighth transistor M8, under the control of the active level signal of the pull-up node PU, provides the second power supply terminal VGL signal to the control node PD_CN, pulling down the control node PD_CN.

[0089] For example, the sixth transistor M6 and the eighth transistor M8 can be of the same type. For instance, both the sixth transistor M6 and the eighth transistor M8 can be NMOS.

[0090] In one implementation, such as Figure 4 As shown, the pull-up module 11 includes a first transistor M1. The gate of the first transistor M1 is coupled to the input signal terminal INPUT, and the first and second terminals of the first transistor M1 are coupled to the first power supply terminal VDD and the pull-up node PU, respectively. Therefore, when the input signal terminal INPUT is at a valid level, the first transistor M1, under the control of the valid level signal of the input signal terminal INPUT, provides the signal of the first power supply terminal VDD to the pull-up node PU, thus pulling up the pull-up node PU.

[0091] In one implementation, such as Figure 4 As shown, the output module 15 includes a first transistor M3 and a storage capacitor. The gate of the first transistor M3 is coupled to the pull-up node PU, and the first and second terminals of the first transistor M3 are coupled to the clock signal terminal CLK and the output signal terminal OUTPUT, respectively. The first and second terminals of the storage capacitor are coupled to the pull-up node PU and the output signal terminal OUTPUT, respectively. Therefore, when the pull-up node PU is an active level signal, the first transistor M3, under the control of the active level signal of the pull-up node PU, provides the clock signal terminal CLK to the output signal terminal OUTPUT, causing the output signal terminal OUTPUT to output a gate drive signal.

[0092] In one implementation, such as Figure 4 As shown, the first reset module 16 includes a first transistor M2. The gate of the first transistor M2 is coupled to the reset signal terminal RST, and the first and second terminals of the first transistor M2 are coupled to the third power supply terminal VSS and the pull-up node PU, respectively. Therefore, when the reset signal terminal RST is active, the first transistor M2, under the control of the active level of the reset signal terminal RST, provides the signal of the third power supply terminal VSS to the pull-up node PU, thereby resetting the pull-up node PU.

[0093] In one implementation, such as Figure 4 As shown, the reset control module 17 includes a tenth transistor M10. The gate of the tenth transistor M10 is coupled to the pull-down node PD, and the first and second terminals of the tenth transistor M10 are coupled to the second power supply terminal VGL and the pull-up node PU, respectively. Therefore, when the pull-down node PD is an active level signal, the tenth transistor M10, under the control of the active level signal of the pull-down node PD, provides the signal of the second power supply terminal VGL to the pull-up node PU, so that the pull-up node PU maintains the reset state.

[0094] In one implementation, such as Figure 4 As shown, the second reset module 18 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is coupled to the pull-down node PD, and the first and second terminals of the eleventh transistor M11 are coupled to the second power supply terminal VGL and the output signal terminal OUTPUT, respectively. Therefore, when the pull-down node PD is an active level signal, the eleventh transistor M11, under the control of the active level signal of the pull-down node PD, provides the signal of the second power supply terminal VGL to the output signal terminal OUTPUT, thereby resetting the output signal terminal OUTPUT and causing the output signal terminal OUTPUT to output a gateless drive signal.

[0095] Figure 4The circuit structure of pull-down module 12, pull-up module 11, output module 15, first reset module 16, reset control module 17, and second reset module 18 is illustrated by way of example. It should be understood that pull-down module 12, pull-up module 11, output module 15, first reset module 16, reset control module 17, and second reset module 18 are not limited to... Figure 4 The circuit structure shown can be replaced with other circuit structures, as long as they can achieve the desired function.

[0096] For example, Figure 4 All transistors in the shift register shown are NMOS transistors. When all transistors in the shift register are NMOS transistors, the effective level signal of each transistor is a high level signal.

[0097] It should be noted that, in actual use, the type of each transistor in the shift register of this embodiment is not limited. Each transistor can be configured as an NMOS or PMOS transistor as needed, and the signals of the input signal terminal INPUT, the first power supply terminal VDD, the second power supply terminal VGL, the third power supply terminal VSS, and the second control power supply terminal GCL can be configured accordingly. When the transistors in the shift register are PMOS transistors, the effective level signal of each transistor is a low-level signal.

[0098] Figure 5 for Figure 4 The diagram shows the timing of the shift register within one frame. The following section combines this with... Figure 4 and Figure 5 The working principle of the shift register in the embodiments of this disclosure is explained in detail. The first power supply terminal VDD is a high-level signal, the second power supply terminal VGL is a low-level signal, the third power supply terminal VSS is a low-level signal, and the first control power supply terminal GCH is a high-level signal.

[0099] During the pull-up phase, when the input signal terminal INPUT is at a valid level (e.g., a high level signal), the first transistor M1 is turned on, providing the first power supply terminal VDD signal to the pull-up node PU, thus pulling the pull-up node PU up. The pull-up phase can be divided into two sub-phases: the first sub-phase and the second sub-phase.

[0100] In the first sub-stage, the first power supply terminal VDD is provided to the pull-up node PU, pulling PU up. The first control power supply terminal GCH is high, turning on the ninth transistor M9 and providing a high-level signal to the control node PD_CN; the fifth transistor M5 turns on, providing a high-level signal to the pull-down node PD. Under the control of the high-level signal from the pull-down node PD, the tenth transistor M10 turns on, providing a low-level signal to the second power supply terminal VGL of the pull-up node PU. Under the control of the high-level signal from the pull-down node PD, the eleventh transistor M11 turns on, providing a low-level signal to the output signal terminal OUTPUT. Therefore, in the first sub-stage, the output signal terminal OUTPUT has no gate signal output.

[0101] In the first sub-stage, a high-level signal (VDD) is provided to the pull-up node PU via the first transistor M1 to charge the pull-up node PU; a low-level signal (VGL) is provided to the pull-up node PU via the tenth transistor M10 to discharge the pull-up node PU. Because the size of the first transistor M1 is larger than that of the tenth transistor M10, the charging speed of the pull-up node PU is greater than the discharging speed, causing the potential of the pull-up node PU to rise slowly. When the pull-up node PU is charged to the effective level signal, the shift register enters the second sub-stage.

[0102] In the second sub-stage, the pull-up node PU is at a valid level, and the sixth transistor M6 and the eighth transistor M8 are turned on, causing the pull-down node PD and the control node PD_CN to discharge. The first control power supply terminal GCH is at a high level, charging the control node PD_CN through the ninth transistor M9 and charging the pull-down node PD through the fifth transistor M5. Since the size of the sixth transistor M6 is larger than that of the fifth transistor M5, and the size of the eighth transistor M8 is larger than that of the ninth transistor M9, the discharge speed of the pull-down node PD is greater than the charging speed of the pull-down node PD, and the discharge speed of the control node PD_CN is greater than the charging speed of the control node PD_CN. Therefore, both the pull-down node PD and the control node PD_CN are pulled low to the potential of the second power supply terminal VGL. The tenth transistor M10 and the eleventh transistor M11 are turned off, and the pull-up node PU maintains a high level signal. Under the control of the valid level signal of the pull-up node PU, the first transistor M3 is turned on, providing the clock signal CLK to the output signal terminal OUTPUT. At this time, the clock signal terminal CLK is at a high level, causing the output signal terminal OUTPUT to output a high level signal.

[0103] During the reset phase, also known as the noise reduction phase, the reset signal terminal RST is at a valid level (e.g., a high level signal). The first transistor M2 is turned on, providing a low-level signal from the third power supply terminal VSS to the pull-up node PU, thus resetting the pull-up node PU to a low level. The sixth transistor M6 and the eighth transistor M8 are turned off. The first control power supply terminal GCH charges the control node PD_CN through the ninth transistor M9, and the first control power supply terminal GCH charges the pull-down node PD through the fifth transistor M5. During the potential rise of the pull-down node PD, the potential rise of the control node PD_CN takes precedence over that of the pull-down node PD. Under the bootstrap action of the bootstrap module 14, the higher potential of the control node PD_CN will cause the potential of the pull-down node PD to rise rapidly, increasing the rise speed of the pull-down node PD potential and enabling the pull-down node PD to rise quickly to the normal high level, thus avoiding a potential drop point in the pull-down node PD during the rise process after the reliability test. Therefore, under the control of the high-level signal of the pull-down node PD, the tenth transistor M10 provides the signal of the second power supply terminal VGL to the pull-up node PU, so that the pull-up node PU is kept at a low level, avoiding the potential rise phenomenon of the pull-up node PU, optimizing the noise reduction effect, improving the reliability of display products and the flicker problem, and improving the life of shift register and product competitiveness.

[0104] During the reset phase, the eleventh transistor M11 is turned on, providing a low-level signal to the second power supply terminal VGL at the output signal terminal OUTPUT, causing the output signal terminal OUTPUT to output a low-level signal and no drive signal to be output.

[0105] Figure 6 This is a schematic diagram of the structure of a shift register according to another embodiment of this disclosure. In one embodiment, such as... Figure 6 As shown, the shift register may further include a frame reset module 19. The frame reset module 19 is coupled to the second control power supply terminal GCL, the second power supply terminal VGL, the pull-up node PU, and the output signal terminal OUTPUT. The frame reset module 19 is configured to provide the signal from the second power supply terminal VGL to the pull-up node PU and the output signal terminal OUTPUT under the control of the second control power supply terminal GCL.

[0106] In one embodiment, the frame reset module 19 includes a fourth transistor M4 and a seventh transistor M7. The gate of the fourth transistor M4 is coupled to the second control power supply terminal GCL, and the first and second terminals of the fourth transistor M4 are coupled to the second power supply terminal VGL and the pull-up node PU, respectively. The gate of the seventh transistor M7 is coupled to the second control power supply terminal GCL, and the first and second terminals of the seventh transistor M7 are coupled to the second power supply terminal VGL and the output signal terminal OUTPUT, respectively. When the second control power supply terminal GCL is active, the fourth transistor M4 is turned on, providing the signal of the second power supply terminal VGL to the pull-up node PU; the seventh transistor M7 is turned on, providing the signal of the second power supply terminal VGL to the output signal terminal OUTPUT.

[0107] It should be noted that, Figure 6 An exemplary structure of the frame reset module 19 is shown in the figure. Those skilled in the art will understand that the frame reset module 19 is not limited to... Figure 6 The structure shown is acceptable as long as it can fulfill its function.

[0108] For example, during the display phase of a single frame, the second control power supply terminal GCL provides an invalid level signal. During the blank phase between two adjacent frames, the second control power supply terminal GCL provides an active level signal. For instance, during the display phase of the Nth frame, the second control power supply terminal GCL provides an invalid level signal, and both the fourth transistor M4 and the seventh transistor M7 are turned off. After the Nth frame and before the N+1th frame, the second control power supply terminal GCL provides an active level signal, and both the fourth transistor M4 and the seventh transistor M7 are turned on, providing the second power supply terminal VGL signal to the pull-up node PU and the output signal terminal OUTPUT. This resets the shift registers in the gate drive circuit, i.e., resets the frame image, preventing any impact on the next frame.

[0109] Figure 7 This is a schematic diagram of a gate driving circuit according to one embodiment of the present disclosure. The present disclosure also provides a gate driving circuit, such as... Figure 7 As shown, the gate driving circuit includes a shift register as described in any embodiment of this disclosure. Exemplarily, the gate driving circuit includes n-stage shift registers. The input signal terminal INPUT of the first-stage shift register is coupled to the trigger signal terminal STV, the input signal terminal INPUT of the i-th-stage shift register is coupled to the output signal terminal OUTPUT of the (i-1)-th-stage shift register, and the reset signal terminal RST of the i-th-stage shift register is coupled to the output signal terminal OUTPUT of the (i+1)-th-stage shift register.

[0110] Figure 8This is a planar schematic diagram of an array substrate according to one embodiment of the present disclosure. The present disclosure also provides an array substrate, which includes a display area 100 and a border area 200 located outside the display area 100, and further includes a shift register as described in any embodiment of the present disclosure, located in the border area 200.

[0111] Figure 9A for Figure 8 The diagram shows an enlarged view of portion A of the array substrate in one embodiment. Figure 9B for Figure 9A A schematic diagram of the structure of the first metal layer in the middle; Figure 10A for Figure 9A An enlarged schematic diagram of the fifth transistor in the image. Figure 10B for Figure 10A A schematic diagram of the BB section. Figure 9A The fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 in the shift register are shown. Figure 9A , Figure 9B and Figure 10A , Figure 10B As shown, the array substrate includes a substrate 31, a first metal layer, a first insulating layer 32, and a second metal layer. The first metal layer is located on one side of the substrate, and the first insulating layer 32 is located on the side of the first metal layer opposite to the substrate 31. The first metal layer includes the gate 50 of a fifth transistor M5, the gate 60 of a sixth transistor M6, the gate 80 of an eighth transistor M8, and the gate 90 of a ninth transistor M9. The gate 60 of the sixth transistor M6 and the gate 80 of the eighth transistor M8 are coupled together. The gate 50 of the fifth transistor M5 and the gate 60 of the sixth transistor M6 are located on opposite sides of the gate 80 of the eighth transistor M8. The gate 90 of the ninth transistor M9 is located on the side of the gate 50 of the fifth transistor M5 opposite to the gate 80 of the eighth transistor M8; that is, the gate 90 of the ninth transistor M9 and the gate 80 of the eighth transistor M8 are located on opposite sides of the gate 50 of the fifth transistor M5. Therefore, the fifth transistor M5 and the sixth transistor M6 are located on opposite sides of the eighth transistor M8. The ninth transistor M9 is located on the side of the fifth transistor M5 opposite to the eighth transistor M8. That is, the ninth transistor M9 and the eighth transistor M8 are located on opposite sides of the fifth transistor M5. The ninth transistor M9, the fifth transistor M5, the eighth transistor M8, and the sixth transistor M6 are arranged sequentially along a first direction (e.g., the vertical direction), which facilitates the wiring of the display substrate.

[0112] like Figure 10A and Figure 10BAs shown, the second metal layer is located on the side of the first insulating layer 32 facing away from the substrate 31. The second metal layer may include a first electrode 51 and a second electrode 52 of the fifth transistor M5. Exemplarily, one of the first electrode and the second electrode may be the source of the fifth transistor M5, and the other may be the drain of the fifth transistor M5. For example, the first electrode is the source S, and the second electrode is the drain D.

[0113] In one embodiment, the second terminal 52 of the fifth transistor M5 is coupled to the pull-down node PD. The second terminal 52 of the fifth transistor M5 includes a ring-shaped metal trace with an opening, such as... Figure 10A As shown, the first electrode 51 of the fifth transistor M5 includes a first metal trace 511 and a second metal trace 512. The first metal trace 511 is located inside the annular metal trace, and the second metal trace 512 is connected to the first metal trace 511, extending from the opening to the outside of the annular metal trace.

[0114] For example, the shape of the ring-shaped metal trace can be a rectangular ring, an elliptical ring, or a circular ring, etc. The shape of the ring-shaped metal trace can be set as needed and is not specifically limited here.

[0115] For example, the orthogonal projection of the second electrode 52 of the fifth transistor M5 onto the substrate lies within the orthogonal projection of the gate 50 of the fifth transistor M5 onto the substrate. Thus, the second electrode 52 and the gate 50 of the fifth transistor M5 can respectively form the two plates of the bootstrap capacitor C2, thereby forming the bootstrap capacitor C2.

[0116] Setting the second electrode 52 of the fifth transistor M5 as an open annular metal trace allows the second electrode 52 of the fifth transistor M5 to have a large overlap area with the gate 50 of the fifth transistor M5, which can increase the capacitance value of the bootstrap capacitor C2, thereby obtaining the required capacitance value of the bootstrap capacitor C2.

[0117] Experiments have shown that the fifth transistor uses... Figure 9A After showing the structure and connection relationship, during the noise reduction stage, the rise rate of the PD potential of the pull-down node increased by about 30μs. In the reliability test, there was no flicker for 240 hours, which greatly optimized the noise reduction effect and improved the product's reliability flicker problem.

[0118] In one embodiment, the ring-shaped metal trace is a rectangular ring-shaped metal trace, with an opening located on one rectangular side of the rectangular ring-shaped metal trace.

[0119] like Figure 10A As shown, the ring-shaped metal trace can have an opening. Figure 10A and Figure 10BIn the illustrated embodiment, the second electrode 52 of the fifth transistor M5 can be a rectangular ring-shaped metal trace, with one side of the rectangular ring-shaped metal trace being removed to form an opening. Thus, the second electrode 52 of the fifth transistor M5 is a "U"-shaped metal trace. The first metal trace 511 and the second metal trace 512 can be parallel to each other. One end of the second metal trace 512 can be connected to one end of the first metal trace 511, and the other end of the second metal trace 512 extends from the opening to the outside of the ring-shaped metal trace.

[0120] Figure 11 This is an enlarged schematic diagram of the fifth transistor in another embodiment of this disclosure. Figure 11 As shown, the second electrode 52 of the fifth transistor M5 can be a rectangular ring-shaped metal trace, with an opening on one side of the rectangular ring-shaped metal trace. Thus, the second electrode 52 of the fifth transistor M5 is a "C"-shaped metal trace. The second metal trace 512 and the first metal trace 511 can be perpendicular to each other. One end of the second metal trace 512 can be connected to the middle of the first metal trace 511, and the other end of the second metal trace 512 extends from the opening to the outside of the ring-shaped metal trace.

[0121] Figure 12A for Figure 8 The diagram shows an enlarged view of portion A of the array substrate in one embodiment. Figure 12B for Figure 12A A schematic diagram of the structure of the first metal layer in the middle; Figure 13A for Figure 12A An enlarged schematic diagram of the fifth transistor in the image. Figure 13B for Figure 13A A schematic diagram of the CC section. Figure 12A The fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 in the shift register are shown. Figure 12A and Figure 12B As shown, the gate 60 of the sixth transistor M6 and the gate 80 of the eighth transistor M8 are coupled. The gate 50 of the fifth transistor M5 and the gate 60 of the sixth transistor M6 are located on opposite sides of the gate 80 of the eighth transistor M8. The gate 90 of the ninth transistor M9 is located on the same side of the gate 50 of the fifth transistor M5 and the gate 80 of the eighth transistor M8. Thus, the fifth transistor M5 and the sixth transistor M6 are located on opposite sides of the eighth transistor M8. The ninth transistor M9 is located on the same side of the fifth transistor M5 and the eighth transistor M8. Figure 12A and Figure 12BAs shown, the gate 50 of the fifth transistor M5 can be L-shaped. The gate 50 of the fifth transistor M5 may include a third metal trace 501 and a fourth metal trace 502, one end of the fourth metal trace 502 being connected to one end of the third metal trace 501, and the fourth metal trace and the third metal trace are not parallel. For example, the fourth metal trace 502 may be perpendicular to the third metal trace 501.

[0122] like Figure 13A As shown, the second electrode 52 of the fifth transistor M5 includes a fifth metal trace 521 and a sixth metal trace 522. One end of the sixth metal trace 522 is connected to one end of the fifth metal trace 521, and the sixth metal trace is not parallel to the fifth metal trace. For example, the sixth metal trace 522 may be perpendicular to the fifth metal trace 521. The first electrode 51 of the fifth transistor M5 includes a seventh metal trace, which is parallel to the fifth metal trace 521. The orthogonal projections of the fifth metal trace 521, the sixth metal trace 522, and the seventh metal trace on the substrate all lie within the orthogonal projection of the gate 50 of the fifth transistor M5 on the substrate. Figure 13A The structure shown also allows the second electrode 52 of the fifth transistor M5 and the gate 50 of the fifth transistor M5 to have a large overlap area, which can increase the capacitance value of the bootstrap capacitor C2, thereby obtaining the required capacitance value of the bootstrap capacitor C2.

[0123] Experiments have shown that the fifth transistor uses... Figure 12A After showing the structure and connection relationship, during the noise reduction stage, the PD potential of the pull-down node increases by about 0.8V, and the rise speed of the PD potential of the pull-down node increases by about 2.67μs, which greatly optimizes the noise reduction effect and improves the product's reliability and flickering issues.

[0124] In one embodiment, the array substrate may further include an active layer 53 for the fifth transistor M5, wherein the active layer 53 for the fifth transistor M5 may be located between the second metal layer and the first insulating layer 32, such as... Figure 10B and Figure 13B As shown.

[0125] Figure 14A This is an enlarged schematic diagram of the fifth transistor in another embodiment of this disclosure. Figure 14B for Figure 14A A schematic diagram of the DD section. In one embodiment, such as... Figure 14A and Figure 14B The array substrate may further include a second insulating layer 33 and an electrode pattern 34. The second insulating layer 33 is located on the side of the second metal layer opposite to the substrate 31. The electrode pattern 34 is located on the side of the second insulating layer 33 opposite to the substrate 31.

[0126] like Figure 14A and Figure 14B As shown, the second electrode 52 of the fifth transistor M5 is provided with a via 523. The electrode pattern 34 penetrates the second insulating layer 33 and the first insulating layer 32 and passes through the via 523 to connect with the gate 50 of the fifth transistor M5. The electrode pattern 34 and the orthographic projection of the second electrode 52 of the fifth transistor M5 on the substrate 31 have an overlapping area. Thus, the electrode pattern 34 is connected to the gate 50 of the fifth transistor M5, and the electrode pattern 34 can form part of the first electrode of the bootstrap capacitor C2. That is, the first electrode of the bootstrap capacitor C2 can include the gate 50 of the fifth transistor M5 and the electrode pattern 34. Therefore, the bootstrap capacitor C2 can include a first sub-capacitor C21 and a second sub-capacitor C22. The gate 50 of the fifth transistor M5 and the second electrode 52 of the fifth transistor M5 can form the first sub-capacitor C21, and the electrode pattern 34 and the second electrode 52 of the fifth transistor M5 can form the second sub-capacitor C22. This structure can further increase the capacitance value of the bootstrap capacitor C2, further improve the rise speed of the pull-down node PD in the noise reduction stage, optimize the noise reduction effect, and better improve the reliability flicker problem of display products.

[0127] In one embodiment, the electrode pattern can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0128] In one embodiment, the array substrate may further include a pixel electrode layer located in the display area. The electrode pattern may be disposed on the same layer as the pixel electrode layer. With this structure, the electrode pattern can be formed simultaneously when the pixel electrode layer is formed, simplifying the fabrication process of the array substrate.

[0129] Figure 10B , Figure 13B Figure 14B The fifth transistor M5 shown is a bottom-gate thin-film transistor. It is understood that in other embodiments, the fifth transistor M5 may be a top-gate thin-film transistor.

[0130] It should be noted that, Figure 9A and Figure 12A It is mainly used to express the positional relationship between the gate metal layer and the source / drain metal layers, therefore, Figure 9A and Figure 12A The active layers of each transistor are not shown.

[0131] In one embodiment, the array substrate may further include gate lines located in the display area, and the output signal terminal OUTPUT of the shift register is coupled to the gate lines.

[0132] This disclosure also provides a display device, which may include the array substrate in any embodiment of this disclosure.

[0133] For example, the display device may be a liquid crystal display device.

[0134] In other embodiments, the display device may also be an organic light-emitting diode (OLED) display device, a light-emitting diode (LED) display device, or the like.

[0135] The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0136] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0137] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0138] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0139] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0140] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0141] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, It includes a display area and a border area located outside the display area, and also includes a shift register located in the border area; The shift register includes: a pull-up module, coupled to an input signal terminal, a first power supply terminal, and a pull-up node, configured to provide a signal from the first power supply terminal to the pull-up node under the control of the input signal terminal; a pull-down module, coupled to a second power supply terminal, the pull-up node, the pull-down node, and a control node, configured to provide a signal from the second power supply terminal to the pull-down node and the control node under the control of the pull-up node; and a noise reduction module, coupled to a first control power supply terminal, the control node, and the pull-down node, configured to provide a signal from the second power supply terminal to the control node under the control of the first control power supply terminal. The control node provides the signal from the first control power terminal and, under the control of the control node, provides the signal from the first control power terminal to the pull-down node; a bootstrap module is coupled to both the control node and the pull-down node; an output module is coupled to the clock signal terminal, the pull-up node, and the output signal terminal, and is configured to provide the clock signal terminal to the output signal terminal under the control of the pull-up node; a first reset module is coupled to the reset signal terminal, the third power terminal, and the pull-up node, and is configured to provide the signal from the first control power terminal to the pull-up node under the control of the reset signal terminal. The signal is supplied to the third power supply terminal; a reset control module, coupled to the pull-down node, the second power supply terminal, and the pull-up node respectively, is configured to provide the signal from the second power supply terminal to the pull-up node under the control of the pull-down node; a second reset module, coupled to the pull-down node, the second power supply terminal, and the output signal terminal respectively, is configured to provide the signal from the second power supply terminal to the output signal terminal under the control of the pull-down node; wherein, the noise reduction module includes a fifth transistor and a ninth transistor, the gate of the ninth transistor is coupled to the first control power supply terminal, the first electrode and the second electrode of the ninth transistor are coupled to the first control power supply terminal and the control node respectively, the gate of the fifth transistor is coupled to the control node, the first electrode of the fifth transistor is coupled to the first control power supply terminal, and the second electrode of the fifth transistor is coupled to the pull-down node; the bootstrap module includes a bootstrap capacitor, the first plate and the second plate of the bootstrap capacitor are coupled to the control node and the pull-down node respectively, the first plate of the bootstrap capacitor includes the gate of the fifth transistor, and the second plate of the bootstrap capacitor includes the second electrode of the fifth transistor; The array substrate includes: a substrate; a first metal layer located on one side of the substrate, including the gate of the fifth transistor, the gate of the fifth transistor including a third metal trace and a fourth metal trace, the fourth metal trace being connected to one end of the third metal trace and not parallel to the third metal trace; a first insulating layer located on the side of the first metal layer opposite to the substrate; a second metal layer located on the side of the first insulating layer opposite to the substrate, including a first electrode and a second electrode of the fifth transistor, the second electrode of the fifth transistor including a fifth metal trace and a sixth metal trace, the sixth metal trace being connected to one end of the fifth metal trace and not parallel to the fifth metal trace, the first electrode of the fifth transistor including a seventh metal trace, the seventh metal trace being parallel to the fifth metal trace, and the orthographic projections of the fifth metal trace, the sixth metal trace, and the seventh metal trace on the substrate all falling within the orthographic projection of the third metal trace on the substrate.

2. The array substrate according to claim 1, characterized in that, The array substrate includes: Substrate; A first metal layer, located on one side of the substrate, includes the gate of the fifth transistor; A first insulating layer is located on the side of the first metal layer opposite to the substrate; The second metal layer, located on the side of the first insulating layer away from the substrate, includes the first electrode and the second electrode of the fifth transistor. The second electrode of the fifth transistor includes an annular metal trace with an opening. The first electrode of the fifth transistor includes a first metal trace and a second metal trace. The first metal trace is located inside the annular metal trace. The second metal trace is connected to the first metal trace and extends from the opening to the outside of the annular metal trace.

3. The array substrate according to claim 2, characterized in that, The ring-shaped metal trace is a rectangular ring-shaped metal trace, and the opening is located on one of the rectangular sides of the rectangular ring-shaped metal trace.

4. The array substrate according to claim 2 or 3, characterized in that, It also includes a second insulating layer and an electrode pattern. The second insulating layer is located on the side of the second metal layer opposite to the substrate, and the electrode pattern is located on the side of the second insulating layer opposite to the substrate. The second electrode of the fifth transistor is provided with a via. The electrode pattern passes through the second insulating layer and the first insulating layer and passes through the via to connect to the gate of the fifth transistor. The electrode pattern and the orthographic projection of the second electrode of the fifth transistor on the substrate have an overlapping area. The first electrode of the bootstrap capacitor also includes the electrode pattern.

5. The array substrate according to claim 1, characterized in that, The bootstrap module includes a bootstrap capacitor, the first plate and the second plate of which are respectively coupled to the control node and the pull-down node.

6. The array substrate according to claim 1, characterized in that, The shift register includes at least one of the following: The pull-down module includes a sixth transistor and an eighth transistor. The gate of the sixth transistor is coupled to the pull-up node. The first and second terminals of the sixth transistor are coupled to the pull-down node and the second power supply terminal, respectively. The gate of the eighth transistor is coupled to the pull-up node. The first and second terminals of the eighth transistor are coupled to the control node and the second power supply terminal, respectively. The pull-up module includes a first transistor, the gate of the first transistor is coupled to the input signal terminal, and the first terminal and the second terminal of the first transistor are coupled to the first power supply terminal and the pull-up node, respectively. The output module includes a third transistor and a storage capacitor. The gate of the third transistor is coupled to the pull-up node. The first and second terminals of the third transistor are coupled to the clock signal terminal and the output signal terminal, respectively. The first and second plates of the storage capacitor are coupled to the pull-up node and the output signal terminal, respectively. The first reset module includes a second transistor, the gate of the second transistor is coupled to the reset signal terminal, and the first terminal and the second terminal of the second transistor are coupled to the third power supply terminal and the pull-up node, respectively. The reset control module includes a tenth transistor, the gate of which is coupled to the pull-down node, and the first and second terminals of which are coupled to the second power supply terminal and the pull-up node, respectively. The second reset module includes an eleventh transistor, the gate of which is coupled to the pull-down node, and the first and second terminals of which are coupled to the second power supply terminal and the output signal terminal, respectively.

7. The array substrate according to claim 1, 5, or 6, characterized in that, The shift register further includes a frame reset module, which is coupled to the second control power supply terminal, the second power supply terminal, the pull-up node, and the output signal terminal, and is configured to provide the signal from the second power supply terminal to the pull-up node and the output signal terminal under the control of the second control power supply terminal.

8. The array substrate according to claim 7, characterized in that, The frame reset module includes a fourth transistor and a seventh transistor. The gate of the fourth transistor is coupled to the second control power supply terminal. The first and second terminals of the fourth transistor are coupled to the second power supply terminal and the pull-up node, respectively. The gate of the seventh transistor is coupled to the second control power supply terminal. The first and second terminals of the seventh transistor are coupled to the second power supply terminal and the output signal terminal, respectively.

9. A display device, characterized in that, The array substrate includes any one of claims 1-8.

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