Chip and method of manufacturing and mounting thereof, and printed circuit board blank

Abstract

A chip, a manufacturing and mounting method thereof, and a printed circuit board preform, the chip comprising: a body having opposite first and second sides; a package frame located on the first side of the body and electrically connected with the body, an exposed pattern on the side of the package frame away from the body matching a target pattern, the target pattern comprising pad positions of pads on a target printed circuit board and a layout of an electrical network; wherein the chip comprises a leadless chip, and the target pattern is designed for a leaded chip. Through the scheme, the leadless chip can be compatible with the PCB board designed for the leaded chip, and the versatility of the chip is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a chip, its manufacturing and mounting methods, and printed circuit board preforms. Background Technology

[0002] Currently, there is a type of power distribution chip on the market that includes a high-side switch. This type of power distribution chip integrates control circuitry and power metal-oxide-semiconductor field-effect transistors (MOSFETs) on a single or multiple dies.

[0003] Currently, in mainstream power distribution chip products, power MOSFETs are typically manufactured using a vertical process, while the control circuitry is manufactured using a horizontal process. The product is packaged with leads and thermal pads, specifically using wire bonding, with the thermal pads connected to the highest potential (Vin). Users of power distribution chips manufactured in this manner will design corresponding patterns on the printed circuit board (PCB). For example, the pad positions and electrical networks on the PCB will be set according to the lead positions of the power distribution chip, and the pad positions and electrical networks on the thermal pads will be designed according to the thermal pad positions of the power distribution chip.

[0004] If manufactured directly using BCD (Bipolar-CMOS-DMOS, where Bipolar is a bipolar transistor used for high-precision analog signal processing, CMOS is a complementary metal-oxide-semiconductor used for designing digital control circuits, and DMOS is a double-diffused metal-oxide-semiconductor used for developing power supplies and high-voltage switching devices) technology, a potential mismatch occurs when using a pinned package. This is because the BCD substrate must be grounded, while the heat dissipation pads on existing PCBs are typically connected to the highest potential. This potential mismatch makes power distribution chips manufactured using BCD technology incompatible with existing commercially available PCBs for pin-to-pin (pin-2-pin) packaging. Furthermore, the high wire bonding resistance of the BCD process negatively impacts device performance.

[0005] While flip-chip manufacturing can effectively reduce resistance and overcome the high resistance of BCD technology, flip chips lack pins and heat dissipation pads, thus making them incompatible with existing PCBs for pin-to-pin compatibility. Furthermore, flip chip package sizes are generally similar to the chip itself; they are not typically designed to be larger for pin-to-pin compatible wire bonding or have specially designed electrical connection patterns for compatibility.

[0006] This means that existing leadless chips, such as flip chips, cannot be directly mounted onto PCBs designed for leaded chips. Summary of the Invention

[0007] The technical problem solved by this invention is how to make leadless chips compatible with PCBs designed for chips with leads.

[0008] To address the aforementioned technical problems, embodiments of the present invention provide a chip, comprising: a body having a first side and a second side opposite to each other; a packaging frame located on the first side of the body and electrically connected to the body, wherein an exposed pattern on the side of the packaging frame opposite to the body matches a target pattern, the target pattern including the pad positions of pads on a target printed circuit board and the layout of electrical networks; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0009] Optionally, matching the exposed pattern and the target pattern includes ensuring that there are no electrical network conflicts in the areas where the exposed pattern and the target pattern overlap.

[0010] Optionally, the exposed pattern is part of a matching pattern, which includes the layout of the electrical network on the package frame and the structure of the solder joint connection between the package frame facing the body and the body. The matching pattern is determined according to the target pattern, and the body and the target printed circuit board are electrically connected through the electrical network provided by the matching pattern.

[0011] Optionally, the encapsulation frame is a single-layer structure, and a portion of the matching pattern is exposed on the side of the encapsulation frame opposite to the body to form the exposed pattern.

[0012] Optionally, the encapsulation frame has a multi-layer structure, and the matching pattern includes the layout of the power-on networks on each layer of the frame, wherein the layout of the power-on networks on the outermost frame forms the exposed pattern.

[0013] Optionally, the exposed pattern is substantially consistent with the target pattern.

[0014] Optionally, the pads include pin pads, and the exposed pattern includes a first pattern, the distribution of the first pattern on the package frame corresponding to the pad positions of the pin pads.

[0015] Optionally, the pad includes a heat dissipation pad, and the exposed pattern includes a second pattern that falls within the pad pattern of the heat dissipation pad.

[0016] Optionally, the packaging frame is a multi-layer structure, and the second pattern is determined according to the pad pattern of the heat dissipation pad. The second pattern includes the layout of the power network on the outermost frame of the multi-layer frame.

[0017] Optionally, the packaging frame is a single-layer structure, and the second pattern is a pattern formed by exposing the matching pattern on the side of the packaging frame away from the body. The matching pattern includes the layout of the electrical network on the packaging frame and the structure of the solder joint connection between the side of the packaging frame facing the body and the body. The matching pattern is determined according to the target pattern, and the body and the target PCB are electrically connected through the electrical network provided by the matching pattern.

[0018] Optionally, a solder joint and an electrical network are provided on the first side of the body, and the body is electrically connected to the packaging frame through the solder joint and the electrical network.

[0019] Optionally, the solder joints include multiple input voltage solder joints and multiple output voltage solder joints arranged in an alternating array, and the input voltage solder joints and output voltage solder joints are staggered.

[0020] Optionally, the packaging frame includes a plurality of strip-shaped electrical networks adapted to electrically connect the solder joints and the pads.

[0021] Optionally, the pinless chip may include a flip chip, and / or the chip may include a power distribution chip.

[0022] Optionally, the body includes: a semiconductor substrate having a front side and a back side facing each other, the front side facing a first side of the body and the back side facing a second side of the body; a working device formed on the front side of the semiconductor substrate, and the packaging frame located on the side of the working device away from the semiconductor substrate.

[0023] To address the aforementioned technical problems, embodiments of the present invention also provide a chip manufacturing method, comprising: obtaining a target pattern, wherein the target pattern includes the pad positions of pads and the layout of electrical networks on a target printed circuit board; determining an exposed pattern of a package frame based on the target pattern, such that the exposed pattern matches the target pattern; electrically connecting the package frame to a first side of a body to obtain the chip, wherein the body has opposing first and second sides, and the exposed pattern is located on the side of the package frame opposite to the body; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0024] Optionally, matching the exposed pattern and the target pattern includes ensuring that there are no electrical network conflicts in the areas where the exposed pattern and the target pattern overlap.

[0025] Optionally, determining the exposed pattern of the package frame according to the target pattern to match the exposed pattern with the target pattern includes: determining a matching pattern according to the target pattern, wherein the matching pattern includes the layout of the electrical network on the package frame and the structure of the solder joint connection between the package frame facing the body and the body, the body and the target printed circuit board being electrically connected through the electrical network provided by the matching pattern; and obtaining the exposed pattern based on the matching pattern.

[0026] Optionally, the encapsulation frame is a single-layer structure, and obtaining the exposed pattern based on the matching pattern includes: partially etching the encapsulation frame to remove a portion of the matching pattern on the side of the encapsulation frame opposite to the body, with the remaining portion of the matching pattern adapted to form the exposed pattern.

[0027] Optionally, the encapsulation frame is a multi-layer structure, the matching pattern includes the layout of the power-on networks on each layer of the frame, and obtaining the exposed pattern based on the matching pattern includes: determining the layout of the power-on networks on the outermost layer of the matching pattern as the exposed pattern.

[0028] Optionally, the exposed pattern is substantially consistent with the target pattern.

[0029] Optionally, the pads include pin pads, the exposed pattern includes a first pattern, and determining the exposed pattern of the package frame according to the target pattern includes: determining the distribution of the first pattern on the package frame corresponding to the pad positions of the pin pads.

[0030] Optionally, the pad includes a heat dissipation pad, the exposed pattern includes a second pattern, and determining the exposed pattern of the package frame according to the target pattern includes: determining the second pattern according to the pad pattern of the heat dissipation pad and the number of layers of the package frame, so that the second pattern falls within the pad pattern of the heat dissipation pad.

[0031] Optionally, determining the second pattern based on the pad pattern of the heat dissipation pad and the number of layers of the package frame includes: when the package frame is a multi-layer structure, determining the second pattern based on the pad pattern of the heat dissipation pad, wherein the second pattern includes the layout of the electrical network on the outermost layer of the multi-layer frame; when the package frame is a single-layer structure, determining the matching pattern as the second pattern by half-etching the remaining part of the package frame away from the body, wherein the matching pattern includes the layout of the electrical network on the package frame and the structure of the solder joint connection between the package frame facing the body and the body, the matching pattern is determined based on the target pattern, and the body and the target PCB board are electrically connected through the electrical network provided by the matching pattern.

[0032] Optionally, the step of electrically connecting the packaging frame to a first side of the body to obtain the chip includes: setting solder joints and electrical networks on the first side of the body; and electrically connecting the packaging frame to the first side of the body through the solder joints.

[0033] To address the aforementioned technical problems, embodiments of the present invention also provide a chip mounting method, comprising: acquiring the aforementioned chip; acquiring a target printed circuit board, the target printed circuit board having opposing first and second sides, the first side of the target printed circuit board having the target pattern disposed thereon; disposing a mask layer on the first side of the target printed circuit board, the mask layer having a window pattern to expose a portion of the target pattern, the window pattern matching the exposed pattern; filling an electrical connection material within a window area defined by the window pattern; mounting the chip to the first side of the target printed circuit board, wherein the chip is electrically connected to the target printed circuit board through the electrical connection material; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0034] Optionally, after mounting the chip to the first side of the target printed circuit board, the chip mounting method further includes removing the mask layer.

[0035] Optionally, the step of setting a mask layer on the first side of the target printed circuit board includes: forming a solder resist layer on the first side of the target printed circuit board according to the window pattern using the window pattern as a mask; or, covering the first side of the target printed circuit board with a stencil, wherein the window position and window area on the stencil are determined according to the window pattern.

[0036] To address the aforementioned technical problems, embodiments of the present invention also provide a printed circuit board prefabrication, comprising: a printed circuit board having a first side and a second side opposite to each other, wherein a target pattern is disposed on the first side of the printed circuit board, the target pattern including the pad positions of pads on the printed circuit board and the layout of electrical networks; a mask layer disposed on the first side of the printed circuit board, the mask layer having a window pattern to expose part of the target pattern, the window pattern matching the exposed pattern, the exposed pattern being the layout of electrical networks of a chip's packaging frame exposed to the outside, the exposed pattern matching the target pattern; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0037] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0038] This invention provides a chip, comprising: a body having a first side and a second side opposite to each other; and a packaging frame located on the first side of the body and electrically connected to the body, wherein an exposed pattern on the side of the packaging frame opposite to the body matches a target pattern, the target pattern including the pad positions of pads on a target printed circuit board and the layout of electrical networks; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0039] Compared to existing technologies that require users to manually adjust the electrical connection patterns on the PCB board to match leadless chips, this implementation allows leadless chips to be directly compatible with PCB boards designed for leaded chips, thereby improving chip versatility and reducing the workload on the user side. Specifically, although the chip is in a leadless package, the pattern and electrical network of the exposed portion of the bottom package frame of the packaged chip are specially designed. Furthermore, by matching the exposed pattern of the package frame with the electrical connection pattern on the target PCB board, such as ensuring that the corresponding portion on the package frame remains exposed in areas with pads on the target PCB board, and keeping the corresponding portion on the package frame concealed in areas without pads on the target PCB board, the chip disclosed in this implementation, although packaged using a leadless process, can still be soldered onto the pads of a customer PCB board originally designed for a chip packaged using a leaded process, without electrical network / electrical function conflicts (or mismatches). Such conflicts or mismatches could be, for example, electrical short circuits or disconnected electrical networks.

[0040] Furthermore, the leadless package specifically refers to a packaged chip with no protruding pins. Matching the exposed pattern of the package frame with the electrical connection pattern (i.e., the target pattern) on the PCB board can include ensuring no electrical network conflicts in the overlapping areas of the exposed pattern and the target pattern. For example, at the corresponding positions of pins in a previously leaded package, the chip in this embodiment is designed with an exposed portion of the package frame, the shape of which is similar to the pin, and the electrical network also corresponds to the pin. As another example, at the corresponding positions of heat dissipation pads in a previously leaded package, the chip in this embodiment is also designed to expose the corresponding electrical network of the package frame, maximizing the area of ​​this exposed electrical network. In non-pin and non-heat dissipation pad areas, targeted design of the electrical network layout on the outermost layer of a multi-layer package frame, such as through semi-etching processes or multi-layer package frames, can prevent the package frame from being exposed on the front of the chip in these areas.

[0041] This invention also provides a chip manufacturing method, comprising: obtaining a target pattern, wherein the target pattern includes the pad positions of pads and the layout of electrical networks on a target printed circuit board; determining an exposed pattern of a package frame based on the target pattern, such that the exposed pattern matches the target pattern; electrically connecting the package frame to a first side of a body to obtain the chip, wherein the body has opposing first and second sides, and the exposed pattern is located on the side of the package frame opposite to the body; wherein the chip includes a leadless chip, and the target pattern is designed for a leaded chip.

[0042] Compared to existing technologies that do not consider compatibility with the original PCB board when manufacturing leadless chips using flip-chip processes, this embodiment considers compatibility issues during the chip manufacturing stage and specially designs the package frame and electrical connection patterns on the chip for compatibility considerations. Therefore, the leadless chip prepared using this embodiment is directly compatible with PCB boards designed for leaded chips, significantly improving chip versatility and reducing the workload on the user side. Specifically, for chips using leadless packaging, the exposed patterns of the package frame are matched with the electrical connection patterns on the PCB board. For example, areas with pads on the PCB board ensure that the corresponding parts on the package frame remain exposed, while non-pad areas on the PCB board are protected from exposure on the back of the chip through semi-etching processes or targeted design of the electrical network layout on the outermost frame of a multi-layer package. Thus, although the chip disclosed in this embodiment is packaged using a leadless process, it can still be soldered onto the pads of a customer's PCB board originally designed for chips using a leaded process, without electrical network / functional conflicts / mismatches.

[0043] This invention also provides a chip mounting method, comprising: acquiring the aforementioned chip; acquiring a target printed circuit board, the target printed circuit board having opposing first and second sides, the first side of the target printed circuit board having the target pattern; distributing a mask layer on the first side of the target printed circuit board, the mask layer having a window pattern to expose a portion of the target pattern, the window pattern matching the exposed pattern; filling an electrical connection material within a window area defined by the window pattern; mounting the chip to the first side of the target printed circuit board, wherein the chip is electrically connected to the target printed circuit board through the electrical connection material; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0044] This implementation scheme enables compatible mounting of leadless chips on target PCBs designed for leaded chips with minimal process improvements and high user ease of operation. Specifically, the leadless chip can be reliably mounted onto the target PCB design for leaded chips simply by adjusting the window pattern on the mask layer to match the exposed pattern of the chip.

[0045] This invention also provides a printed circuit board prefabrication, comprising: a printed circuit board having a first side and a second side opposite to each other, wherein a target pattern is disposed on the first side of the printed circuit board, the target pattern including the pad positions of pads and the layout of electrical networks on the printed circuit board; a mask layer disposed on the first side of the printed circuit board, the mask layer having a window pattern to expose part of the target pattern, the window pattern matching the exposed pattern, the exposed pattern being the layout of electrical networks of a chip's packaging frame exposed to the outside, the exposed pattern matching the target pattern; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0046] This implementation pre-fabricates a mask layer on a printed circuit board (PCB) that matches the windowed pattern and the exposed pattern of the leadless chip. Therefore, users can achieve compatible mounting of leadless chips on PCBs designed for leaded chips without significantly adjusting the mounting process when installing the leadless chip onto the PCB pre-fabricated component. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a chip according to the first embodiment of the present invention;

[0048] Figure 2 yes Figure 1 A cross-sectional view along the AA direction;

[0049] Figure 3 yes Figure 1 A cross-sectional view along the BB direction;

[0050] Figure 4 yes Figure 1 A sectional view along the CC direction;

[0051] Figure 5 yes Figure 1 A schematic diagram of the exposed pattern of the chip shown.

[0052] Figure 6 Mounted on the target printed circuit board Figure 1 The diagram shows the window opening of the pads for the chip shown.

[0053] Figure 7 This is a schematic diagram of the inner packaging framework of a chip according to the second embodiment of the present invention;

[0054] Figure 8 yes Figure 7 A schematic diagram of the multi-layer packaging framework of the chip shown.

[0055] Figure 9 yes Figure 8 Cross-sectional view along the DD direction;

[0056] Figure 10 This is a flowchart of a chip manufacturing method according to the third embodiment of the present invention;

[0057] Figure 11 This is a flowchart of a chip mounting method according to the third embodiment of the present invention. Detailed Implementation

[0058] As mentioned in the background section, existing technologies cannot achieve compatibility between pinless chips and pinned chips.

[0059] Specifically, power distribution chips are a type of switching circuit commonly used in manufacturing. These chips typically contain at least one transistor used as a switch to control the on / off state of the load. Based on whether they have diagnostics, power rating, and whether they handle inductive loads, power distribution chips can be further categorized into hot-swappable chips, high-side switching chips, load switches, and so on.

[0060] Taking high-side switching chips as an example, these power distribution chips typically include a control circuit and one or more power MOSFETs. The control circuit provides functions such as control and protection for the power MOSFETs, which are used to carry load current. When the power MOSFET is turned on, the load current flowing through the on-resistance of the power MOSFET generates heat through losses, so high-side switches have high requirements for heat dissipation. Generally, a thermal pad is provided on the bottom of the chip in the package. This thermal pad is soldered to a thermal pad on the user-provided PCB board, thus dissipating heat from the high-side switch to the PCB board.

[0061] Existing high-side switches, whose control circuits include multiple transistors, can be fabricated using BCD technology. The power section consists of one or more MOSFETs. Due to their high voltage withstand capability and large power output, they can be fabricated using lateral (LDMOS) structures or vertical (VDMOS / trench MOS) structures. For vertical structures, since the substrate is N-type (because the lower surface drain of the vertical structure is N-type, the substrate is usually also N-type), it typically needs to be connected to the highest system potential, i.e., Vin. The lower surface of this silicon wafer also serves as the drain of the power MOSFET, and current flows in from the lower surface.

[0062] Considering the potential problems of high wire bonding resistance and large package size when using power distribution chips with pins and heat dissipation pads, more and more manufacturers are choosing to use non-wire bonding methods such as flip-chip technology to package chips.

[0063] However, because flip-chip packages are not typically designed to be larger for pin-to-pin compatible wire bonding, nor are their electrical connection patterns specially designed for compatibility, existing leadless chips packaged using flip-chip technology are incompatible with PCBs originally designed for leaded chips. To ensure the proper use of power distribution chips manufactured using flip-chip technology (hereinafter referred to as flip chips), the current mainstream practice is for users to redesign the electrical connection patterns on their PCBs to accommodate flip chips. This obviously increases the workload on the user side significantly, impacting product promotion and application.

[0064] To address the aforementioned technical problems, embodiments of the present invention provide a chip, comprising: a body having a first side and a second side opposite to each other; a packaging frame located on the first side of the body and electrically connected to the body, wherein an exposed pattern on the side of the packaging frame opposite to the body matches a target pattern, the target pattern including the pad positions of pads on a target printed circuit board and the layout of electrical networks; wherein the chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0065] Therefore, by adopting this embodiment, leadless chips can be directly compatible with PCBs designed for leaded chips, thereby improving chip versatility and reducing the workload on the user side. Specifically, although the chip is in a leadless package, the pattern and electrical network of the exposed portion of the bottom package frame of the packaged chip are specially designed. Furthermore, by matching the exposed pattern of the package frame with the electrical connection pattern on the target PCB, such as ensuring that the corresponding part on the package frame remains exposed in areas with pads on the target PCB, and keeping the corresponding part on the package frame concealed in areas without pads on the target PCB, the chip disclosed in this embodiment, although packaged using a leadless process, can still be soldered onto the pads of a customer PCB designed for a chip originally packaged using a leaded process, without electrical network / electrical function conflicts (or mismatches). Such conflicts or mismatches could be, for example, electrical short circuits or disconnected electrical networks.

[0066] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0067] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in each drawing. The embodiments are merely illustrative, and of course, partial substitutions or combinations can be made to the structures shown in different embodiments. In the variations, descriptions of matters common to the first embodiment are omitted, and only the differences are described. In particular, the same effects produced by the same structure will not be mentioned one by one in each embodiment.

[0068] Figure 1 This is a schematic diagram of a chip 1 according to the first embodiment of the present invention; Figure 2 yes Figure 1 A cross-sectional view along the AA direction; Figure 3 yes Figure 1 A cross-sectional view along the BB direction; Figure 4 yes Figure 1 A sectional view along the CC direction; Figure 5 yes Figure 1 A schematic diagram of the exposed pattern of chip 1 is shown. Wherein, Figure 1 This can be viewed as a perspective view of chip 1, exemplarily showing the internal structure of chip 1 when it is not encapsulated; Figure 5 This is an external view of chip 1, exemplarily illustrating the external structure of chip 1 after molding. Molding can refer to covering the chip 1 with a shell 13 to protect the internal components during processing; the shell 13 can be, for example, a plastic shell.

[0069] This implementation scheme can be applied to leadless chip manufacturing scenarios, such as flip chip manufacturing scenarios, so that flip chips can be directly soldered to PCBs originally designed for leaded chips. In practical applications, this implementation scheme can also be applied to chips with a mix of flip and leaded components.

[0070] The chip 1 described in this embodiment is a leadless package, meaning that no leads protrude after the chip 1 is packaged. Furthermore, compared to chips with leaded packages, chip 1 may not have a heat dissipation pad on its bottom after packaging.

[0071] The chip 1 described in this embodiment can be, for example, a power distribution chip manufactured using a flip-chip process. It should be noted that... Figure 1 and Figure 5 All images show a front view of chip 1. For flip chips, the front view refers to the side of chip 1 that faces and contacts the PCB board when it is mounted on the PCB board (corresponding to the bottom of chip 1 after it is packaged). Figures 2 to 4 The example is shown with the chip 1 facing down, i.e., flipped onto the target PCB board.

[0072] Specifically, refer to Figures 1 to 5 The chip 1 described in this embodiment may include a body 10 and a packaging frame 11. The body 10 is used to implement the digital circuit functions and / or analog circuit functions of the chip 1. The body 10 has a first side 10a and a second side 10b facing each other, wherein the first side 10a of the body 10 faces the front of the chip 1, and the packaging frame 11 is electrically connected to the first side 10a of the body 10.

[0073] Taking a power distribution chip as an example, the body 10 may include a control circuit 101 and a power MOSFET 102, wherein the control circuit 101 is coupled to at least one signal terminal signal, and the power MOSFET 102 is coupled to at least one voltage input terminal Vin and at least one voltage output terminal Vout.

[0074] Furthermore, the body 10 may include: a semiconductor substrate having opposing front and back sides, wherein the front side faces a first side 10a of the body 10 and the back side faces a second side 10b of the body 10; and a working device formed on the front side of the semiconductor substrate. The working device may include the aforementioned control circuit 101 and power MOSFET 102, that is, each working device may be equivalent to a functional module of the chip 1. During manufacturing, the working device can be formed on the front side of the semiconductor substrate to obtain the body 10.

[0075] In a specific implementation, continue to refer to Figures 1 to 5The first side 10a of the body 10 may be provided with solder bumps (hereinafter referred to as solder points) and electrical networks. The body 10 is electrically connected to the package frame 11 through these solder bumps and electrical networks.

[0076] Specifically, the electrical network may include electrical connection channels between solder joints, between solder joints and working devices, and / or between pads, and may also include electrical connection channels arranged on the package frame 11. Through the cooperation of solder joints and the electrical network, electrical connections can be achieved between the leads of the working devices and the pads on the target PCB board.

[0077] In some embodiments, the electrical connection pattern formed by the solder joints and electrical networks disposed on the first side 10a of the body 10 does not need to perfectly match the electrical connection pattern on the target PCB board (as described below). That is, the design of the solder joints and electrical networks on the chip 1 body 10 can be more flexible, as long as it ensures that there is a corresponding electrical path from the working device to the electrical network exposed by the exposed pattern of the package frame 11, and then to the pads or electrical networks on the target PCB board.

[0078] In a specific implementation, continue to refer to Figure 1 The solder joints may include multiple input voltage solder joints and multiple output voltage solder joints arranged in an alternating array. The input voltage solder joints are those that electrically connect the working device to the input voltage terminal Vin, and the output voltage solder joints are those that electrically connect the working device to the output voltage terminal Vout.

[0079] Specifically, alternating array arrangements can be, for example, in Figure 1 From the perspective shown, each row of solder joints is considered a group, and multiple groups of input voltage solder joints and multiple groups of output voltage solder joints are arranged alternately in the vertical direction.

[0080] Furthermore, the input voltage solder points and output voltage solder points on adjacent rows or columns are staggered. That is, vertically, the input voltage solder points and output voltage solder points in adjacent rows are offset and not on the same straight line. However, the input voltage solder points in every other row, as well as the output voltage solder points in every other row, are on the same straight line.

[0081] Therefore, reducing the spacing between solder joints helps to reduce the connection resistance between chip 1 and the target PCB board.

[0082] In practical applications, multiple sets of input voltage solder joints and multiple sets of output voltage solder joints can also be arranged in two or more rows at intervals, and this embodiment does not impose any restrictions on this.

[0083] In a specific implementation, continue to refer to Figures 1 to 5The packaging frame 11 can be located on the side of the working device away from the semiconductor substrate. That is, the packaging frame 11 is positioned facing the front of the chip 1. When the chip 1 is flip-chip bonded to the target PCB board, the packaging frame 11 is located between the body 10 and the target PCB board, so that the working device can be electrically connected to the target PCB board through the packaging frame 11.

[0084] Furthermore, the exposed pattern on the side of the encapsulation frame 11 opposite to the body 10 matches the target pattern.

[0085] Exposed patterns can specifically refer to the patterns formed on the portion of the electrical network of the packaging frame 11 exposed on the surface of the encapsulated chip 1, such as... Figure 5 As shown. The electrical network of the package frame 11 is adapted to electrically connect (also known as electrical connection) solder joints and pads.

[0086] The target pattern may specifically include the pad locations and electrical network layout on the target PCB board. The target printed circuit board refers to the PCB board on which chip 1 needs to be soldered, and the electrical connection layout on the target printed circuit board is designed and manufactured based on a pinned chip with pins (and heat dissipation pads); that is, the target pattern is designed for pinned chips. The material used for the pads may be, for example, copper.

[0087] In some embodiments, the target pattern may include the layout of all pads required for soldering chip 1 on the target PCB and all electrical networks that successfully achieve electrical connections. In some embodiments, the target pattern may only be a portion of the actual layout on the target PCB, such as connecting only a portion of multiple output voltage terminals Vout, while the remaining output voltage terminals Vout are avoided by being open-circuited.

[0088] It should be noted that the layout of the electrical network described in this embodiment is not limited to the result shown on the existing target PCB board, and the layout may be adjusted in the future due to the addition or reduction of related electrical functions.

[0089] In this specific embodiment, by obtaining the target pattern on the target PCB board in advance, the layout of the electrical network exposed on the bottom of the chip 1 by the package frame 11 can be reasonably designed so that the exposed pattern can match the target pattern. Specifically, the matching can include ensuring that there are no conflicts or mismatches in the electrical network (or electrical function) in the overlapping areas of the exposed pattern and the target pattern. For example, matching can include ensuring that there are no electrical short circuits or open circuits in the overlapping areas.

[0090] Furthermore, the area where the exposed pattern and the target pattern overlap can specifically refer to the area where the projection of the exposed pattern on the target PCB board and the target pattern overlap after the chip 1 is installed on the target PCB board, that is, the part where electrical connection will occur in the area where the chip 1 and the target PCB board are in contact.

[0091] Therefore, by adopting this implementation scheme, the leadless chip can be directly compatible with PCB boards designed for leaded chips, thereby improving the versatility of chip 1 and reducing the workload on the user side. Specifically, although chip 1 is a leadless package, the pattern and electrical network of the exposed part of the bottom package frame 11 of the packaged chip 1 are specially designed. By matching the exposed pattern of the package frame 11 with the electrical connection pattern on the target PCB board, such as ensuring that the corresponding part on the package frame 11 remains exposed in areas with pads on the target PCB board, and keeping the corresponding part on the package frame 11 concealed in areas without pads on the target PCB board.

[0092] Therefore, although the chip 1 disclosed in this embodiment is obtained by using a leadless packaging process, it can still be soldered onto the pads of a customer's PCB board that was originally designed to use a chip with a leaded packaging process, without any electrical network / electrical function conflict (or mismatch). Such conflict or mismatch may be, for example, an electrical short circuit or a disconnection of the electrical network.

[0093] Furthermore, the solder joints and electrical networks on the body 10 of chip 1 can also be designed according to the electrical connection pattern on the target PCB board to ensure that the packaging frame 11 can match the target PCB board.

[0094] In a specific implementation, continue to refer to Figures 1 to 5 The exposed pattern may be part of the matching pattern, wherein the matching pattern may include the layout of the power-on network on the package frame 11 and the structure of the solder joint connection between the package frame 11 facing the body 10 and the body 10.

[0095] In other words, the matching pattern may include the exposed pattern on the side of the package frame 11 facing away from the body 10, the electrical network layout in the middle, and the structure of the upper layer (i.e., the side facing the body 10) and the solder joint connection of the chip 1. Thus, the body 10 and the target PCB board achieve electrical connection through the electrical network provided by the matching pattern. Furthermore, the matching pattern can be determined according to the target pattern to ensure a reliable electrical connection between the working device of the chip 1 and the target PCB board.

[0096] For example, for such Figures 1 to 5The single-layer packaging frame 11 shown has a portion of its matching pattern exposed on the side of the packaging frame 11 facing away from the body 10 to form an exposed pattern. Here, "single-layer structure" means that the packaging frame 11 is a single-layer structure, and all electrical networks of the packaging frame 11 are arranged on the same plane; the layout of all electrical networks constitutes the matching pattern. In this example, the electrical network layouts on opposite sides of the single-layer packaging frame 11 can initially be the same (e.g., both are matching patterns). After one side is soldered to the body 10, the opposite side can be partially etched using the exposed pattern as a mask, so that only the portion of the matching pattern on the side of the packaging frame 11 facing away from the body 10 that overlaps with the exposed pattern is ultimately exposed.

[0097] In a specific implementation, continue to refer to Figure 1 The package frame 11 may include multiple strip-shaped electrical networks. For example, a set of input voltage solder points corresponds to one strip-shaped electrical network. Similarly, a set of output voltage solder points corresponds to one strip-shaped electrical network. This reduces the resistance of the package frame 11 soldered according to this matching pattern.

[0098] In a specific implementation, combined with Figure 5 and Figure 6 The pads on the target printed circuit board may include pin pads 121. Figure 6 Mounted on the target printed circuit board Figure 1 The diagram shows the window opening of the pads for chip 1.

[0099] Specifically, the lead pad 121 may be designed for soldering the leads of a chip with leads.

[0100] Furthermore, the exposed pattern of the package frame 11 may include a first pattern, and the distribution of the first pattern on the package frame 11 corresponds to the pad position of the pin pad 121 on the target PCB board.

[0101] In some embodiments, the correspondence may specifically mean that for each port of each working device on the body 10, at least one first pattern is arranged on the package frame 11 to correspond to the pin pad 121 suitable for electrically connecting the port.

[0102] For example, the distribution of the first pattern on the package frame 11 and the pad positions of the pin pads 121 can be in one-to-one correspondence.

[0103] refer to Figure 6The target PCB board can have multiple pin pads 121, which are arranged in two columns on both sides of the chip 1's placement position on the target PCB board. Correspondingly, there can be multiple first patterns, which are also arranged in two columns on both sides of the body 10. Furthermore, each pin pad 121 has a corresponding first pattern. When the chip 1 is mounted to the target PCB board, the pattern of each first pattern and the corresponding pin pad 121 at least partially overlaps. Figure 6 The example shown is based on the premise that each first pattern falls completely within the pad pattern of the corresponding pin pad 121. In actual applications, it is possible that at least one first pattern and the pad pattern of the corresponding pin pad 121 partially overlap.

[0104] For example, when multiple pin pads 121 correspond to the same port, the distribution of the first pattern on the package frame 11 can correspond to the pad position of only one pin pad 121. Alternatively, the area of ​​the first pattern can be large enough to correspond to multiple pin pads 121 simultaneously.

[0105] For example, several unimportant pins may be omitted from the design of matching first patterns. That is, the package frame 11 may not have a first pattern corresponding to the pin pads 121 of these pins.

[0106] Therefore, in the corresponding position of the pin that was originally pinned, the chip 1 of this embodiment is designed with an exposed portion of the package frame 11. The shape of the exposed portion is similar to that of the pin, and the electrical network also corresponds to the pin.

[0107] In practical applications, the first pattern may also include an interference pattern. The distribution of the interference pattern on the package frame 11 corresponds to an unimportant position on the target PCB board, such as a position that will not interfere with the target pattern.

[0108] In a specific implementation, continue to refer to Figure 5 and Figure 6 The pad may include a thermal pad 122, which is specifically designed for soldering a chip with pins.

[0109] Furthermore, the exposed pattern of the package frame 11 may include a second pattern, and the second pattern falls within the pad pattern of the heat dissipation pad 122.

[0110] Furthermore, the distribution of the second pattern on the package frame 11 can correspond to the position of the heat sink 122 on the target PCB board. That is, for each port of each working device on the body 10, the package frame 11 can be arranged with at least one second pattern to correspond to the heat sink 122 suitable for electrically connecting that port.

[0111] In some embodiments, the number of thermal pads 122 can be one, corresponding to all ports on the body 10 that require electrical connection to the thermal pads 122. Correspondingly, the second pattern can be a single pattern falling within the pad pattern of the individual thermal pad 122. Alternatively, the second pattern can include multiple independent patterns, all located within the pad pattern of the individual thermal pad 122, such as the second pattern being honeycomb-shaped.

[0112] For example, a heat dissipation pad 122 can be provided on the target PCB board. A single heat dissipation pad 122 can be located between two rows of pin pads 121, such as typically located directly below the corresponding position of the body 10 on the target PCB board. The area of ​​the heat dissipation pad 122 is typically not less than the area of ​​the body 10 to achieve better heat dissipation. Accordingly, when the chip 1 is mounted to the target PCB board, the portion of the electrical network of the package frame 11 that falls within the pad pattern of the heat dissipation pad 122 is defined as the second pattern.

[0113] Therefore, in the original position of the heat dissipation pad with pin package, the chip 1 in this embodiment is also designed to expose the electrical network corresponding to the package frame 11, and to maximize the area of ​​this exposed electrical network.

[0114] In one specific implementation, in non-pin and non-heat-dissipating pad areas, a process such as half-etch can be used to prevent the package frame 11 from being exposed on the front side of the chip 1 in these areas. Figures 2 to 4 As shown.

[0115] Therefore, by designing the pattern exposed at the bottom of the flip chip packaging frame 11, it is made to be basically consistent with the electrical network at the same position as the pins and / or heat dissipation pads of the leaded product, so as to achieve the effect of compatibility during soldering.

[0116] In a specific implementation, continue to refer to Figures 1 to 5 For a single-layer encapsulation frame 11, the second pattern may be a pattern formed by exposing the matching pattern on the side of the encapsulation frame 11 away from the body 10.

[0117] Specifically, if the pad pattern of the heat sink pad 122 is directly determined as the second pattern, compared to Figure 1 and Figure 5It is understood that this will also include a portion of the electrical connection pattern between the pin pad 121 and the body 10 within the area of ​​the second pattern. Therefore, to avoid electrical short circuits when chip 1 is soldered to the target PCB board, this embodiment, when designing the matching pattern, designs as much of the portion within the pad pattern of the heat sink 122 as possible, excluding the electrical network connecting the pin pad 121 and the body 10, as the electrical network connecting the heat sink 122 and the body 10, and defines this portion of the electrical network as the second pattern. For example, refer to... Figure 1 The second pattern can be in the shape of a comb.

[0118] Therefore, although it is not possible to perfectly match the heat dissipation pad 122, the electrical connection area between the chip 1 and the heat dissipation pad 122 can still be increased as much as possible to ensure the heat dissipation effect.

[0119] Figure 7 This is a schematic diagram of the inner packaging framework of a chip 2 according to the second embodiment of the present invention; Figure 8 yes Figure 7 A schematic diagram of the multi-layer packaging framework of chip 2 is shown; Figure 9 yes Figure 8 Cross-sectional view along the DD direction. This view mainly focuses on chip 2 and the aforementioned... Figures 1 to 5 The differences of the chip 1 in the illustrated embodiment will be explained.

[0120] Specifically, the chip 2 described in this embodiment is the same as the one described above. Figures 1 to 5 The main differences in the chip 1 described in the illustrated embodiment include: the packaging frame 21 has a multi-layer structure, such as a two-layer structure, meaning the electrical network on the packaging frame 21 can be distributed in either layer of the two-layer structure, and the two layers are electrically connected. The layer furthest from the body 10 in the multi-layer packaging frame 21 is referred to as the outermost frame, and the remaining layers in the multi-layer structure are referred to as the inner frames. For example, adjacent frames can be connected by electroplating or placing copper, using technologies such as vias. Figure 7 This shows a front view of chip 2 after the outermost frame has been removed. Figure 8 A schematic diagram of the electrical connections of the two-layer structure of the encapsulation frame 21 in the second pattern is shown.

[0121] In one specific implementation, the chip 2 described in this embodiment is similar to the one described above. Figures 1 to 5 The differences in the chip 1 described in the illustrated embodiment may also include: for the multi-layer packaging frame 21, the matching pattern may include the layout of the power-on network on each layer of the frame, wherein the layout of the power-on network on the outermost frame forms an exposed pattern.

[0122] Specifically, the exposed patterns formed on the outermost frame may include a first pattern corresponding to the pin pad 121 and a second pattern corresponding to the heat dissipation pad 122.

[0123] Furthermore, the layout of the electrical network on the inner frame is adapted to ensure that the electrical network layouts corresponding to the body 10 and the exposed pattern have corresponding electrical paths.

[0124] Furthermore, the second pattern can be determined based on the pad pattern of the heat dissipation pad 122.

[0125] In some embodiments, the distribution of the second pattern on the outermost frame of the package frame 21 can perfectly match the pad pattern of the heat dissipation pad 122.

[0126] In other words, the area of ​​the exposed pattern and its position on chip 1 are basically consistent with the area of ​​the heat dissipation pad 122 and its position on the target PCB board.

[0127] In some embodiments, the distribution of the second pattern on the outermost frame of the package frame 21 can match the pad pattern portion of the thermal pad 122. For example, the area of ​​the exposed pattern can be smaller than the area of ​​the thermal pad 122, such as the exposed pattern falling into the pad pattern of the thermal pad 122 in a honeycomb pattern.

[0128] The above Figures 1 to 5 The single-layer packaging frame 11 shown requires prioritizing the avoidance of electrical conflicts when designing exposed patterns, which can result in insufficient electrical network fill rate and potentially limit the graphic design of the second pattern to some extent. In contrast, the electrical network fill rate in the multi-layer packaging frame 21 shown in this embodiment can be arbitrarily set, thus effectively avoiding electrical conflicts while providing greater flexibility in the graphic design of the second pattern.

[0129] by Figures 7 to 9 Taking the dual-layer package frame 21 shown as an example, by designing the portion of the electrical connection pattern between the pin pad 121 and the body 10 that falls into the second pattern into the inner layer of the dual-layer structure, it is possible to achieve complete alignment between the chip 2 and the heat dissipation pad 122 while ensuring that no electrical short circuit occurs when the chip 2 is soldered to the target PCB board. This results in superior heat dissipation.

[0130] Furthermore, considering that the inner frame of the double-layer structure has an electrical network connecting the pin pads 121 and the body 10, the pattern of the electrical network connecting the heat dissipation pads 122 and the body 10, which is also arranged in the inner frame, can be comb-shaped, similar to the above. Figures 1 to 5 The second pattern of chip 1 in the illustrated embodiment is as follows: Figure 8 The area outlined by the dashed line is shown in the figure. This ensures that the electrical network connecting the pin pad 121 and the body 10 is not interfered with, while also guaranteeing a reliable electrical connection and heat dissipation between the working device and the heat sink pad 122.

[0131] It should be noted that this embodiment uses a two-layer packaging frame 21 as an example for demonstration. In practical applications, the packaging frame 21 can be a three-layer or even more-layer structure. Accordingly, for the outermost frame in the multi-layer structure, the electrical network of this layer is designed according to the second pattern aligned (or as closely aligned as possible) with the pad pattern of the heat dissipation pad 122; for the electrical network on the inner frame in the multi-layer structure, it is sufficient to ensure successful connection to the pin pad 121 and the heat dissipation pad 122.

[0132] Figure 10 This is a flowchart of a chip manufacturing method according to the third embodiment of the present invention. This embodiment can be adapted to manufacture the above-mentioned chip. Figures 1 to 5 Chip 1 shown, or the manufacturing of the above Figures 7 to 9 Chip 2 is shown. Therefore, the explanation of the terms used in this embodiment can be found by referring to... Figures 1 to 9 The relevant descriptions of the embodiments shown will not be repeated here.

[0133] Specifically, refer to Figure 10 The chip manufacturing method described in this embodiment may include the following steps:

[0134] Step S101: Obtain the target pattern, wherein the target pattern includes the pad positions of the pads and the layout of the electrical network on the target printed circuit board.

[0135] Step S102: Determine the exposed pattern of the packaging frame according to the target pattern, so that the exposed pattern matches the target pattern;

[0136] Step S103: Electrically connect the packaging frame to the first side of the body to obtain the chip, wherein the body has a first side and a second side opposite to each other, and the exposed pattern is located on the side of the packaging frame opposite to the body.

[0137] The chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0138] In some embodiments, the target pattern can be pre-acquired and stored in a preset database, and correspondingly, the target pattern can be retrieved from the preset database in step S101.

[0139] Alternatively, when performing step S101, the target pattern can be obtained from the target printed circuit board in real time.

[0140] In some embodiments, the target pattern can be the pad positions and electrical network layout of all pads on the target printed circuit board. Accordingly, in step S102, the pattern of the area where the chip needs to be mounted in the target pattern is extracted, and a matching pattern is determined accordingly.

[0141] Alternatively, the target pattern can be the pad positions and electrical network layout of the pads in the area where the chip is mounted on the target printed circuit board. Accordingly, in step S102, the matching pattern is determined directly based on the target pattern.

[0142] In one specific implementation, matching the exposed pattern and the target pattern determined in step S102 may include ensuring that there are no electrical network conflicts in the overlapping areas of the exposed pattern and the target pattern. This ensures that the chip manufactured using this embodiment is compatible with the target PCB board.

[0143] In one specific implementation, step S103 may include: setting solder joints and an electrical network on a first side of the body; and electrically connecting the packaging frame to the first side of the body via the solder joints. For example, the packaging frame is soldered to the first side of the body via solder joints, and the solder joints and electrical network on the body and the electrical network of the packaging frame are correspondingly connected to form an electrical path.

[0144] Furthermore, after electrically connecting the packaging frame to the first side of the body in step S103, steps such as molding can be performed to obtain a complete chip.

[0145] In one specific implementation, step S102 may include the steps of: determining a matching pattern based on the target pattern, wherein the matching pattern includes the layout of the electrical network on the packaging frame and the structure of the solder joint connection between the packaging frame facing the body and the body, the body and the target printed circuit board being electrically connected through the electrical network provided by the matching pattern; and obtaining the exposed pattern based on the matching pattern.

[0146] For example, for a single-layer packaging frame, step S102 may further include the step of: partially etching the packaging frame to remove a portion of the matching pattern on the side of the packaging frame opposite to the body, the remaining portion of the matching pattern being adapted to form the exposed pattern, such as... Figures 2 to 4 As shown. In this example, the exposed pattern can be obtained by performing a semi-etching process after the package frame is soldered to the body 10.

[0147] For example, for a multi-layered packaging frame, step S102 may further include the step of determining the layout of the electrical network on the outermost frame of the matching pattern as the exposed pattern. In this example, the exposed pattern can be laid out on the outermost frame of the packaging frame during the design phase. Accordingly, after the packaging frame is soldered to the body 10, the exposed pattern can be directly formed without half-etching or other processing. Furthermore, in this example, the exposed pattern can be substantially consistent with the target pattern.

[0148] In one specific implementation, the pad may include a lead pad, and the exposed pattern may include a first pattern. Accordingly, step S102 may include the step of determining the distribution of the first pattern on the package frame according to the pad position of the lead pad.

[0149] In one specific implementation, the pad may include a heat dissipation pad, and the exposed pattern may include a second pattern. Accordingly, step S102 may include the step of: determining the second pattern based on the pad pattern of the heat dissipation pad and the number of layers of the package frame, so that the second pattern falls within the pad pattern of the heat dissipation pad. Furthermore, the distribution of the second pattern on the package frame also corresponds to the pad position of the heat dissipation pad on the target PCB board.

[0150] In some embodiments, combined with Figures 7 to 9 When the package frame has a multi-layer structure, the second pattern can be determined based on the pad pattern of the thermal pad. For example, the pad pattern of the thermal pad can be directly determined as the second pattern. Alternatively, the second pattern can be designed to be as close as possible to the pad pattern of the thermal pad; for example, if the pad pattern of the thermal pad is rectangular, the second pattern can be circular, and vice versa. Yet another example is that the second pattern can be designed as multiple independent patterns, distributed within the area enclosed by the thermal pad.

[0151] In some embodiments, combined with Figures 1 to 5 When the encapsulation frame is a single-layer structure, the remaining portion of the encapsulation frame after half-etching on the side facing away from the body can be matched with the pattern to determine the second pattern. This creates a step on the side of the encapsulation frame facing away from the body, preventing the uncovered portion of the exposed pattern from being exposed.

[0152] Furthermore, after completing the semi-etching process on the packaging frame, the processed packaging frame and the chip body can be molded together to obtain the chip. At this time, the electrical network layout on the front of the chip exposed outside the molded body is called the exposed pattern.

[0153] Figure 11 This is a flowchart of a chip mounting method according to the third embodiment of the present invention. This embodiment can be adapted to use the chip mounting method described above. Figure 10 The chip manufactured by the method shown is soldered to the target PCB board. That is, using this embodiment, leadless chips (as described above) can be soldered onto the target PCB board. Figures 1 to 5 Chip 1 shown, or the manufacturing of the above Figures 7 to 9 The chip 2) shown is soldered to the target PCB board designed for pinned chips. Therefore, the explanations of the terms used in this embodiment can be found in [reference needed]. Figures 1 to 9 The relevant descriptions of the embodiments shown will not be repeated here.

[0154] Specifically, refer to Figure 11The chip mounting method described in this embodiment may include the following steps:

[0155] Step S201, obtain the above Figures 1 to 9 The chip described in any of the embodiments shown;

[0156] Step S202: Obtain a target printed circuit board, the target printed circuit board having a first side and a second side opposite to each other, and the target pattern is provided on the first side of the target printed circuit board;

[0157] Step S203: A mask layer is provided on the first side of the target printed circuit board. The mask layer has a window pattern to expose part of the target pattern, and the window pattern matches the exposed pattern.

[0158] Step S204: Fill the window area defined by the window pattern with electrical connection material, and mount the chip to the first side of the target printed circuit board, wherein the chip is electrically connected to the target printed circuit board through the electrical connection material.

[0159] The chip includes a leadless chip, and the target pattern is designed for a chip with leads.

[0160] In some embodiments, the electrical connection material may be, for example, solder.

[0161] Considering that the pad pattern on the target PCB board may be significantly larger than the exposed pattern on the bottom of chip 1 (or chip 2), especially since the second pattern on the bottom of chip 1 is no longer a large, continuous copper structure but rather a sparse, comb-like strip structure, opening the entire heat dissipation pad 122 during chip 1 soldering to the target PCB board could lead to problems such as excessive solder buildup under chip 1, affecting the soldering effect. Here, "opening the window" refers to the area on the target PCB board where the copper on the pad is exposed for soldering, without being covered by a mask layer (e.g., not covered by a solder resist layer or not covered by a stencil).

[0162] Therefore, in this embodiment, when using the above... Figure 10 After the chip is manufactured using the method described in the illustrated embodiment, to achieve better soldering results, a mask layer can be specifically designed to adjust the window pattern on the target PCB board when soldering the chip to the target PCB board. For example, when soldering the chip to the target PCB board... Figures 1 to 5 When the chip 1 shown is mounted onto the target PCB board, the window pattern on the mask layer in step S203 can be designed as follows: Figure 6 The shape outlined by a dashed line at the midpoint.

[0163] In other words, in this embodiment, the window pattern no longer perfectly matches the target pattern, but is designed based on the exposed pattern. This ensures that there are windows on the target PCB where the exposed pattern and the target pattern overlap. Furthermore, a mask layer is used to cover any excess target pattern, thus preventing the window area from being too large and affecting the soldering effect.

[0164] In some embodiments, the window pattern can be adjusted by fine-tuning the shape of the solder mask layer. Accordingly, step S203 may include the step of forming a solder mask layer on a first side of the target printed circuit board using the window pattern as a mask.

[0165] For example, when spraying solder resist onto a target PCB board, a windowed pattern can be used as a mask pattern. This creates a windowed pattern on the first side of the target PCB board that is covered by the mask pattern but not coated with solder resist, forming a pattern that closely resembles the exposed pattern. Figure 6 Taking the area on the target PCB board that was not originally enclosed by the dotted line as an example, these areas can be regarded as the parts that do not fall into the window pattern. In this example, by covering this part of the area with the solder mask layer, too much solder can be avoided during soldering.

[0166] For example, when performing step S203, a solder resist layer can be applied to the first side of the entire target PCB board, and then the solder resist material falling into the area enclosed by the window pattern can be removed by means of chemical etching.

[0167] In some embodiments, the window pattern can be adjusted by fine-tuning the shape of the stencil. Accordingly, step S203 may include the step of covering a stencil on a first side of the target printed circuit board, wherein the window position and window area on the stencil are determined according to the window pattern.

[0168] For example, the area of ​​the stencil opening can be reduced so that when the stencil covers the surface of the target printed circuit board, excess parts of the target pattern can be covered, thereby reducing the position and amount of solder paste.

[0169] In one specific implementation, after step S204, the chip mounting method described in this embodiment may further include the step of removing the mask layer.

[0170] For example, in scenarios where the mask layer is a solder resist layer, the solder resist layer can be removed by chemical etching or other methods. In scenarios where the mask layer is a stencil, the stencil can be removed directly.

[0171] Therefore, this implementation scheme enables compatible mounting of leadless chips on target PCBs designed for leaded chips with minimal process improvements and high user ease of operation. Specifically, the leadless chip can be reliably mounted onto the target PCB designed for leaded chips simply by adjusting the window pattern on the mask layer to match the exposed pattern of the chip. Since there is no need to redesign the pattern of the copper layer on the target PCB (i.e., the target pattern), the modification to the customer is minor.

[0172] In one specific implementation, the mask layer can be pre-prepared on the PCB board (i.e., the aforementioned target PCB board), and the intermediate product obtained from this pre-preparation can be called a printed circuit board preform.

[0173] For example, when preparing a PCB board, during the process of coating the solder mask layer, the desired window pattern can be selected for production to obtain a PCB board preform that conforms to the pattern of exposed leaded chips in this embodiment.

[0174] For example, the PCB manufacturing process can follow the existing process, meaning the pad patterns on the resulting PCB will remain the same. Figure 6 The area outlined by the solid line is shown. Furthermore, before the PCB board leaves the factory, a stencil can be attached to the first side of the PCB board, and the position and area of ​​the openings on the stencil are determined according to the aforementioned opening pattern. Thus, a PCB board prefabricated part conforming to the leadless chip exposure pattern of this embodiment can also be obtained.

[0175] Accordingly, steps S202 and S203 can be replaced by the step: obtaining the printed circuit board preform. Compared to the above... Figure 11 The illustrated embodiment requires setting a mask layer before soldering when installing the chip. This embodiment pre-fabricates a mask layer on the printed circuit board that matches the exposed pattern of the leadless chip, further facilitating the installation operation. For example, users can obtain the above-mentioned... Figures 1 to 9 The chip shown and the printed circuit board prefabricated component described in this embodiment can be directly soldered to complete the chip installation.

[0176] Therefore, users can achieve compatible installation of leadless chips on PCBs designed for leaded chips without adjusting the mounting process when installing leadless chips onto the prefabricated printed circuit board.

[0177] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip, characterized in that, include: The body has a first side and a second side that are opposite to each other; A packaging frame is located on a first side of the body and electrically connected to the body. The exposed pattern of the packaging frame on the side opposite to the body matches a target pattern. The target pattern includes the pad positions of the pads and the layout of the electrical network on the target printed circuit board. The chip includes a leadless chip, and the target pattern is designed for a chip with leads.

2. The chip according to claim 1, characterized in that, The matching of the exposed pattern and the target pattern includes: there is no electrical network conflict in the area where the exposed pattern and the target pattern overlap.

3. The chip according to claim 1 or 2, characterized in that, The exposed pattern is part of the matching pattern, which includes the layout of the electrical network on the package frame and the structure of the solder joint connection between the package frame facing the body and the body. The matching pattern is determined according to the target pattern, and the body and the target printed circuit board are electrically connected through the electrical network provided by the matching pattern.

4. The chip according to claim 3, characterized in that, The encapsulation frame is a single-layer structure, and a portion of the matching pattern is exposed on the side of the encapsulation frame opposite to the body to form the exposed pattern.

5. The chip according to claim 3, characterized in that, The encapsulation frame has a multi-layer structure, and the matching pattern includes the layout of the power-on networks on each layer of the frame, wherein the layout of the power-on networks on the outermost frame forms the exposed pattern.

6. The chip according to claim 5, characterized in that, The exposed pattern is substantially consistent with the target pattern.

7. The chip according to claim 1, characterized in that, The pads include pin pads, and the exposed pattern includes a first pattern, the distribution of which on the package frame corresponds to the pad positions of the pin pads.

8. The chip according to claim 1 or 7, characterized in that, The pad includes a heat dissipation pad, and the exposed pattern includes a second pattern that falls within the pad pattern of the heat dissipation pad.

9. The chip according to claim 8, characterized in that, The packaging frame has a multi-layer structure, and the second pattern is determined based on the pad pattern of the heat dissipation pad. The second pattern includes the layout of the power network on the outermost layer of the multi-layer frame.

10. The chip according to claim 8, characterized in that, The packaging frame is a single-layer structure. The second pattern is a pattern formed by exposing the matching pattern on the side of the packaging frame away from the body. The matching pattern includes the layout of the electrical network on the packaging frame and the structure of the solder joint connection between the side of the packaging frame facing the body and the body. The matching pattern is determined according to the target pattern. The body and the target PCB are electrically connected through the electrical network provided by the matching pattern.

11. The chip according to claim 1, characterized in that, The first side of the body is provided with solder joints and electrical network, and the body is electrically connected to the packaging frame through the solder joints and electrical network.

12. The chip according to claim 11, characterized in that, The solder joints include multiple input voltage solder joints and multiple output voltage solder joints arranged in an alternating array, and the input voltage solder joints and output voltage solder joints are staggered.

13. The chip according to claim 11, characterized in that, The packaging frame includes multiple strip-shaped electrical networks adapted to electrically connect the solder joints and the pads.

14. The chip according to claim 1, characterized in that, The pinless chip includes a flip chip, and / or the chip includes a power distribution chip.

15. The chip according to claim 1, characterized in that, The body includes: A semiconductor substrate having opposing front and back sides, the front side facing a first side of the body and the back side facing a second side of the body; The working device is formed on the front side of the semiconductor substrate, and the package frame is located on the side of the working device away from the semiconductor substrate.

16. A chip manufacturing method, characterized in that, include: Obtain a target pattern, wherein the target pattern includes the pad positions and electrical network layout of the pads on the target printed circuit board; The exposed pattern of the packaging frame is determined based on the target pattern so that the exposed pattern matches the target pattern. The chip is obtained by electrically connecting the packaging frame to a first side of the body, wherein the body has a first side and a second side opposite to each other, and the exposed pattern is located on the side of the packaging frame opposite to the body; The chip includes a leadless chip, and the target pattern is designed for a chip with leads.

17. The chip manufacturing method according to claim 16, characterized in that, The matching of the exposed pattern and the target pattern includes: there is no electrical network conflict in the area where the exposed pattern and the target pattern overlap.

18. The chip manufacturing method according to claim 16 or 17, characterized in that, The step of determining the exposed pattern of the packaging frame according to the target pattern, so that the exposed pattern matches the target pattern, includes: A matching pattern is determined based on the target pattern, wherein the matching pattern includes the layout of the electrical network on the packaging frame and the structure of the solder joint connection between the packaging frame facing the body and the body, and the body and the target printed circuit board are electrically connected through the electrical network provided by the matching pattern; The exposed pattern is obtained based on the matching pattern.

19. The chip manufacturing method according to claim 18, characterized in that, The encapsulation frame is a single-layer structure, and obtaining the exposed pattern based on the matching pattern includes: The package frame is partially etched to remove a portion of the matching pattern on the side of the package frame opposite to the body, leaving the remaining matching pattern adapted to form the exposed pattern.

20. The chip manufacturing method according to claim 18, characterized in that, The encapsulation frame has a multi-layer structure, the matching pattern includes the layout of the power-on networks on each layer of the frame, and obtaining the exposed pattern based on the matching pattern includes: The layout of the electrical network on the outermost frame of the matching pattern is determined as the exposed pattern.

21. The chip manufacturing method according to claim 20, characterized in that, The exposed pattern is substantially consistent with the target pattern.

22. The chip manufacturing method according to claim 16, characterized in that, The pads include pin pads, the exposed pattern includes a first pattern, and determining the exposed pattern of the package frame based on the target pattern includes: The distribution of the first pattern on the package frame is determined according to the pad positions of the pin pads.

23. The chip manufacturing method according to claim 16 or 22, characterized in that, The pads include heat dissipation pads, the exposed pattern includes a second pattern, and determining the exposed pattern of the package frame based on the target pattern includes: The second pattern is determined based on the pad pattern of the heat dissipation pad and the number of layers of the package frame, so that the second pattern falls within the pad pattern of the heat dissipation pad.

24. The chip manufacturing method according to claim 23, characterized in that, The step of determining the second pattern based on the pad pattern of the heat dissipation pad and the number of layers of the package frame includes: When the package frame is a multi-layer structure, the second pattern is determined according to the pad pattern of the heat dissipation pad, wherein the second pattern includes the layout of the electrical network on the outermost frame of the multi-layer frame; when the package frame is a single-layer structure, the remaining part of the package frame after half-etching away from the body is determined as the second pattern, wherein the matching pattern includes the layout of the electrical network on the package frame and the structure of the solder joint connection between the package frame facing the body and the body, the matching pattern is determined according to the target pattern, and the body and the target PCB are electrically connected through the electrical network provided by the matching pattern.

25. The chip manufacturing method according to claim 16, characterized in that, The step of electrically connecting the packaging frame to the first side of the body to obtain the chip includes: Solder joints and electrical networks are provided on the first side of the body; The encapsulation frame is electrically connected to the first side of the body via the solder joints.

26. A chip mounting method, characterized in that, include: Obtain the chip according to any one of claims 1 to 15 above; A target printed circuit board is obtained, the target printed circuit board having a first side and a second side opposite to each other, and the target pattern is provided on the first side of the target printed circuit board; A mask layer is provided on the first side of the target printed circuit board, the mask layer having a window pattern to expose a portion of the target pattern, the window pattern matching the exposed pattern; Electrical connection material is filled in the window area defined by the window pattern, and the chip is mounted to the first side of the target printed circuit board, wherein the chip is electrically connected to the target printed circuit board through the electrical connection material; The chip includes a leadless chip, and the target pattern is designed for a chip with leads.

27. The chip mounting method according to claim 26, characterized in that, After mounting the chip onto the first side of the target printed circuit board, the method further includes: removing the mask layer.

28. The chip mounting method according to claim 26, characterized in that, The step of setting a mask layer on the first side of the target printed circuit board includes: Using the windowed pattern as a mask, a solder resist layer is formed on the first side of the target printed circuit board; or A steel mesh is used to cover the first side of the target printed circuit board, and the window positions and window areas on the steel mesh are determined according to the window pattern.

29. A printed circuit board preform, characterized in that, include: A printed circuit board has a first side and a second side opposite to each other. The first side of the printed circuit board is provided with a target pattern, which includes the pad positions of the pads on the printed circuit board and the layout of the electrical network. A mask layer is disposed on the first side of the printed circuit board. The mask layer has a window pattern to expose a portion of the target pattern. The window pattern matches the exposed pattern. The exposed pattern is the layout of the electrical network exposed by the chip's packaging frame. The exposed pattern matches the target pattern. The chip includes a leadless chip, and the target pattern is designed for a chip with leads.

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