A low-capacitance wire bonding structure for ESD protection

Abstract

This invention provides a low-capacitance wire-bonding structure utilizing a passivation layer dielectric, comprising: an n-type substrate; a P-type well region; a first N+ contact region; a second N+ contact region; a first P+ region; a second P+ region; a first oxide dielectric region; a second oxide dielectric region; a third oxide dielectric region; a first metal electrode; a second metal electrode; a first passivation layer region; a second passivation layer region; a third passivation layer region; and a conductive adhesive or solder region. This invention removes the metal region above the parasitic capacitance and opens both ends of the remaining metal, connecting it to the metal via subsequent wire bonding solder. In this way, the equivalent dielectric layer thickness of the device's pad metal region becomes the total thickness of the dielectric plus the passivation layer, which is considered a dielectric layer, thereby significantly reducing capacitance without affecting process parameters, device area, or current carrying capacity.

Description

Technical Field

[0001] This invention belongs to the field of electronic science and technology, and is mainly used for electrostatic discharge (ESD) protection technology. More specifically, it is a novel method for optimizing the size of parasitic pad metal capacitance in devices. Its core idea is to use a passivation layer dielectric to increase the dielectric layer thickness between the pad metal and the substrate, thereby reducing the parasitic capacitance of the pad metal, and relates to the device structure. Background Technology

[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. ESD is present in every aspect of daily life. However, this seemingly commonplace electrical phenomenon poses a fatal threat to delicate integrated circuits. With advancements in integrated circuit manufacturing processes, the minimum linewidth has decreased to the sub-micron or even nanometer level. While this has led to improved chip performance, it has also significantly reduced ESD resistance, making electrostatic damage more severe. Most ESD incidents cause non-fatal damage to integrated circuits, reducing their lifespan and reliability, and ultimately causing system functional degradation. This poses a significant obstacle to achieving large-scale, highly reliable integration.

[0003] Currently, electronic devices also include data transmission interfaces. For these interfaces, in addition to providing basic ESD protection, the devices must be "completely invisible" during normal system operation (data transmission), meaning they cannot interfere with the integrity of the data transmission signal. This places stringent requirements on the parasitic capacitance of the ESD protection devices. Therefore, with ever-increasing data transmission speeds, ensuring sufficient ESD protection while minimizing capacitance and maintaining signal integrity of high-speed data interfaces has become a new and serious challenge. In the parasitic capacitance of ESD devices, the MIS parasitic capacitance formed by the metal and silicon substrate accounts for a portion of the total capacitance. The main objective of this invention is to reduce this portion of capacitance through technological means.

[0004] In traditional structures (such as) Figure 1As shown, the pad metal is continuous, which leads to the formation of excess parasitic capacitance in the empty area below the pad where there are no device structures. To eliminate this parasitic capacitance, it is best to increase the dielectric thickness. However, due to process limitations, changes in dielectric thickness affect the via size, and the increase in thickness is limited, resulting in less than ideal capacitance suppression. To significantly increase the equivalent dielectric thickness, this invention removes the metal area above the parasitic capacitance and opens it at both ends, connecting it to the metal via subsequent wire bonding solder. In this way, the equivalent dielectric thickness of the device pad metal area becomes the total thickness of the dielectric plus passivation layer, thereby greatly reducing capacitance without affecting process parameters, device area, or current carrying capacity. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: without increasing the device area, by removing the metal area above the parasitic capacitance and opening the two ends of the remaining metal, and connecting it to the metal inside the passivation layer opening through subsequent wire bonding solder, the equivalent dielectric layer thickness of the device pad metal area becomes the total thickness of the dielectric plus the passivation layer which is regarded as the dielectric layer, thereby greatly reducing the capacitance, while having no impact on process parameters, device area, and current capacity.

[0006] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0007] A low-capacitance wire bonding structure for ESD protection includes: an n-type substrate 01; a first N+ contact region 11, a first P+ region 21, and a P-type well region 02 sequentially implanted from left to right on the surface of the n-type substrate 01; a second N+ contact region 12 and a second P+ region 22 implanted on the inner surface of the P-type well region 02; an oxide layer dielectric grown on the surface of the n-type substrate 01, with openings above the first P+ region 21 and the second N+ contact region 12, such that the oxide layer dielectric is divided into three parts, from left to right: a first oxide layer dielectric region 31, a second oxide layer dielectric region 32, and a third oxide layer dielectric region 33; a metal deposited on the oxide layer dielectric and a section of metal located in the middle above the second oxide layer dielectric 32 removed, the remaining two metal parts being a first metal electrode 41 and a second metal electrode from left to right. 42, so that the right end of the first metal electrode 41 covers part of the upper left surface of the second oxide layer medium region 32, and the left end of the second metal electrode 42 covers part of the upper right surface of the second oxide layer medium region 32; a passivation layer is grown above the oxide layer medium and the metal electrode, and an opening is made above the first metal electrode 41 and the second metal electrode 42, so that the passivation layer is divided into three parts, from left to right: the first passivation layer region 51, the second passivation layer region 52 and the third passivation layer region 53; the first passivation layer region 51 is located above the first metal electrode 41, the second passivation layer region 52 fills the gap above the cut-off metal part in the second oxide layer medium region 32, and the third passivation layer region 53 is located above the second metal electrode 42, and conductive adhesive or solder area 06 is applied or soldered on the passivation layer and covers the opening of the metal electrode.

[0008] As a preferred embodiment, a second P-type well region 022 is implanted on the surface of the n-type substrate 01 and below the second passivation layer 52; a third N+ region 13 is implanted on the inner surface of the second P-type well region 022.

[0009] The beneficial effects of this invention are as follows: By removing the metal region above the parasitic capacitance and opening the remaining metal at both ends, the metal is connected to the substrate via solder in subsequent wire bonding. This makes the equivalent dielectric layer thickness of the pad metal region of the device the total thickness of the dielectric plus the passivation layer considered as the dielectric layer, thereby significantly reducing capacitance without affecting process parameters, device area, or current carrying capacity. The low-capacitance wire bonding structure for ESD protection of this invention effectively reduces the parasitic capacitance between the pad and the substrate. Since the wire bonding area cleverly replaces the original pad metal region, the device's metal current carrying capacity is theoretically unaffected. Furthermore, because the dielectric below the wire bonding area is composed of oxide and passivation layers, the parasitic capacitance of the wire bonding metal to the substrate is greatly reduced, making it a universal low-capacitance optimization method. Attached Figure Description

[0010] Figure 1It uses a traditional pad metal binding wire structure.

[0011] Figure 2 This is a low-capacitance wire binding structure for ESD protection according to Embodiment 1 of the present invention.

[0012] Figure 3 This is a low-capacitance wire binding structure for ESD protection according to Embodiment 2 of the present invention.

[0013] 01 is an n-type substrate, 02 is a P-type well region, 11 is the first N+ contact region, 12 is the second N+ contact region, 13 is the third N+ region, 21 is the first P+ region, 22 is the second P+ region, 31 is the first oxide layer dielectric region, 32 is the second oxide layer dielectric region, 33 is the third oxide layer dielectric region, 41 is the first metal electrode, 42 is the second metal electrode, 51 is the first passivation layer region, 52 is the second passivation layer region, 53 is the third passivation layer region, 06 is the conductive adhesive or solder region, and 022 is the second P-type well region. Detailed Implementation

[0014] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0015] Example 1:

[0016] This invention proposes a low-capacitance wire-binding structure for ESD protection: The device comprises: an n-type substrate 01; a first N+ contact region 11, a first P+ region 21, and a P-type well region 02 sequentially implanted from left to right on the surface of the n-type substrate 01; a second N+ contact region 12 and a second P+ region 22 implanted on the inner surface of the P-type well region 02; an oxide layer dielectric grown on the surface of the n-type substrate 01, with openings above the first P+ region 21 and the second N+ contact region 12, such that the oxide layer dielectric is divided into three parts, from left to right: a first oxide layer dielectric region 31, a second oxide layer dielectric region 32, and a third oxide layer dielectric region 33; metal deposited on the oxide layer dielectric, and a section of metal located in the middle above the second oxide layer dielectric 32 removed, the remaining two metal parts being a first metal electrode 41 and a second oxide layer dielectric region 42, from left to right. The second metal electrode 42 covers a portion of the upper left surface of the second oxide layer medium region 32 with the right end of the first metal electrode 41, and covers a portion of the upper right surface of the second oxide layer medium region 32 with the left end of the second metal electrode 42. A passivation layer is grown above the oxide layer medium and the metal electrode, and an opening is made above the first metal electrode 41 and the second metal electrode 42, so that the passivation layer is divided into three parts, from left to right: a first passivation layer region 51, a second passivation layer region 52 and a third passivation layer region 53. The first passivation layer region 51 is located above the first metal electrode 41, the second passivation layer region 52 fills the gap above the cut-off metal portion in the second oxide layer medium region 32, and the third passivation layer region 53 is located above the second metal electrode 42. Conductive adhesive or solder area 06 is applied or soldered above the passivation layer and covers the opening of the metal electrode.

[0017] Example 2:

[0018] Based on Embodiment 1, the device introduces a series junction capacitance to further reduce the total parasitic Pad capacitance. Specifically, compared to the original structure, the difference is that a second P-type well region 022 is implanted on the surface of the n-type substrate 01 and below the second passivation layer 52; a third N+ region 13 is implanted on the inner surface of the second P-type well region 022.

[0019] Working principle:

[0020] According to the common formula for calculating the capacitance of a parallel-plate capacitor, c = εS / 4πkD, where ε is the dielectric constant of the dielectric, S is the area between the plates, D is the distance between the plates, and k is the electrostatic constant, the novel structure proposed in this invention utilizes a passivation layer, which effectively increases the dielectric layer thickness D between the conductive adhesive or solder area 06 and the n-type substrate 01, thus effectively reducing parasitic Pad capacitance. Simultaneously, the modified structure of this invention adds two series-connected junction capacitances: the junction capacitance between the third N+ contact area 13 and the second P-type well area 022, and the junction capacitance between the second P-type well area 022 and the n-type substrate 01, further reducing parasitic capacitance. Since this invention does not modify the original process parameters and steps, it only requires adjusting the layout design to achieve a remarkably low parasitic capacitance effect, making it an excellent wiring method for ultra-low capacitance ESD or other high-speed devices. Furthermore, this technology is a universal bonding technique that can reduce parasitic capacitance in ESD devices, power devices, or other high-speed signal integrated circuits, thus offering significant advantages in fields such as radio frequency and high-speed signal applications.

[0021] In summary, this invention proposes a low-capacitance wire-binding structure for ESD protection, which effectively reduces the parasitic capacitance between the pad and the substrate. Since the wire-binding area cleverly replaces the original pad metal area, the device's metal current-carrying capacity is theoretically unaffected. Furthermore, because the dielectric beneath the wire-binding area is composed of oxide and passivation layers, the parasitic capacitance of the wire-binding metal to the substrate is significantly reduced, making it a versatile low-capacitance optimization technique. The device structure and accompanying drawings provided in this invention are merely illustrative of the wire-binding structure. Besides the structure shown in the drawings, this wire-binding technique can also be used in various other high-speed devices or circuits (such as various high-speed TVS devices or arrays, high-speed discrete gate MOS devices, high-speed signal integrated circuits, and other applications requiring low parasitic capacitance). Therefore, any wire-binding structure involving the use of a passivation layer dielectric to reduce pad parasitic capacitance should be within the scope of this invention.

[0022] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low-capacitance wire bonding structure for ESD protection, characterized in that... include: n-type substrate (01); A first N+ contact region (11), a first P+ region (21), and a P-type well region (02) are sequentially implanted from left to right on the surface of an n-type substrate (01); a second N+ contact region (12) and a second P+ region (22) are implanted inside the P-type well region (02); an oxide layer medium is grown on the surface of the n-type substrate (01) and holes are made above the first P+ region (21) and the second N+ contact region (12), so that the oxide layer medium is divided into three parts, from left to right: a first oxide layer medium region (31), a second oxide layer medium region (32), and a third oxide layer medium region (33); metal is deposited on the oxide layer medium and a section of metal located in the middle above the second oxide layer medium (32) is removed, and the remaining two parts of metal are the first metal electrode (41) and the second metal electrode (42) from left to right, so that the first metal electrode (41) The right end of the second oxide layer medium region (32) covers part of the upper left surface of the second oxide layer medium region (32), so that the left end of the second metal electrode (42) covers part of the upper right surface of the second oxide layer medium region (32); a passivation layer is grown above the oxide layer medium and the metal electrode and an opening is made above the first metal electrode (41) and the second metal electrode (42), so that the passivation layer is divided into three parts, from left to right: the first passivation layer region (51), the second passivation layer region (52) and the third passivation layer region (53); the first passivation layer region (51) is located above the first metal electrode (41), the second passivation layer region (52) fills the gap formed after the metal is cut off on the second oxide layer medium region (32), the third passivation layer region (53) is located above the second metal electrode (42), and the conductive adhesive or solder area (06) is applied or soldered on the passivation layer and covers the opening of the metal electrode.

2. The low-capacitance wire bonding structure for ESD protection according to claim 1, characterized in that: A second P-type well region (022) is implanted on the surface of an n-type substrate (01) and below the second passivation layer (52); a third N+ region (13) is implanted on the inner surface of the second P-type well region (022).

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