A high-isolation semiconductor single-pole double-throw switch based on transmission zero points
By introducing a parallel resonant circuit into the RF single-pole double-throw switch to generate a transmission zero, the challenges of small size and high isolation are solved, realizing a high-isolation and miniaturized RF switch design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2022-12-01
- Publication Date
- 2026-06-23
AI Technical Summary
Existing RF single-pole double-throw switches cannot simultaneously achieve small size and high isolation. Traditional design methods result in large chip size and limited means of improving isolation.
The design employs a parallel resonant circuit to generate transmission zeros. By using a parallel resonant unit composed of parallel transistors and inductors, transmission zeros and transmission poles are formed, improving isolation and simplifying the switching structure.
It achieves miniaturization and high isolation of the switch, with isolation increased to over 20dB, chip size less than 1 square millimeter, and performance significantly improved.
Smart Images
Figure CN115940910B_ABST
Abstract
Description
Technical Field
[0001] This invention discloses a high-isolation semiconductor single-pole double-throw switch based on transmission zero point, which relates to radio frequency integrated circuit design technology and belongs to the technical field of basic electronic circuits. Background Technology
[0002] A radio frequency (RF) single-pole double-throw (SPDT) switch is a control circuit widely used in communications, radar, and detection fields. It is typically a three-port circuit, with one end connected to the antenna, one end to the transmit link, and the other end to the receive link. Field-effect transistor (FET) based switches offer the advantage of low power consumption due to their small gate current. The main technical specifications of an RF SPDT switch include: operating bandwidth, conduction branch loss, disconnection branch isolation, chip size, in-band impedance matching, and power capacity. However, due to design process limitations, it is difficult to simultaneously achieve small size and high isolation in RF SPDT switches.
[0003] Existing single-pole double-throw switches can be divided into two types according to different circuit design principles: The first type is a single-pole double-throw switch that uses a series-parallel transistor structure. A capacitor is added between the series and parallel transistors to assist in matching. Isolation is improved by extending multiple stages of transistors, but this comes at the cost of chip size. The second type is a single-pole double-throw switch that uses a multi-stage series-parallel transistor structure. Isolation is improved by cascading multiple stages of transistors, but the reuse rate of the series-parallel transistor structure is low, and it cannot simultaneously achieve the requirements of small switch size and high isolation.
[0004] In summary, existing single-pole double-throw switches need improvement in the following aspects: (1) the means to achieve high isolation of the turn-off branch are relatively simple and it is difficult to achieve high isolation; (2) in order to achieve high isolation, many transistors and quarter-wavelength impedance transformation lines are generally used, resulting in a large chip size. Summary of the Invention
[0005] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a high-isolation semiconductor single-pole double-throw switch based on transmission zero point, solving the technical problem of complex semiconductor switch structures to achieve high isolation performance, and realizing the invention objective of miniaturizing semiconductor switches while achieving high isolation.
[0006] To achieve the above-mentioned objectives, the present invention employs the following technical solution:
[0007] A high-isolation semiconductor single-pole double-throw switch based on transmission zero point, comprising:
[0008] The first RF port is connected to one end of the input matching module;
[0009] The first switching arm includes at least one parallel resonant unit, a first parallel transistor, and a first output matching module. The at least one parallel resonant unit is connected in sequence to form a series branch. The input terminal of the series branch serves as the input terminal of the first switching arm and is connected to the other end of the input matching module. The output terminal of the series branch, the source of the first parallel transistor, and one end of the first output matching module are connected together. The other end of the first output matching module serves as the output terminal of the first switching arm. The drain of the first parallel transistor is grounded, and the gate of the first parallel transistor is connected to the first DC port.
[0010] The second switching arm includes at least one parallel resonant unit, a second parallel transistor, and a second output matching module. The at least one parallel resonant unit is connected in sequence to form a series branch. The input terminal of the series branch serves as the input terminal of the second switching arm and is connected to the other end of the input matching module. The output terminal of the series branch, the source of the second parallel transistor, and one end of the second output matching module are connected together. The other end of the second output matching module serves as the output terminal of the second switching arm. The drain of the second parallel transistor is grounded, and the gate of the second parallel transistor is connected to the second DC port.
[0011] The second radio frequency port is connected to the output terminal of the first switch arm; and...
[0012] The third RF port is connected to the output of the second switch arm.
[0013] As a further optimization scheme for a high-isolation semiconductor single-pole double-throw switch based on transmission zero, the parallel resonant unit includes: a transistor and an inductor. The source of the transistor is connected to one end of the inductor as the input terminal of the parallel resonant unit, and the drain of the transistor is connected to the other end of the inductor as the output terminal of the parallel resonant unit. The DC ports connected to each parallel resonant unit in the first switching arm have the same logic level, which is opposite to the logic level connected to the first DC port. The DC ports connected to each parallel resonant unit in the second switching arm have the same logic level, which is opposite to the logic level connected to the second DC port.
[0014] As a further optimization of the high-isolation semiconductor single-pole double-throw switch based on transmission zero point, the input matching module, the first output matching module, and the second output matching module are pure inductors, pure capacitors, or any combination of capacitors and inductors.
[0015] As a further optimization of the high-isolation semiconductor single-pole double-throw switch based on transmission zero point, the DC ports connected to the gates of the transistors in the first DC port, the second DC port, and each parallel resonant unit are connected to the DC bias voltage via gate resistors.
[0016] As a further optimization of the high-isolation semiconductor single-pole double-throw switch based on transmission zero point, the inductors contained in the input matching module, each parallel resonant unit of the first switch arm, the first output matching module, each parallel resonant unit of the second switch arm, and the second output matching module are microstrip inductors, stripline inductors, or spiral inductors.
[0017] As a further optimization of the high-isolation semiconductor single-pole double-throw switch based on transmission zero point, the capacitors included in the input matching module, the first output matching module, and the second output matching module are microstrip line capacitors, metal-insulator-metal capacitors, metal-oxide-metal capacitors, planar capacitors, or interdigital capacitors.
[0018] As a further optimization of the high-isolation semiconductor single-pole double-throw switch based on transmission zero, the transistor is a field-effect transistor, a high electron mobility transistor, an mHEMT, or a pHEMT transistor.
[0019] As a further optimization of the high-isolation semiconductor single-pole double-throw switch based on transmission zero point, the drain ground of the transistor is actually a terminal metallized grounding via, which contains weak parasitic effects.
[0020] The present invention, by adopting the above technical solution, has the following beneficial effects:
[0021] (1) The semiconductor double-throw switch proposed in this invention abandons the traditional method of using multiple parallel transistors or quarter-wavelength impedance transformation lines to improve isolation. Instead, it uses parallel resonant circuits to generate transmission zeros. Any parallel resonant circuit and parallel transistors can achieve a transmission zero in the turn-off branch and generate a transmission pole in the turn-on branch. The parallel transistors further improve the isolation, which can be effectively increased to more than 20dB.
[0022] (2) The semiconductor double-throw switch proposed in this invention can achieve miniaturization of the switch size by using the structure of multiplexed parallel resonant circuit. The size of a high isolation single-pole double-throw switch is less than 1 square millimeter. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of a high-isolation semiconductor single-pole double-throw switch based on transmission zero point provided in Embodiment 1 of the present invention.
[0024] Figure 2 This is a simulation curve showing the relationship between scattering parameters and frequency in Embodiment 1 of the present invention.
[0025] Figure 3 This is a schematic diagram of a high-isolation semiconductor single-pole double-throw switch based on transmission zero point provided in Embodiment 2 of the present invention.
[0026] Figure 4 This is a schematic diagram of a general structure of a high-isolation semiconductor single-pole double-throw switch based on transmission zero point according to the present invention.
[0027] The following are the labeling instructions in the diagram: 01, Input matching module; 11, First output matching module; 21, Second output matching module; 12, First parallel resonant unit; 21, Second parallel resonant unit; P1, First RF port; P2, Second RF port; P3, Third RF port; 001, Input matching inductor; K1, First DC port; K2, Second DC port; K11, Third DC port; K12, Fourth DC port; K21, Fifth DC port; K22, Sixth DC port; S1, First parallel transistor; S2, Second parallel transistor; S11, First transistor; S21, Second transistor; S12, Third transistor; S22, Fourth transistor; L11, First inductor; L21, Second inductor; L12, Third inductor; L22, Fourth inductor; Linput, Input matching inductor; Loutput1, First output matching inductor; Loutput2, Second output matching inductor. Detailed Implementation
[0028] The technical solution of the invention will now be described in detail with reference to the accompanying drawings.
[0029] The present invention discloses a general circuit structure for a high-isolation semiconductor single-pole double-throw switch based on a transmission zero point, as follows: Figure 4 As shown, it includes: a first RF port P1, a second RF port P2, a third RF port P3, a first switch arm, and a second switch arm. The first switch arm includes: a first parallel resonant unit 12, a first parallel transistor S1, and a first output matching module 11. The second switch arm includes: a second parallel resonant unit 22, a second parallel transistor S2, and a second output matching module 21. The first RF port P1 is connected to one end of the input matching module 01; the input terminals of the first parallel resonant unit 12 and the second parallel resonant unit 22 are both connected to the other end of the input matching module 01; the source of the first parallel transistor S1 and the output terminal of the first parallel resonant unit 12 are both connected to one end of the first output matching module 11; the other end of the first output matching module 11 is connected to the second RF port P2; the source of the second parallel transistor S2 and the other end of the second parallel resonant unit 22 are both connected to one end of the second output matching module 21; the other end of the second output matching module 21 is connected to the third RF port P3; the drains of the first parallel transistor S1 and the second parallel transistor S2 are both grounded; the gate of the first parallel transistor S1 is connected to the first DC port K1; and the gate of the second parallel transistor S2 is connected to the second DC port K2.
[0030] The first parallel resonant unit 12 includes: a first inductor L11 and a first transistor S11. One end of the first inductor L11 is connected to the source of the first transistor S11 as the input terminal of the first parallel resonant unit 12, and the other end of the first inductor L11 is connected to the drain of the first transistor S11 as the output terminal of the first parallel resonant unit 12. The gate of the first transistor S11 is connected to the third DC port K11.
[0031] The second parallel resonant unit 22 includes: a second inductor L21 and a second transistor S21. One end of the second inductor L21 is connected to the source of the second transistor S21 as the input terminal of the second parallel resonant unit 22, and the other end of the second inductor L21 is connected to the drain of the second transistor S21 as the output terminal of the second parallel resonant unit 22. The gate of the second transistor S21 is connected to the fifth DC port K21. Specific Implementation Example 1:
[0033] This embodiment presents a high-isolation semiconductor single-pole double-throw switch based on a transmission zero point, such as... Figure 1 As shown, in Figure 4 Based on the general circuit structure shown, the input matching inductor Linput is selected to implement the input matching module 01, the first output matching inductor Loutput1 is selected to implement the first output matching module 11, and the second output matching inductor Loutput2 is selected to implement the second output matching module 21.
[0034] One end of the input matching inductor Linput is connected to the first RF port P1.
[0035] In the first switching arm, the other end of the input matching inductor Linput is electrically connected to the source of the first transistor S11 and one end of the first inductor L11. The source of the first parallel transistor S1 is electrically connected to the drain of the first transistor S1 and the other end of the first inductor L11. The drain of the first parallel transistor S1 is grounded. One end of the first output matching inductor Loutput1 is connected to the drain of the first transistor S11, the other end of the first inductor L11, and the source of the first parallel transistor S1. The other end of the first output matching inductor Loutput1 is connected to the second RF port P2. The gate of the first parallel transistor S1 is connected to the first DC port K1. The gate of the first transistor S11 is connected to the third DC port K11.
[0036] In the second switching arm, the other end of the input matching inductor Linput is electrically connected to the source of the second transistor S21 and one end of the second inductor L21. The source of the second parallel transistor S2 is electrically connected to the drain of the second transistor S21 and the other end of the second inductor L21. The drain of the second parallel transistor S2 is grounded. One end of the second output matching inductor Loutput2 is connected to the drain of the second transistor S21, the other end of the second inductor L21, and the source of the second parallel transistor S2. The other end of the second output matching inductor Loutput2 is connected to the third RF port P3. The gate of the second parallel transistor S2 is connected to the second DC port K2. The gate of the second transistor S21 is connected to the fifth DC port K21.
[0037] The input matching inductor Linput is implemented using a microstrip line with a width of 20µm and a length of 100µm; the inductance value of the first inductor L11 in the first switching arm is 690pH; the first output matching inductor Loutput1 is implemented using a microstrip line with a width of 20µm and a length of 100µm; the first parallel transistor S1 is a HEMT with a gate width of 60µm; the first transistor S11 is a HEMT with a gate width of 50µm and a gate index of 4; the inductance value of the second inductor L21 in the second switching arm is 690pH; the second output matching inductor Loutput2 is implemented using a microstrip line with a width of 20µm and a length of 100µm; the second parallel transistor S2 is a HEMT with a gate width of 60µm; the second transistor S21 is a HEMT with a gate width of 50µm and a gate index of 4.
[0038] When the first DC port K1 is low, the third DC port K11 is high, the second DC port K2 is high, and the fourth DC port K21 is low, the first parallel transistor S1 and the second transistor S21 are turned off, and the second parallel transistor S2 and the first transistor S11 are turned on. That is, the first switch arm is turned on and the second switch arm is turned off. The second parallel resonant unit connected in series on the second switch arm in the off state generates an additional transmission zero. The second parallel resonant unit and the second parallel transistor on the second switch arm form a transmission pole with the same frequency as the above transmission zero on the first switch arm that is turned on.
[0039] The core circuit size of this single-pole double-throw switch is less than 1 square millimeter, and its isolation level generally reaches 20dB. Compared with existing small-sized single-pole double-throw switches, this switch has a significant advantage in isolation performance.
[0040] Figure 2 This is a simulation curve showing the relationship between scattering parameters and frequency in Embodiment 1 of the present invention. Figure 2As shown, the single-pole double-throw switch disclosed in Embodiment 1 of this invention has a center frequency of 27 GHz. At the center frequency, the insertion loss is 0.6 dB, the return loss is greater than 50 dB, and the isolation is greater than 50 dB. Compared with the prior art, the single-pole double-throw switch provided in Embodiment 1 of this invention has significantly improved return loss and isolation, significantly reduced insertion loss, and significantly improved performance. Specific Implementation Example 2:
[0042] This embodiment presents a high-isolation semiconductor single-pole double-throw switch based on a transmission zero point, such as... Figure 3 As shown, based on Embodiment 1, a parallel resonant unit composed of a third transistor S12 and a third inductor L12 is added to the first switch arm, and a parallel resonant unit composed of a fourth transistor S22 and a fourth inductor L22 is added to the second switch arm. The logic level connected to the fourth DC port K12, where the gate of the third transistor S12 is connected, is the same as the logic level connected to the third DC port K11. The logic level connected to the sixth DC port K22, where the gate of the fourth transistor S22 is connected, is the same as the logic level connected to the fifth DC port K21. The two parallel resonant units in the turn-off switch arm introduce two transmission zeros, and the two parallel resonant units and the parallel transistor in the turn-off switch arm introduce two transmission poles in the conduction branch.
[0043] The above embodiments are merely illustrative examples of the present invention and do not limit its scope of protection. Those skilled in the art can make partial changes to it. For example, several parallel resonant units can be added to the two switching arms to introduce multiple transmission zeros in order to improve the isolation. Any equivalent substitution in any form that conforms to the spirit of the invention falls within the scope of protection of the present invention.
Claims
1. A high-isolation semiconductor single-pole double-throw switch based on transmission zero point, characterized in that, include: The first RF port is connected to one end of the input matching module. The first switching arm includes at least one parallel resonant unit, a first parallel transistor, and a first output matching module. The at least one parallel resonant unit is sequentially connected to form a series branch. The input terminal of the series branch serves as the input terminal of the first switching arm and is connected to the other end of the input matching module. The output terminal of the series branch, the source of the first parallel transistor, and one end of the first output matching module are connected together. The other end of the first output matching module serves as the output terminal of the first switching arm. The drain of the first parallel transistor is grounded, and the gate of the first parallel transistor is connected to a first DC port. The second switching arm includes at least one parallel resonant unit, a second parallel transistor, and a second output matching module. The at least one parallel resonant unit is connected in sequence to form a series branch. The input terminal of the series branch serves as the input terminal of the second switching arm and is connected to the other end of the input matching module. The output terminal of the series branch, the source of the second parallel transistor, and one end of the second output matching module are connected together. The other end of the second output matching module serves as the output terminal of the second switching arm. The drain of the second parallel transistor is grounded, and the gate of the second parallel transistor is connected to a second DC port. The second radio frequency port is connected to the output terminal of the first switch arm, and, The third radio frequency port is connected to the output of the second switch arm; The parallel resonant unit includes a transistor and an inductor. The source of the transistor is connected to one end of the inductor as the input terminal of the parallel resonant unit, and the drain of the transistor is connected to the other end of the inductor as the output terminal of the parallel resonant unit. The DC ports connected to each parallel resonant unit in the first switching arm have the same logic level, which is opposite to the logic level connected to the first DC port. The DC ports connected to each parallel resonant unit in the second switching arm have the same logic level, which is opposite to the logic level connected to the second DC port.
2. The high-isolation semiconductor single-pole double-throw switch based on transmission zero point according to claim 1, characterized in that, The input matching module, the first output matching module, and the second output matching module are either pure inductors, pure capacitors, or any combination of capacitors and inductors.
3. The high-isolation semiconductor single-pole double-throw switch based on transmission zero point according to claim 1, characterized in that, The DC port connected to the gate of the transistor in the first DC port, the second DC port, and each parallel resonant unit is connected to the DC bias voltage via a gate resistor.
4. A high-isolation semiconductor single-pole double-throw switch based on transmission zero point according to claim 2, characterized in that, The inductors included in the input matching module, each parallel resonant unit of the first switch arm, the first output matching module, each parallel resonant unit of the second switch arm, and the second output matching module are microstrip inductors, stripline inductors, or spiral inductors.
5. A high-isolation semiconductor single-pole double-throw switch based on transmission zero point according to claim 2, characterized in that, The capacitors included in the input matching module, the first output matching module, and the second output matching module are microstrip line capacitors, metal-insulator-metal capacitors, metal-oxide-metal capacitors, planar capacitors, or interdigital capacitors.
6. The high-isolation semiconductor single-pole double-throw switch based on transmission zero point according to claim 1, characterized in that, The transistor is a field-effect transistor, a high electron mobility transistor, an mHEMT, or a pHEMT transistor.