A post-weighted multi-bit input compute-in-memory circuit and method based on RRAM

Abstract

The application discloses a post-weighted multi-bit input memory and calculation circuit and method based on RRAM, comprising a plurality of parallel memory and calculation circuits, each memory and calculation circuit comprising a first clamping circuit, a first current mirror, a second clamping circuit, a second current mirror, a sampling capacitor and a multi-bit input weighting capacitor array, wherein one end of the first clamping circuit is connected with the first current mirror, one end of the second clamping circuit is connected with the second current mirror, the lower plate of the sampling capacitor is grounded, and the upper plate of the sampling capacitor is connected with the other end of the first current mirror, the other end of the second current mirror and the multi-bit input weighting capacitor array respectively. The application can realize multi-bit weighting operation of input data and weight data through current mirror technology and capacitor array, especially can complete post-weighting of input data through proportional capacitor values, save time consumed by data input, and improve data throughput and operation efficiency of the memory and calculation system.

Description

Technical Field

[0001] This invention relates to a post-weighted multi-bit input storage circuit and method based on RRAM, belonging to the technical field of multi-bit input storage circuits. Background Technology

[0002] Traditional multi-bit input memory (MIM) circuits use pulse width to represent input data weights. Taking the least significant bit as the baseline, the pulse width for the second bit is twice that of the least significant bit, the pulse width for the third bit is four times that of the least significant bit, and so on. The higher the bit, the larger the required pulse width, and the longer the data input time. Inputting a large number of bits using traditional methods consumes a significant amount of time, reduces the data processing speed of the MIM circuit, and severely limits the accuracy of the input data, the throughput of the MIM system, and its computational efficiency. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a post-weighted multi-bit input storage and computing circuit and method based on RRAM, which can perform operations on multiple bit input data in just one data input cycle, saving the time consumed by data input and improving the data throughput and computing efficiency of the storage and computing system.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical means:

[0005] In a first aspect, the present invention proposes a post-weighted multi-bit input memory circuit based on RRAM, comprising multiple parallel memory loops. Each memory loop includes a first clamping circuit, a first current mirror, a second clamping circuit, a second current mirror, a sampling capacitor, and a multi-bit input weighting capacitor array. The first clamping circuit is connected to one end of the first current mirror, the second clamping circuit is connected to one end of the second current mirror, the lower plate of the sampling capacitor is grounded, and the upper plate of the sampling capacitor is connected to the other end of the first current mirror, the other end of the second current mirror, and the multi-bit input weighting capacitor array, respectively.

[0006] The first clamping circuit and the second clamping circuit each include a first RRAM storage array and a second RRAM storage array, which are used to store single-bit weight data.

[0007] The multi-bit input weighted capacitor array includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and a third capacitor. One end of the first switch and one end of the second switch are connected in parallel to the upper plate of the sampling capacitor, respectively. The other end of the first switch is connected to one end of the fourth switch and the upper plate of the second capacitor, respectively. The other end of the second switch is connected to one end of the third switch and the upper plate of the first capacitor, respectively. The other ends of the third switch and the other ends of the fourth switch are connected to the upper plate of the third capacitor, respectively. The lower plates of the first capacitor, the second capacitor, and the third capacitor are grounded.

[0008] In conjunction with the first aspect, the first clamping circuit further includes a first transistor and a first power amplifier, the non-inverting input of the first power amplifier being connected to the clamping circuit reference voltage V. CLP The inverting input terminal of the first power amplifier is connected to the source terminal of the first transistor and the first RRAM storage array, respectively. The output terminal of the first power amplifier is connected to the gate terminal of the first transistor, and the drain terminal of the first transistor is connected to one end of the first current mirror.

[0009] The second clamping circuit also includes a fourth transistor and a second power amplifier, with the non-inverting input of the second power amplifier connected to the clamping circuit's reference voltage V. CLP The inverting input of the second power amplifier is connected to the source of the fourth transistor and the second RRAM storage array, respectively. The output of the second power amplifier is connected to the gate of the fourth transistor, and the drain of the fourth transistor is connected to one end of the second current mirror.

[0010] In conjunction with the first aspect, further, the first current mirror includes a second transistor and a third transistor. The source terminals of the second transistor and the third transistor are respectively connected to a power supply. The gate terminal of the second transistor is respectively connected to the drain terminal of the first transistor, the drain terminal of the second transistor, and the gate terminal of the third transistor. The drain terminal of the third transistor is connected to the upper plate of the sampling capacitor.

[0011] The second current mirror includes a fifth transistor and a sixth transistor. The source terminals of the fifth transistor and the sixth transistor are respectively connected to the power supply. The gate terminal of the fifth transistor is respectively connected to the drain terminal of the fourth transistor, the drain terminal of the fifth transistor, and the gate terminal of the sixth transistor. The drain terminal of the sixth transistor is connected to the upper plate of the sampling capacitor.

[0012] In conjunction with the first aspect, furthermore, the aspect ratio of the sixth transistor is twice that of the third transistor.

[0013] In conjunction with the first aspect, further, the capacitance of the first capacitor is twice the capacitance of the second capacitor, and the capacitance of the third capacitor is equal to the sum of the capacitances of the first and second capacitors.

[0014] Secondly, the present invention proposes a post-weighted multi-bit input storage method based on RRAM. This storage method is implemented based on a post-weighted multi-bit input storage circuit based on RRAM as described in the first aspect. For each storage loop in the post-weighted multi-bit input storage circuit, the method includes the following steps:

[0015] The bit line voltages V of the first RRAM storage array and the second RRAM storage array are respectively clamped by the first clamping circuit and the second clamping circuit. BL All clamped to the clamping circuit reference voltage V CLP ;

[0016] According to Ohm's law, the first bit line current and the second bit line current are obtained by the bit line voltage and resistance of the first RRAM memory array and the second RRAM memory array, where the first bit line current represents the unweighted weighted data of the first RRAM array and the second bit line current represents the unweighted weighted data of the second RRAM array.

[0017] The first current and the second current are mirrored according to the proportions of the first current mirror and the second current mirror to obtain the mirrored first current and second current.

[0018] The sampling capacitor is charged by the mirrored first and second currents to obtain the first sampling voltage and the second sampling voltage.

[0019] Close the first switch, open the second, third, and fourth switches, sample the first sampling voltage on the sampling capacitor into the second capacitor, then open the first switch, and store the result of the multiplication and accumulation of the lower bit input data and the two bits weighted data in the second capacitor in the form of charge.

[0020] Close the second switch, open the first, third, and fourth switches, sample the second sampling voltage on the sampling capacitor into the first capacitor, then open the second switch, and store the result of the multiplication and accumulation of the higher bit input data and the two-bit weighted data in the first capacitor in the form of charge.

[0021] When the third and fourth switches are closed and the first and second switches are opened, the charge stored in the first and second capacitors flows to the third capacitor under the influence of the potential difference, resulting in the product and summation of the two-bit input data and the two-bit weight data.

[0022] In conjunction with the second aspect, further, after closing the third and fourth switches, the voltage V on the upper plates of the first, second, and third capacitors... SUM for:

[0023]

[0024] Among them, V SUMThis is the voltage representation of the product and summation of two-bit input data and two-bit weighted data, where Q is the total charge stored in the first and second capacitors, and C is the total charge stored in the first and second capacitors. i0 Let C be the capacitance value of the first capacitor. i1 C is the capacitance value of the second capacitor. S This is the capacitance value of the third capacitor.

[0025] The following advantages can be obtained by adopting the above technical means:

[0026] This invention proposes a post-weighted multi-bit input in-memory computing circuit and method based on RRAM. It stores single-bit weight data using an RRAM storage array, and then uses current mirroring technology and a capacitor array to represent the multiplication and accumulation result of the input data and weight data in the form of current or voltage. This achieves multi-bit weighting of the input and weight data. During data input, this invention does not need to consider the weight information of the input data; each bit of the multi-bit input data can be treated as a single bit. The weighting operation of the input data is then performed through a post-weighted capacitor array, thus avoiding the need for multi-cycle pulse weighting at the input end, saving data input time, and improving the data throughput and computational efficiency of the in-memory computing system. Furthermore, by changing the number of parallel in-memory computing loops, this invention can expand to include the required multi-bit input and multi-bit weight data multiplication and accumulation operations, resulting in better circuit scalability, a simpler circuit structure, and easier widespread application. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the storage loop in a post-weighted multi-bit input storage circuit based on RRAM according to the present invention.

[0028] Figure 2 This is a waveform diagram of the calculation module of the post-weighted multi-bit input storage circuit in an embodiment of the present invention. Detailed Implementation

[0029] The technical solution of the present invention will be further described below with reference to the accompanying drawings:

[0030] Example 1:

[0031] This invention proposes a post-weighted multi-bit input memory circuit based on RRAM, comprising multiple parallel memory loops, such as... Figure 1 As shown, each memory-based loop includes a first clamping circuit, a first current mirror, a second clamping circuit, a second current mirror, and a sampling capacitor (C). CThe circuit comprises a first clamping circuit connected to one end of a first current mirror, a second clamping circuit connected to one end of a second current mirror, a sampling capacitor whose lower plate is connected to ground potential VSS, and whose upper plate is connected to the other ends of the first and second current mirrors and the multi-bit input weighting capacitor array. In this circuit, the first and second clamping circuits clamp the bit line voltage of the RRAM storage array to a specified voltage and output a bit line current capable of representing the weight of a single bit. The first and second current mirrors mirror the bit line currents output by the first and second clamping circuits proportionally. The sampling capacitor converts the weight data in current form into voltage form. The multi-bit input weighting capacitor array represents the weight of multi-bit input data in the capacitor array, enabling the computation of multi-bit input data.

[0032] The first clamping circuit includes a first transistor (M) M0 The system comprises a first power amplifier (A0) and a first RRAM memory array (RRAM0), with the non-inverting input of the first power amplifier connected to a clamping circuit reference voltage V. CLP The inverting input terminal of the first power amplifier is connected to the source terminal of the first transistor and the first RRAM storage array, respectively. The output terminal of the first power amplifier is connected to the gate terminal of the first transistor, and the drain terminal of the first transistor is connected to one end of the first current mirror.

[0033] The second clamping circuit includes a fourth transistor (M). M1 The second power amplifier (A1) and the second RRAM memory array (RRAM1) are connected, with the non-inverting input of the second power amplifier connected to the clamping circuit reference voltage V. CLP The inverting input of the second power amplifier is connected to the source of the fourth transistor and the second RRAM storage array, respectively. The output of the second power amplifier is connected to the gate of the fourth transistor, and the drain of the fourth transistor is connected to one end of the second current mirror.

[0034] In the first and second clamping circuits, the first and fourth transistors are NMOS transistors used to adjust the bit line current of the RRAM memory array. The first and second power amplifiers are used for high-gain error power amplification. The first and second RRAM memory arrays are used to store single-bit weighted data.

[0035] The first current mirror includes a second transistor (M) P0 ), third transistor (M) P1 The source terminals of the second transistor and the third transistor are connected to the power supply, respectively. The gate terminal of the second transistor is connected to the drain terminal of the first transistor, the drain terminal of the second transistor, and the gate terminal of the third transistor, respectively. The drain terminal of the third transistor is connected to the upper plate of the sampling capacitor.

[0036] The second current mirror includes the fifth transistor (M). P3 ) and the sixth transistor (M) P2 The source terminals of the fifth and sixth transistors are connected to the power supply, respectively. The gate terminal of the fifth transistor is connected to the drain terminal of the fourth transistor, the drain terminal of the fifth transistor, and the gate terminal of the sixth transistor, respectively. The drain terminal of the sixth transistor is connected to the upper plate of the sampling capacitor.

[0037] In the first and second current mirrors, M P0 M P1 M P2 M P3 All use PMOS transistors, the sixth transistor M P2 The aspect ratio is that of the third transistor M P1 It is twice the width-to-length ratio.

[0038] The multi-bit input weighted capacitor array includes a first switch (S0), a second switch (S1), a third switch (S2), a fourth switch (S3), and a first capacitor (C). I0 ), second capacitor (C) I1 ) and the third capacitor (C S One end of the first switch and one end of the second switch are connected in parallel to the upper plate of the sampling capacitor. The other end of the first switch is connected to one end of the fourth switch and the upper plate of the second capacitor. The other end of the second switch is connected to one end of the third switch and the upper plate of the first capacitor. The other ends of the third switch and the fourth switch are connected to the upper plate of the third capacitor. The lower plates of the first capacitor, the second capacitor, and the third capacitor are connected to the ground potential VSS.

[0039] In a multi-bit input weighted capacitor array, the first to fourth switches can be used to control the movement of charges in the capacitor array; the capacitance of the first capacitor is twice the capacitance of the second capacitor, and the capacitance of the third capacitor is equal to the sum of the capacitances of the first and second capacitors.

[0040] Example 2:

[0041] Based on the post-weighted multi-bit input memory circuit in Embodiment 1, this invention also proposes a post-weighted multi-bit input memory method. For each memory loop in the post-weighted multi-bit input memory circuit, the method includes the following steps:

[0042] Step A: The bit line voltage V of the first RRAM storage array and the second RRAM storage array are respectively clamped by the first clamping circuit and the second clamping circuit. BL0 V BL1 All clamped to the clamping circuit reference voltage V CLPClamping prevents deviations in the read RRAM array current caused by changes in the bit line voltage due to variations in the RRAM array resistance, thus avoiding large errors in the calculation results.

[0043] Step B: According to Ohm's law, the first bit line current and the second bit line current I are obtained on the bit line BL of the first and second RRAM memory arrays through the bit line voltage and resistance of the first and second RRAM memory arrays. BL The first bit current represents the unweighted weighted data of the first RRAM array, and the second bit current represents the unweighted weighted data of the second RRAM array.

[0044] Step C: Using the first current mirror and the second current mirror, perform mirroring and weighting operations on the first and second line currents according to the ratio to obtain the mirrored first current I. BL0 Second current I BL1 Through transistor M P0 and M P1 (M P2 and M P3 A current mirror composed of [components] mirrors the bit line currents of the RRAM array to the M [array]. P1 (M P3 The current branch where the transistor is located is used to represent the multi-bit weight.

[0045] like Figure 1 As shown, transistor M P1 Mirror flow through transistor M P0 The current is I BL0 This represents the weighted data of the lower bit; transistor M P2 Mirror flow through transistor M P3 The current is I BL1 And due to transistor M P2 The channel width-to-length ratio is the transistor M P1 twice that, so I BL1 This represents the weight data of the higher bit.

[0046] Step D: Charge the sampling capacitor with the mirrored first current and second current to obtain the first sampling voltage and the second sampling voltage. The first sampling voltage is the voltage representation of the product and accumulation result of the lower bit input data and the two-bit weighted data, and the second sampling voltage is the voltage representation of the product and accumulation result of the higher bit input data and the two-bit weighted data.

[0047] Step E: When calculating the lower bit of the input data and the two-bit weight data, the input data is represented by the opening / closing of the first switch. The first switch is closed, and the second, third, and fourth switches are opened. The first sampling voltage on the sampling capacitor is sampled into the second capacitor. Then the first switch is opened, and the result of the multiplication and accumulation of the lower bit of the input data and the two-bit weight data is stored in the second capacitor in the form of charge.

[0048] Step F: When calculating the higher bit of the input data and the two-bit weight data, the input data is represented by the opening / closing of the second switch. The second switch is closed, and the first, third, and fourth switches are opened. The second sampling voltage on the sampling capacitor is sampled into the first capacitor. Then the second switch is opened, and the result of the multiplication and accumulation of the higher bit of the input data and the two-bit weight data is stored in the first capacitor in the form of charge.

[0049] Step G: Close the third and fourth switches and open the first and second switches. Initially, since the potential of the upper plate of the first and second capacitors is higher than that of the upper plate of the third capacitor, the charge stored in the first and second capacitors will flow to the third capacitor under the influence of the potential difference. As a result, the multiplication and accumulation of the two-bit input data and the two-bit weight data are obtained on the third capacitor.

[0050] Assuming the total charge stored in the first and second capacitors is Q, then after closing the third and fourth switches, the voltage values ​​V on the upper plates of the first, second, and third capacitors will be... SUM for:

[0051]

[0052] Among them, V SUM C is the voltage representation of the product and summation of two-bit input data and two-bit weighted data. i0 Let C be the capacitance value of the first capacitor. i1 C is the capacitance value of the second capacitor. S This is the capacitance value of the third capacitor.

[0053] Because the capacitance of the first capacitor is twice that of the second capacitor, sampling the calculation result of the higher bit input data and weight data onto the first capacitor in the form of voltage is equivalent to doubling the weight of its input bits. Sampling the calculation result of the lower bit input data and weight data onto the second capacitor in the form of voltage is equivalent to doubling the weight of its input bits. Finally, by connecting the upper plates of the first, second, and third capacitors, it is equivalent to adding the calculation results of two bits, thus obtaining the product and sum of the two-bit input data and the two-bit weight data.

[0054] According to the method of the present invention, theoretically, multiplication and accumulation operations of input data and weight data of any number of bits can be performed. In the embodiments of the present invention, the principle is described only through multiplication and accumulation operations of two-bit input data and two-bit weight data.

[0055] Figure 2 The waveform diagram shows the calculation mode of the RRAM storage circuit with post-multi-bit input. The V1 indicator line represents the sum of the weighted data bits, presented as a voltage of 32.707mV on the sampling capacitor C. C Above; the indicator line V2 indicates that switch S0 is turned on, and the sampling capacitor C is connected. C The voltage on the capacitor C is sampled. I1 Above; the indicator line V3 indicates that switch S1 is turned on, and the sampling capacitor C is connected. C The voltage on the capacitor C is sampled. I0 Above; the indicator line V4 indicates that switches S3 and S4 are turned on simultaneously, and capacitor C is connected. I1 and C I0 Charge is transferred to capacitor C S In the process, a weighted calculation is performed to obtain the correct weighted result; the identifier V5 indicates that in the case of no reset, the capacitor C I1 C I0 and C S The potential of the upper plate remains constant, from Figure 2 It can be seen that the circuit and method of the present invention function correctly.

[0056] Compared with the prior art, the memory computing circuit and method of the present invention have the following advantages:

[0057] First, this invention can perform weighted expansion of weighted data through a current mirror structure, and can perform weighted expansion of input data through a multi-bit input weighted capacitor array structure, employing a single... Figure 1 The storage loop shown can perform multiplication and accumulation operations on two-bit input data and two-bit weight data, using two... Figure 1 The parallel structure of the storage-computing circuit shown can perform multiplication and accumulation operations on four-bit input data and two-bit weight data. Similarly, it can be extended to multiplication and accumulation operations on multiple-bit input and multiple-bit weight data as needed according to the actual computing environment. Therefore, the circuit of the present invention has better scalability.

[0058] Secondly, this invention can achieve multi-bit weighting of input data and weight data using only current mirror technology and capacitor array. Compared with existing circuit structures, the circuit structure of this invention is simpler and has lower production difficulty and cost.

[0059] Finally, the present invention can perform post-weighting of input data by proportional capacitance value. Therefore, when inputting data, there is no need to consider the weight information of the input data. Each bit of the multi-bit input data can be regarded as a single bit data. This can effectively avoid the weighting operation of input data in the form of multi-cycle pulses at the input end, saving data input time and thus improving the data throughput and computing efficiency of the in-memory computing system.

[0060] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A post-weighted multi-bit input storage circuit based on RRAM, characterized in that, It includes multiple parallel memory-based computing loops. Each memory-based computing loop includes a first clamping circuit, a first current mirror, a second clamping circuit, a second current mirror, a sampling capacitor, and a multi-bit input weighting capacitor array. The first clamping circuit is connected to one end of the first current mirror, the second clamping circuit is connected to one end of the second current mirror, the lower plate of the sampling capacitor is grounded, and the upper plate of the sampling capacitor is connected to the other end of the first current mirror, the other end of the second current mirror, and the multi-bit input weighting capacitor array, respectively. The first clamping circuit and the second clamping circuit each include a first RRAM storage array and a second RRAM storage array, which are used to store single-bit weight data. The multi-bit input weighted capacitor array includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and a third capacitor. One end of the first switch and one end of the second switch are connected in parallel to the upper plate of the sampling capacitor, respectively. The other end of the first switch is connected to one end of the fourth switch and the upper plate of the second capacitor, respectively. The other end of the second switch is connected to one end of the third switch and the upper plate of the first capacitor, respectively. The other ends of the third switch and the other ends of the fourth switch are connected to the upper plate of the third capacitor, respectively. The lower plates of the first capacitor, the second capacitor, and the third capacitor are grounded.

2. The post-weighted multi-bit input storage circuit based on RRAM according to claim 1, characterized in that, The first clamping circuit further comprises a first transistor and a first power amplifier, a positive input end of the first power amplifier is connected with a clamping circuit reference voltage V CLP , a negative input end of the first power amplifier is respectively connected with a source end of the first transistor and a first RRAM storage array, an output end of the first power amplifier is connected with a gate end of the first transistor, and a drain end of the first transistor is connected with one end of a first current mirror; The second clamping circuit also includes a fourth transistor and a second power amplifier, with the non-inverting input of the second power amplifier connected to the clamping circuit's reference voltage V. CLP The inverting input of the second power amplifier is connected to the source of the fourth transistor and the second RRAM storage array, respectively. The output of the second power amplifier is connected to the gate of the fourth transistor, and the drain of the fourth transistor is connected to one end of the second current mirror.

3. The post-weighted multi-bit input storage circuit based on RRAM according to claim 2, characterized in that, The first current mirror includes a second transistor and a third transistor. The source terminals of the second transistor and the third transistor are respectively connected to a power supply. The gate terminal of the second transistor is respectively connected to the drain terminal of the first transistor, the drain terminal of the second transistor, and the gate terminal of the third transistor. The drain terminal of the third transistor is connected to the upper plate of the sampling capacitor. The second current mirror includes a fifth transistor and a sixth transistor. The source terminals of the fifth transistor and the sixth transistor are respectively connected to the power supply. The gate terminal of the fifth transistor is respectively connected to the drain terminal of the fourth transistor, the drain terminal of the fifth transistor, and the gate terminal of the sixth transistor. The drain terminal of the sixth transistor is connected to the upper plate of the sampling capacitor.

4. The post-weighted multi-bit input storage circuit based on RRAM according to claim 3, characterized in that, The aspect ratio of the sixth transistor is twice that of the third transistor.

5. The post-weighted multi-bit input storage circuit based on RRAM according to claim 1, characterized in that, The capacitance of the first capacitor is twice that of the second capacitor, and the capacitance of the third capacitor is equal to the sum of the capacitances of the first and second capacitors.

6. A post-weighted multi-bit input storage and computation method based on RRAM, characterized in that, The storage method is implemented based on a post-weighted multi-bit input storage circuit based on RRAM as described in any one of claims 1 to 5. For each storage loop in the post-weighted multi-bit input storage circuit, the method includes the following steps: The bit line voltages V of the first RRAM storage array and the second RRAM storage array are respectively clamped by the first clamping circuit and the second clamping circuit. BL All clamped to the clamping circuit reference voltage V CLP ; According to Ohm's law, the first bit line current and the second bit line current are obtained by the bit line voltage and resistance of the first RRAM memory array and the second RRAM memory array, where the first bit line current represents the unweighted weighted data of the first RRAM array and the second bit line current represents the unweighted weighted data of the second RRAM array. The first current and the second current are mirrored according to the proportions of the first current mirror and the second current mirror to obtain the mirrored first current and second current. The sampling capacitor is charged by the mirrored first and second currents to obtain the first sampling voltage and the second sampling voltage. Close the first switch, open the second, third, and fourth switches, sample the first sampling voltage on the sampling capacitor into the second capacitor, then open the first switch, and store the result of the multiplication and accumulation of the lower bit input data and the two bits weighted data in the second capacitor in the form of charge. Close the second switch, open the first, third, and fourth switches, sample the second sampling voltage on the sampling capacitor into the first capacitor, then open the second switch, and store the result of the multiplication and accumulation of the higher bit input data and the two-bit weighted data in the first capacitor in the form of charge. When the third and fourth switches are closed and the first and second switches are opened, the charge stored in the first and second capacitors flows to the third capacitor under the influence of the potential difference, resulting in the product and summation of the two-bit input data and the two-bit weight data.

7. The post-weighted multi-bit input storage method based on RRAM according to claim 6, characterized in that, After closing the third and fourth switches, the voltage V on the upper plates of the first, second, and third capacitors... SUM for: Among them, V SUM This is the voltage representation of the product and summation of two-bit input data and two-bit weighted data, where Q is the total charge stored in the first and second capacitors, and C is the total charge stored in the first and second capacitors. i0 Let C be the capacitance value of the first capacitor. i1 C is the capacitance value of the second capacitor. S This is the capacitance value of the third capacitor.

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