Nand flash power down test apparatus, power down test method, and storage medium

Abstract

The application discloses a nand flash power-off test device, a power-off test method and a storage medium, wherein the power-off test device comprises a Device device as a power-off test object and a Host device as a power-off test machine, the Device device comprises a NAND Flash module; the Host device is connected with the NAND Flash module, and the Host device is used for sending a first driving command to a raw NAND to control a target physical block and / or a target page in the raw NAND to perform a power-off test in the case of the raw NAND; and in the case of a NAND chip comprising a flash controller, a first indication command is sent to the flash controller of the NAND chip to instruct the flash controller to determine the target physical block and / or the target page to perform the power-off test, so that the hit probability and the test efficiency of the power-off test are improved.

Description

Technical Field

[0001] This application relates to the field of memory chip technology, and in particular to a NAND flash power-down testing device, power-down testing method, and storage medium. Background Technology

[0002] Memory chips manufactured using SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology have a special structure, such as... Figure 1 As shown, each memory cell in a memory chip consists of a control transistor (or simply control transistor) and a storage transistor (or simply data transistor). The electrical characteristics of the memory cell are controlled by SWL (SEL - word line control signal) and WL (word line), thereby reading the output current of the memory cell on BL (bit line) to realize data reading and writing.

[0003] Currently, when a memory chip detects an error in a memory cell during a programming-erase operation, it typically completes the current operation first and records the address of the defective memory cell. Then, it performs a replacement operation on those memory cells. Since the replacement operation and the programming-erase operation are separate, the test machine is required to exchange information with the memory chip multiple times. This includes the test machine sending instructions to the memory chip, the memory chip returning test results, the test machine sending replacement instructions, and the memory chip returning replacement operation results, etc. This results in insufficient testing efficiency and places high demands on the performance of the test machine. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a NAND flash power-down testing device, power-down testing method, and storage medium, which can simplify the instructions in the power-down testing process and can also specify target physical blocks and / or target pages in the NAND Flash for power-down testing, thereby improving the hit probability and testing efficiency of power-down testing.

[0006] In a first aspect, embodiments of this application provide a NAND flash power-down testing device, comprising:

[0007] Devices used for power-down testing include NAND Flash modules;

[0008] The host device, acting as a power-down tester, is connected to the NAND Flash module. The host device is used for:

[0009] When the NAND Flash module is a raw NAND, a first drive command is sent to the raw NAND to control the power-down scenario and timing of the target physical block and / or target page in the raw NAND;

[0010] In the case where the NAND Flash module is a NAND chip containing a flash memory controller, a first instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to determine the power-down scenario and timing of the target physical block and / or target page.

[0011] In some embodiments, the Host device includes an application processor that is communicatively connected to the Device device and supplies power to the Device device.

[0012] In some embodiments, the Host device is further configured to:

[0013] When the NAND Flash module is a raw NAND, after the power-down test is completed, a second drive command is sent to the raw NAND to perform a read test on the target physical block and / or target page;

[0014] In the case where the NAND Flash module is a NAND chip containing a flash memory controller, after the power-down test is completed, a second instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and / or the target page.

[0015] Secondly, this application also provides a NAND flash power-down testing method, applied to the Host device in the NAND flash power-down testing apparatus of the first aspect embodiment, the power-down testing method comprising:

[0016] When the NAND Flash module is a raw NAND, a first drive command is sent to the raw NAND to control the power-down scenario and timing of the target physical block and / or target page in the raw NAND;

[0017] or,

[0018] In the case where the NAND Flash module is a NAND chip containing a flash memory controller, a first instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to determine the power-down scenario and timing of the target physical block and / or target page.

[0019] In some embodiments, sending the first drive command to the raw NAND includes:

[0020] The target physical block and / or target page in the raw NAND are programmed according to the power-down test case, wherein the power-down test case includes a preset power-down timing and the address of the target physical block and / or target page;

[0021] During the programming process, the device is powered off according to a preset power-off timing.

[0022] In some embodiments, sending a first instruction command to the flash memory controller of the NAND chip includes:

[0023] A power-down test case is sent to the flash memory controller to instruct the flash memory controller to run the power-down test case, which includes a preset power-down timing and the address of the target physical block and / or target page;

[0024] When a power-down notification is received from the flash memory controller, the power supply to the device is cut off.

[0025] In some embodiments, the preset power-off timing is the moment when the NAND Flash module is in a busy state of programming operation, or the moment when the NAND Flash module is in a busy state of programming operation and there is a delay for a period of time.

[0026] In some embodiments, it also includes:

[0027] Once the power failure of the device is detected to be complete, power the device back on.

[0028] Once the entire power-down test is complete, a second drive command is sent to the raw NAND to perform a read test on the target physical block and / or target page.

[0029] In some embodiments, it also includes:

[0030] Once the power failure of the device is detected to be complete, power the device back on.

[0031] Once the entire power-down test is complete, a second instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and / or target page.

[0032] Thirdly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the power-down test method as described in the second aspect embodiment.

[0033] The NAND flash power-down testing device, power-down testing method, and storage medium provided in this application have at least the following beneficial effects: By constructing a Host-Device as a testing platform, and sending test commands from the Host to the Device, the Host can perform a complete power-down test on the Device while the NAND Flash is in the programming state; This application embodiment can perform power-down tests on specific physical block and page locations and specific programming times of the NAND Flash, improving the hit probability and testing efficiency of power-down tests; In addition, after power-down testing of the target physical block and target page, the target physical block and target page can be read and tested to obtain more fundamental power-down test data.

[0034] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0035] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and form part of the specification. They are used together with the examples of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0036] Figure 1 This is a schematic diagram of the power-off testing device provided in the embodiments of this application;

[0037] Figure 2 This is a flowchart of the power-down test method for raw NAND provided in the embodiments of this application;

[0038] Figure 3 This is a flowchart of a power-down test method for a NAND chip including a flash memory controller, provided in an embodiment of this application.

[0039] Figure 4 This is a flowchart of the power-off process method for raw NAND provided in the embodiments of this application;

[0040] Figure 5 This is a flowchart of a power-off process method for a NAND chip including a flash memory controller, provided in an embodiment of this application.

[0041] Figure 6This is a flowchart of a raw NAND power-down-power-on and read test provided in an embodiment of this application;

[0042] Figure 7 This is a flowchart of a NAND chip including a flash memory controller undergoing a power-down-power-on and read test, as provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] Existing NAND Flash power-loss testing methods mainly include product-level power-loss testing, such as SSD and eMMC file power-loss testing. Product-level power-loss testing primarily involves the CPU / APU connected to the module sending a series of commands according to the corresponding communication protocol to make the module operate normally in various states such as read, write, and erase, and then randomly cutting off the power supply to the module to complete a single module power-loss test. This process is repeated until the set power-loss test standard is reached, at which point the power-loss test is complete.

[0045] The existing solutions mentioned above have some shortcomings:

[0046] (1) It is not possible to perform power-down tests on specific physical blocks, page locations, or specific programming times of NAND Flash;

[0047] (2) It is impossible to perform correlation analysis between NAND Flash characteristics and physical structure characteristics for NAND Flash that has experienced abnormal data loss due to power failure.

[0048] (3) The probability of hitting the target during a power outage and the efficiency of the power outage test are relatively low.

[0049] Based on this, embodiments of this application provide a NAND flash power-down testing device, power-down testing method, and storage medium, which can perform power-down testing at specific times for target physical blocks and target pages, and simplify the command interaction of the power-down testing process through commands between host and device, thereby improving the hit probability and testing efficiency of power-down testing.

[0050] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0051] Reference Figure 1 According to (a) and (b), a first aspect of this application provides a NAND flash power-down testing apparatus, comprising:

[0052] Devices used for power-down testing include NAND Flash modules;

[0053] The host device, acting as a power-down tester, connects to the NAND Flash module. The host device is used for:

[0054] When the NAND Flash module is raw NAND, a first drive command is sent to the raw NAND to control the power-down scenario and timing of the target physical block and / or target page in the raw NAND;

[0055] In the case where the NAND Flash module is a NAND chip containing a flash memory controller, a first instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to determine the power-down scenario and timing of the target physical block and / or target page.

[0056] This application embodiment constructs a Host-Device device as a test platform. It utilizes communication between the Host and Device to achieve a complete power-down test by completely de-energizing the Device while the NAND Flash is in the programming state. Specifically, the Device refers to raw NAND or a module with embedded NAND Flash and a flash memory controller, such as eMMC, UFS, or SSD. It is primarily responsible for communicating with the Host or driving the NAND Flash (except for raw NAND, which is directly driven by the Host for power-down testing). The Host is generally an Application Processor Unit (APU), responsible for powering the Device and enabling communication between Devices or driving the NAND Flash (if the Device is raw NAND, the Host needs to drive the NAND Flash; if the Device is a module with embedded NAND Flash, the Host does not need to drive the NAND Flash, but instead sends commands to the flash memory controller).

[0057] Therefore, for raw NAND, the host directly executes the power-down test via the first drive command, specifying the target physical block or target page, and then writes preset test data through programming operations. During the programming operation, the raw NAND is directly powered off, thus completing one power-down test. Afterward, the host continues to power on the device and repeats the programming-power-down process until the entire power-down test is completed. For NAND chips containing a flash memory controller, the host indirectly executes the power-down test via the first instruction command. The host instructs the device to execute a predetermined power-down test process. The flash memory controller internally programs the target physical block or specified target page according to the first instruction command. The flash memory controller controls the power-down timing and notifies the host to power off when the power-down timing is reached. Therefore, the host does not directly execute the power-down test. Compared to current power-down testing schemes, the Host-Device communication in this embodiment does not require complex internal software layer calculations and conversions, which greatly reduces latency and increases the flexibility of power-down timing selection.

[0058] It is understood that the first drive command, first indication command, etc. in the embodiments of this application are not standard protocol commands corresponding to NAND Flash. Standard protocol commands obviously cannot achieve the power-down test of this solution. Therefore, the embodiments of this application adjust the NAND Flash driver and specify the target physical block or the target page through private commands (first drive command, first indication command, etc.). The number of commands sent by the host is small. For NAND chips containing flash controllers, the private commands directly instruct the flash controller to control the power-down timing, rather than the host directly controlling it. The device runs in a non-firware environment without any background operations, which improves the response speed and thus greatly improves the test efficiency.

[0059] Therefore, it can be seen that the host device includes an application processor, which communicates with the device and supplies power to it. In other words, the power-off operation is performed by the host.

[0060] The Host device is also used for:

[0061] When the NAND Flash module is raw NAND, after the power-down test is completed, a second drive command is sent to the raw NAND to perform a read test on the target physical block and / or the target page.

[0062] When the NAND Flash module is a NAND chip containing a flash memory controller, after the power-down test is completed, a second instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and / or the target page.

[0063] Since the host can specify which physical blocks and pages in the NAND Flash are subject to power-down testing and which are normally programmed blocks and pages each time it sends a power-down test command, the host can send commands to the device to read the data, threshold voltage distribution, and other information of the physical blocks and pages of the NAND Flash being tested. This allows the host to visually observe whether the NAND Flash has experienced abnormal data loss due to power loss.

[0064] Reference Figure 2 and Figure 3 The second aspect of this application provides a NAND flash power-down testing method, applied to the host device in the NAND flash power-down testing apparatus of the first aspect embodiment. The power-down testing method includes:

[0065] Step S100: When the NAND Flash module is a raw NAND, send a first drive command to the raw NAND to control the power-down scenario and timing of the target physical block and / or target page in the raw NAND.

[0066] or,

[0067] Step S200: If the NAND Flash module is a NAND chip containing a flash memory controller, a first instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to determine the power-down scenario and timing of the target physical block and / or target page.

[0068] Similarly, the power-down testing method in the second aspect embodiment also involves the host performing a power-down test on the raw NAND or instructing the flash memory controller to perform a power-down test via a first drive command or a first instruction command. For details, please refer to the description of the first aspect embodiment, which will not be repeated here.

[0069] Reference Figure 4 For step S100, sending the first drive command to the raw NAND can specifically include the following steps:

[0070] Step S110: Program the target physical block and / or target page in the raw NAND according to the power-down test case. The power-down test case includes the preset power-down timing and the address of the target physical block and / or target page.

[0071] Step S120: During the programming process, the device is powered off according to the preset power-off timing.

[0072] Reference Figure 5 Sending the first instruction command to the flash memory controller of the NAND chip in step S200 may specifically include the following steps:

[0073] Step S210: Send the power-down test case to the flash memory controller to instruct the flash memory controller to run the power-down test case. The power-down test case includes a preset power-down timing and the address of the target physical block and / or the target page.

[0074] Step S220: When a power-down notification is received from the flash memory controller, the power supply to the Device is cut off.

[0075] For both raw NAND and NAND chips with flash controllers, preset power-down timings can be set through power-down test cases, and the addresses of target physical blocks and / or target pages can be specified. In the case of raw NAND, the host directly controls the power-down test process. In the case of NAND chips with flash controllers, the flash controller controls the power-down scenarios and timings, and notifies the host to perform a power-down when necessary. Upon receiving the notification, the host immediately cuts off the power supply to the device.

[0076] Different power-down timings can be set. For example, the preset power-down timing can be the moment when the NAND Flash module is in the busy state of programming operation, or the moment when the NAND Flash module is in the busy state of programming operation with a delay. NAND Flash programming states are divided into Ready and Busy. Traditional power-down testing processes rely on the host to determine the power-down timing. Since it's unclear whether the NAND Flash is currently in the Ready or Busy state (power-down in the Busy state is only a valid power-down test), the hit rate is not high. This application directly connects the host to the raw NAND or delegates the power-down timing to the flash memory controller, clearly knowing the current programming state and avoiding the problem of low hit rate. Based on this, embodiments of this application can also set a delay (e.g., 100 microseconds) after the actual power-down timing, and then notify the host to power off the device. By specifying this delay parameter, the NAND Flash can be completely powered down at different specific moments during programming.

[0077] Reference Figure 6 In one embodiment, in the case of raw NAND, after the power-down test is completed, the following steps are also included:

[0078] Step S310: When the power failure of the Device is detected to be complete, power on the Device again.

[0079] Step S320: Once the entire power-down test is complete, send a second drive command to the raw NAND to perform a read test on the target physical block and / or target page.

[0080] Reference Figure 7 In one embodiment, when the NAND chip includes a flash memory controller, the process after the power-down test is completed further includes:

[0081] Step S410: When the power failure of the Device is detected to be complete, power on the Device again.

[0082] Step S420: When the entire power-down test is completed, a second instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and / or the target page.

[0083] Each time a power-down occurs on a target physical block and / or target page, the host powers the device back on to initiate the next power-down, until the required number of power-downs is met or all addresses in the NAND Flash have been traversed. Afterward, a read test is performed, causing the device to read data from the physical block page of the test NAND Flash, including threshold voltage distribution, allowing for direct observation of whether any abnormal data loss has occurred due to power-down.

[0084] This application also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a power-down test method as described in the second aspect embodiment.

[0085] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0086] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0087] It should be understood that in the description of the embodiments of this application, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0089] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0090] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0091] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0093] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A NAND flash power-down testing device, characterized in that, include: Devices used for power-down testing include NAND Flash modules; The host device, acting as a power-down tester, is connected to the NAND Flash module. The host device is used for: When the NAND Flash module is a raw NAND, a first drive command is sent to the raw NAND to control the power-down scenario and timing of the target physical block and / or target page in the raw NAND; In the case where the NAND Flash module is a NAND chip containing a flash memory controller, a first instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to determine the power-down scenario and timing of the target physical block and / or target page; The first driving command and the first instruction command both set the preset power-down timing and the address of the target physical block and / or the target page through power-down test cases; The preset power-off timing is either when the NAND Flash module is in a busy state during programming operations, or when the NAND Flash module is in a busy state during programming operations with a delay of a certain period of time.

2. The power failure testing device according to claim 1, characterized in that, The host device includes an application processor that is communicatively connected to the device and supplies power to the device.

3. The power failure testing device according to claim 2, characterized in that, The Host device is also used for: When the NAND Flash module is a raw NAND, after the power-down test is completed, a second drive command is sent to the raw NAND to perform a read test on the target physical block and / or target page; In the case where the NAND Flash module is a NAND chip containing a flash memory controller, after the power-down test is completed, a second instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and / or the target page.

4. A method for testing the power-down state of NAND flash memory, characterized in that, The power-down test method, applied to the host device in the NAND flash power-down test apparatus as described in any one of claims 1 to 3, comprises: When the NAND Flash module is a raw NAND, a first drive command is sent to the raw NAND to control the power-down scenario and timing of the target physical block and / or target page in the raw NAND; or, In the case where the NAND Flash module is a NAND chip containing a flash memory controller, a first instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to determine the power-down scenario and timing of the target physical block and / or target page; The first drive command and the first instruction command both set a preset power-down timing and the address of the target physical block and / or the target page through power-down test cases; the preset power-down timing is the moment when the NAND Flash module is in the busy state of programming operation, or the moment when the NAND Flash module is in the busy state of programming operation and delayed for a period of time.

5. The power-off test method according to claim 4, characterized in that, Sending the first drive command to the raw NAND includes: The target physical block and / or target page in the raw NAND are programmed according to the power-down test case, wherein the power-down test case includes a preset power-down timing and the address of the target physical block and / or target page; During the programming process, the device is powered off according to a preset power-off timing.

6. The power-off test method according to claim 4, characterized in that, Sending the first instruction command to the flash memory controller of the NAND chip includes: A power-down test case is sent to the flash memory controller to instruct the flash memory controller to run the power-down test case, which includes a preset power-down timing and the address of the target physical block and / or target page; When a power-down notification is received from the flash memory controller, the power supply to the device is cut off.

7. The power-off test method according to claim 5, characterized in that, Also includes: Once the power failure of the device is detected to be complete, power the device back on. Once the entire power-down test is complete, a second drive command is sent to the raw NAND to perform a read test on the target physical block and / or target page.

8. The power-off test method according to claim 6, characterized in that, Also includes: Once the power failure of the device is detected to be complete, power the device back on. Once the entire power-down test is complete, a second instruction command is sent to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and / or target page.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the power-down test method as described in any one of claims 4 to 8.

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